1/*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#ifndef __UMC_V6_7_H__
24#define __UMC_V6_7_H__
25
26#include "soc15_common.h"
27#include "amdgpu.h"
28
29/* EccErrCnt max value */
30#define UMC_V6_7_CE_CNT_MAX 0xffff
31/* umc ce interrupt threshold */
32#define UMC_V6_7_CE_INT_THRESHOLD 0xffff
33/* umc ce count initial value */
34#define UMC_V6_7_CE_CNT_INIT (UMC_V6_7_CE_CNT_MAX - UMC_V6_7_CE_INT_THRESHOLD)
35
36#define UMC_V6_7_INST_DIST 0x40000
37
38/* number of umc channel instance with memory map register access */
39#define UMC_V6_7_UMC_INSTANCE_NUM 4
40/* number of umc instance with memory map register access */
41#define UMC_V6_7_CHANNEL_INSTANCE_NUM 8
42/* total channel instances in one umc block */
43#define UMC_V6_7_TOTAL_CHANNEL_NUM (UMC_V6_7_CHANNEL_INSTANCE_NUM * UMC_V6_7_UMC_INSTANCE_NUM)
44/* one piece of normalizing address is mapped to 8 pieces of physical address */
45#define UMC_V6_7_NA_MAP_PA_NUM 8
46/* R14 bit shift should be considered, double the number */
47#define UMC_V6_7_BAD_PAGE_NUM_PER_CHANNEL (UMC_V6_7_NA_MAP_PA_NUM * 2)
48/* The CH4 bit in SOC physical address */
49#define UMC_V6_7_PA_CH4_BIT 12
50/* The C2 bit in SOC physical address */
51#define UMC_V6_7_PA_C2_BIT 17
52/* The R14 bit in SOC physical address */
53#define UMC_V6_7_PA_R14_BIT 34
54/* UMC regiser per channel offset */
55#define UMC_V6_7_PER_CHANNEL_OFFSET 0x400
56
57/* XOR bit 20, 25, 34 of PA into CH4 bit (bit 12 of PA),
58 * hash bit is only effective when related setting is enabled
59 */
60#define CHANNEL_HASH(channel_idx, pa) (((channel_idx) >> 4) ^ \
61 (((pa) >> 20) & 0x1ULL & adev->df.hash_status.hash_64k) ^ \
62 (((pa) >> 25) & 0x1ULL & adev->df.hash_status.hash_2m) ^ \
63 (((pa) >> 34) & 0x1ULL & adev->df.hash_status.hash_1g))
64#define SET_CHANNEL_HASH(channel_idx, pa) do { \
65 (pa) &= ~(0x1ULL << UMC_V6_7_PA_CH4_BIT); \
66 (pa) |= (CHANNEL_HASH(channel_idx, pa) << UMC_V6_7_PA_CH4_BIT); \
67 } while (0)
68
69extern struct amdgpu_umc_ras umc_v6_7_ras;
70extern const uint32_t
71 umc_v6_7_channel_idx_tbl_second[UMC_V6_7_UMC_INSTANCE_NUM][UMC_V6_7_CHANNEL_INSTANCE_NUM];
72extern const uint32_t
73 umc_v6_7_channel_idx_tbl_first[UMC_V6_7_UMC_INSTANCE_NUM][UMC_V6_7_CHANNEL_INSTANCE_NUM];
74void umc_v6_7_convert_error_address(struct amdgpu_device *adev,
75 struct ras_err_data *err_data, uint64_t err_addr,
76 uint32_t ch_inst, uint32_t umc_inst);
77#endif
78

source code of linux/drivers/gpu/drm/amd/amdgpu/umc_v6_7.h