1/*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include <linux/slab.h>
25#include <linux/module.h>
26#include <linux/pci.h>
27
28#include "amdgpu.h"
29#include "amdgpu_atombios.h"
30#include "amdgpu_ih.h"
31#include "amdgpu_uvd.h"
32#include "amdgpu_vce.h"
33#include "amdgpu_ucode.h"
34#include "amdgpu_psp.h"
35#include "amdgpu_smu.h"
36#include "atom.h"
37#include "amd_pcie.h"
38
39#include "gc/gc_11_0_0_offset.h"
40#include "gc/gc_11_0_0_sh_mask.h"
41#include "mp/mp_13_0_0_offset.h"
42
43#include "soc15.h"
44#include "soc15_common.h"
45#include "soc21.h"
46#include "mxgpu_nv.h"
47
48static const struct amd_ip_funcs soc21_common_ip_funcs;
49
50/* SOC21 */
51static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_vcn0[] = {
52 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},
53 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)},
54 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
55};
56
57static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_vcn1[] = {
58 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},
59 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)},
60};
61
62static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode_vcn0 = {
63 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_encode_array_vcn0),
64 .codec_array = vcn_4_0_0_video_codecs_encode_array_vcn0,
65};
66
67static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode_vcn1 = {
68 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_encode_array_vcn1),
69 .codec_array = vcn_4_0_0_video_codecs_encode_array_vcn1,
70};
71
72static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decode_array_vcn0[] = {
73 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
74 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
75 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},
76 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
77 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
78};
79
80static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decode_array_vcn1[] = {
81 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
82 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
83 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},
84 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
85};
86
87static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode_vcn0 = {
88 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_decode_array_vcn0),
89 .codec_array = vcn_4_0_0_video_codecs_decode_array_vcn0,
90};
91
92static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode_vcn1 = {
93 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_decode_array_vcn1),
94 .codec_array = vcn_4_0_0_video_codecs_decode_array_vcn1,
95};
96
97/* SRIOV SOC21, not const since data is controlled by host */
98static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_encode_array_vcn0[] = {
99 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},
100 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)},
101 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
102};
103
104static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_encode_array_vcn1[] = {
105 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},
106 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)},
107};
108
109static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_encode_vcn0 = {
110 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn0),
111 .codec_array = sriov_vcn_4_0_0_video_codecs_encode_array_vcn0,
112};
113
114static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_encode_vcn1 = {
115 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn1),
116 .codec_array = sriov_vcn_4_0_0_video_codecs_encode_array_vcn1,
117};
118
119static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_decode_array_vcn0[] = {
120 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
121 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
122 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},
123 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
124 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
125};
126
127static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_decode_array_vcn1[] = {
128 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
129 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
130 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},
131 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
132};
133
134static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_decode_vcn0 = {
135 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn0),
136 .codec_array = sriov_vcn_4_0_0_video_codecs_decode_array_vcn0,
137};
138
139static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_decode_vcn1 = {
140 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn1),
141 .codec_array = sriov_vcn_4_0_0_video_codecs_decode_array_vcn1,
142};
143
144static int soc21_query_video_codecs(struct amdgpu_device *adev, bool encode,
145 const struct amdgpu_video_codecs **codecs)
146{
147 if (adev->vcn.num_vcn_inst == hweight8(adev->vcn.harvest_config))
148 return -EINVAL;
149
150 switch (amdgpu_ip_version(adev, ip: UVD_HWIP, inst: 0)) {
151 case IP_VERSION(4, 0, 0):
152 case IP_VERSION(4, 0, 2):
153 case IP_VERSION(4, 0, 4):
154 case IP_VERSION(4, 0, 5):
155 if (amdgpu_sriov_vf(adev)) {
156 if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) ||
157 !amdgpu_sriov_is_av1_support(adev)) {
158 if (encode)
159 *codecs = &sriov_vcn_4_0_0_video_codecs_encode_vcn1;
160 else
161 *codecs = &sriov_vcn_4_0_0_video_codecs_decode_vcn1;
162 } else {
163 if (encode)
164 *codecs = &sriov_vcn_4_0_0_video_codecs_encode_vcn0;
165 else
166 *codecs = &sriov_vcn_4_0_0_video_codecs_decode_vcn0;
167 }
168 } else {
169 if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0)) {
170 if (encode)
171 *codecs = &vcn_4_0_0_video_codecs_encode_vcn1;
172 else
173 *codecs = &vcn_4_0_0_video_codecs_decode_vcn1;
174 } else {
175 if (encode)
176 *codecs = &vcn_4_0_0_video_codecs_encode_vcn0;
177 else
178 *codecs = &vcn_4_0_0_video_codecs_decode_vcn0;
179 }
180 }
181 return 0;
182 case IP_VERSION(4, 0, 6):
183 if (encode)
184 *codecs = &vcn_4_0_0_video_codecs_encode_vcn0;
185 else
186 *codecs = &vcn_4_0_0_video_codecs_decode_vcn0;
187 return 0;
188 default:
189 return -EINVAL;
190 }
191}
192
193static u32 soc21_didt_rreg(struct amdgpu_device *adev, u32 reg)
194{
195 unsigned long flags, address, data;
196 u32 r;
197
198 address = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_INDEX);
199 data = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_DATA);
200
201 spin_lock_irqsave(&adev->didt_idx_lock, flags);
202 WREG32(address, (reg));
203 r = RREG32(data);
204 spin_unlock_irqrestore(lock: &adev->didt_idx_lock, flags);
205 return r;
206}
207
208static void soc21_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
209{
210 unsigned long flags, address, data;
211
212 address = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_INDEX);
213 data = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_DATA);
214
215 spin_lock_irqsave(&adev->didt_idx_lock, flags);
216 WREG32(address, (reg));
217 WREG32(data, (v));
218 spin_unlock_irqrestore(lock: &adev->didt_idx_lock, flags);
219}
220
221static u32 soc21_get_config_memsize(struct amdgpu_device *adev)
222{
223 return adev->nbio.funcs->get_memsize(adev);
224}
225
226static u32 soc21_get_xclk(struct amdgpu_device *adev)
227{
228 u32 reference_clock = adev->clock.spll.reference_freq;
229
230 /* reference clock is actually 99.81 Mhz rather than 100 Mhz */
231 if ((adev->flags & AMD_IS_APU) && reference_clock == 10000)
232 return 9981;
233
234 return reference_clock;
235}
236
237
238void soc21_grbm_select(struct amdgpu_device *adev,
239 u32 me, u32 pipe, u32 queue, u32 vmid)
240{
241 u32 grbm_gfx_cntl = 0;
242 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
243 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
244 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
245 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
246
247 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, grbm_gfx_cntl);
248}
249
250static bool soc21_read_disabled_bios(struct amdgpu_device *adev)
251{
252 /* todo */
253 return false;
254}
255
256static struct soc15_allowed_register_entry soc21_allowed_read_registers[] = {
257 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS)},
258 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS2)},
259 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE0)},
260 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE1)},
261 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE2)},
262 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE3)},
263 { SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_STATUS_REG)},
264 { SOC15_REG_ENTRY(SDMA1, 0, regSDMA1_STATUS_REG)},
265 { SOC15_REG_ENTRY(GC, 0, regCP_STAT)},
266 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT1)},
267 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT2)},
268 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT3)},
269 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_BUSY_STAT)},
270 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STALLED_STAT1)},
271 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STATUS)},
272 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_BUSY_STAT)},
273 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STALLED_STAT1)},
274 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STATUS)},
275 { SOC15_REG_ENTRY(GC, 0, regGB_ADDR_CONFIG)},
276};
277
278static uint32_t soc21_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
279 u32 sh_num, u32 reg_offset)
280{
281 uint32_t val;
282
283 mutex_lock(&adev->grbm_idx_mutex);
284 if (se_num != 0xffffffff || sh_num != 0xffffffff)
285 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0);
286
287 val = RREG32(reg_offset);
288
289 if (se_num != 0xffffffff || sh_num != 0xffffffff)
290 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
291 mutex_unlock(lock: &adev->grbm_idx_mutex);
292 return val;
293}
294
295static uint32_t soc21_get_register_value(struct amdgpu_device *adev,
296 bool indexed, u32 se_num,
297 u32 sh_num, u32 reg_offset)
298{
299 if (indexed) {
300 return soc21_read_indexed_register(adev, se_num, sh_num, reg_offset);
301 } else {
302 if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG) && adev->gfx.config.gb_addr_config)
303 return adev->gfx.config.gb_addr_config;
304 return RREG32(reg_offset);
305 }
306}
307
308static int soc21_read_register(struct amdgpu_device *adev, u32 se_num,
309 u32 sh_num, u32 reg_offset, u32 *value)
310{
311 uint32_t i;
312 struct soc15_allowed_register_entry *en;
313
314 *value = 0;
315 for (i = 0; i < ARRAY_SIZE(soc21_allowed_read_registers); i++) {
316 en = &soc21_allowed_read_registers[i];
317 if (!adev->reg_offset[en->hwip][en->inst])
318 continue;
319 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
320 + en->reg_offset))
321 continue;
322
323 *value = soc21_get_register_value(adev,
324 indexed: soc21_allowed_read_registers[i].grbm_indexed,
325 se_num, sh_num, reg_offset);
326 return 0;
327 }
328 return -EINVAL;
329}
330
331#if 0
332static int soc21_asic_mode1_reset(struct amdgpu_device *adev)
333{
334 u32 i;
335 int ret = 0;
336
337 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
338
339 /* disable BM */
340 pci_clear_master(adev->pdev);
341
342 amdgpu_device_cache_pci_state(adev->pdev);
343
344 if (amdgpu_dpm_is_mode1_reset_supported(adev)) {
345 dev_info(adev->dev, "GPU smu mode1 reset\n");
346 ret = amdgpu_dpm_mode1_reset(adev);
347 } else {
348 dev_info(adev->dev, "GPU psp mode1 reset\n");
349 ret = psp_gpu_reset(adev);
350 }
351
352 if (ret)
353 dev_err(adev->dev, "GPU mode1 reset failed\n");
354 amdgpu_device_load_pci_state(adev->pdev);
355
356 /* wait for asic to come out of reset */
357 for (i = 0; i < adev->usec_timeout; i++) {
358 u32 memsize = adev->nbio.funcs->get_memsize(adev);
359
360 if (memsize != 0xffffffff)
361 break;
362 udelay(1);
363 }
364
365 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
366
367 return ret;
368}
369#endif
370
371static enum amd_reset_method
372soc21_asic_reset_method(struct amdgpu_device *adev)
373{
374 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
375 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
376 amdgpu_reset_method == AMD_RESET_METHOD_BACO)
377 return amdgpu_reset_method;
378
379 if (amdgpu_reset_method != -1)
380 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
381 amdgpu_reset_method);
382
383 switch (amdgpu_ip_version(adev, ip: MP1_HWIP, inst: 0)) {
384 case IP_VERSION(13, 0, 0):
385 case IP_VERSION(13, 0, 7):
386 case IP_VERSION(13, 0, 10):
387 return AMD_RESET_METHOD_MODE1;
388 case IP_VERSION(13, 0, 4):
389 case IP_VERSION(13, 0, 11):
390 case IP_VERSION(14, 0, 0):
391 case IP_VERSION(14, 0, 1):
392 case IP_VERSION(14, 0, 4):
393 case IP_VERSION(14, 0, 5):
394 return AMD_RESET_METHOD_MODE2;
395 default:
396 if (amdgpu_dpm_is_baco_supported(adev))
397 return AMD_RESET_METHOD_BACO;
398 else
399 return AMD_RESET_METHOD_MODE1;
400 }
401}
402
403static int soc21_asic_reset(struct amdgpu_device *adev)
404{
405 int ret = 0;
406
407 switch (soc21_asic_reset_method(adev)) {
408 case AMD_RESET_METHOD_PCI:
409 dev_info(adev->dev, "PCI reset\n");
410 ret = amdgpu_device_pci_reset(adev);
411 break;
412 case AMD_RESET_METHOD_BACO:
413 dev_info(adev->dev, "BACO reset\n");
414 ret = amdgpu_dpm_baco_reset(adev);
415 break;
416 case AMD_RESET_METHOD_MODE2:
417 dev_info(adev->dev, "MODE2 reset\n");
418 ret = amdgpu_dpm_mode2_reset(adev);
419 break;
420 default:
421 dev_info(adev->dev, "MODE1 reset\n");
422 ret = amdgpu_device_mode1_reset(adev);
423 break;
424 }
425
426 return ret;
427}
428
429static int soc21_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
430{
431 /* todo */
432 return 0;
433}
434
435static int soc21_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
436{
437 /* todo */
438 return 0;
439}
440
441static void soc21_program_aspm(struct amdgpu_device *adev)
442{
443 if (!amdgpu_device_should_use_aspm(adev))
444 return;
445
446 if (adev->nbio.funcs->program_aspm)
447 adev->nbio.funcs->program_aspm(adev);
448}
449
450const struct amdgpu_ip_block_version soc21_common_ip_block = {
451 .type = AMD_IP_BLOCK_TYPE_COMMON,
452 .major = 1,
453 .minor = 0,
454 .rev = 0,
455 .funcs = &soc21_common_ip_funcs,
456};
457
458static bool soc21_need_full_reset(struct amdgpu_device *adev)
459{
460 switch (amdgpu_ip_version(adev, ip: GC_HWIP, inst: 0)) {
461 case IP_VERSION(11, 0, 0):
462 case IP_VERSION(11, 0, 2):
463 case IP_VERSION(11, 0, 3):
464 default:
465 return true;
466 }
467}
468
469static bool soc21_need_reset_on_init(struct amdgpu_device *adev)
470{
471 u32 sol_reg;
472
473 if (adev->flags & AMD_IS_APU)
474 return false;
475
476 /* Check sOS sign of life register to confirm sys driver and sOS
477 * are already been loaded.
478 */
479 sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
480 if (sol_reg)
481 return true;
482
483 return false;
484}
485
486static void soc21_init_doorbell_index(struct amdgpu_device *adev)
487{
488 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ;
489 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0;
490 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1;
491 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2;
492 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3;
493 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4;
494 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5;
495 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6;
496 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7;
497 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START;
498 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END;
499 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0;
500 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1;
501 adev->doorbell_index.gfx_userqueue_start =
502 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START;
503 adev->doorbell_index.gfx_userqueue_end =
504 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END;
505 adev->doorbell_index.mes_ring0 = AMDGPU_NAVI10_DOORBELL_MES_RING0;
506 adev->doorbell_index.mes_ring1 = AMDGPU_NAVI10_DOORBELL_MES_RING1;
507 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0;
508 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1;
509 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH;
510 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1;
511 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3;
512 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5;
513 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7;
514 adev->doorbell_index.vpe_ring = AMDGPU_NAVI10_DOORBELL64_VPE;
515 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP;
516 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP;
517
518 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1;
519 adev->doorbell_index.sdma_doorbell_range = 20;
520}
521
522static void soc21_pre_asic_init(struct amdgpu_device *adev)
523{
524}
525
526static int soc21_update_umd_stable_pstate(struct amdgpu_device *adev,
527 bool enter)
528{
529 if (enter)
530 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id: 0);
531 else
532 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id: 0);
533
534 if (adev->gfx.funcs->update_perfmon_mgcg)
535 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter);
536
537 return 0;
538}
539
540static const struct amdgpu_asic_funcs soc21_asic_funcs = {
541 .read_disabled_bios = &soc21_read_disabled_bios,
542 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom,
543 .read_register = &soc21_read_register,
544 .reset = &soc21_asic_reset,
545 .reset_method = &soc21_asic_reset_method,
546 .get_xclk = &soc21_get_xclk,
547 .set_uvd_clocks = &soc21_set_uvd_clocks,
548 .set_vce_clocks = &soc21_set_vce_clocks,
549 .get_config_memsize = &soc21_get_config_memsize,
550 .init_doorbell_index = &soc21_init_doorbell_index,
551 .need_full_reset = &soc21_need_full_reset,
552 .need_reset_on_init = &soc21_need_reset_on_init,
553 .get_pcie_replay_count = &amdgpu_nbio_get_pcie_replay_count,
554 .supports_baco = &amdgpu_dpm_is_baco_supported,
555 .pre_asic_init = &soc21_pre_asic_init,
556 .query_video_codecs = &soc21_query_video_codecs,
557 .update_umd_stable_pstate = &soc21_update_umd_stable_pstate,
558};
559
560static int soc21_common_early_init(struct amdgpu_ip_block *ip_block)
561{
562 struct amdgpu_device *adev = ip_block->adev;
563
564 adev->nbio.funcs->set_reg_remap(adev);
565 adev->smc_rreg = NULL;
566 adev->smc_wreg = NULL;
567 adev->pcie_rreg = &amdgpu_device_indirect_rreg;
568 adev->pcie_wreg = &amdgpu_device_indirect_wreg;
569 adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64;
570 adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64;
571 adev->pciep_rreg = amdgpu_device_pcie_port_rreg;
572 adev->pciep_wreg = amdgpu_device_pcie_port_wreg;
573
574 /* TODO: will add them during VCN v2 implementation */
575 adev->uvd_ctx_rreg = NULL;
576 adev->uvd_ctx_wreg = NULL;
577
578 adev->didt_rreg = &soc21_didt_rreg;
579 adev->didt_wreg = &soc21_didt_wreg;
580
581 adev->asic_funcs = &soc21_asic_funcs;
582
583 adev->rev_id = amdgpu_device_get_rev_id(adev);
584 adev->external_rev_id = 0xff;
585 switch (amdgpu_ip_version(adev, ip: GC_HWIP, inst: 0)) {
586 case IP_VERSION(11, 0, 0):
587 adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG |
588 AMD_CG_SUPPORT_GFX_CGLS |
589#if 0
590 AMD_CG_SUPPORT_GFX_3D_CGCG |
591 AMD_CG_SUPPORT_GFX_3D_CGLS |
592#endif
593 AMD_CG_SUPPORT_GFX_MGCG |
594 AMD_CG_SUPPORT_REPEATER_FGCG |
595 AMD_CG_SUPPORT_GFX_FGCG |
596 AMD_CG_SUPPORT_GFX_PERF_CLK |
597 AMD_CG_SUPPORT_VCN_MGCG |
598 AMD_CG_SUPPORT_JPEG_MGCG |
599 AMD_CG_SUPPORT_ATHUB_MGCG |
600 AMD_CG_SUPPORT_ATHUB_LS |
601 AMD_CG_SUPPORT_MC_MGCG |
602 AMD_CG_SUPPORT_MC_LS |
603 AMD_CG_SUPPORT_IH_CG |
604 AMD_CG_SUPPORT_HDP_SD;
605 adev->pg_flags = AMD_PG_SUPPORT_VCN |
606 AMD_PG_SUPPORT_VCN_DPG |
607 AMD_PG_SUPPORT_JPEG |
608 AMD_PG_SUPPORT_ATHUB |
609 AMD_PG_SUPPORT_MMHUB;
610 adev->external_rev_id = adev->rev_id + 0x1; // TODO: need update
611 break;
612 case IP_VERSION(11, 0, 2):
613 adev->cg_flags =
614 AMD_CG_SUPPORT_GFX_CGCG |
615 AMD_CG_SUPPORT_GFX_CGLS |
616 AMD_CG_SUPPORT_REPEATER_FGCG |
617 AMD_CG_SUPPORT_VCN_MGCG |
618 AMD_CG_SUPPORT_JPEG_MGCG |
619 AMD_CG_SUPPORT_ATHUB_MGCG |
620 AMD_CG_SUPPORT_ATHUB_LS |
621 AMD_CG_SUPPORT_IH_CG |
622 AMD_CG_SUPPORT_HDP_SD;
623 adev->pg_flags =
624 AMD_PG_SUPPORT_VCN |
625 AMD_PG_SUPPORT_VCN_DPG |
626 AMD_PG_SUPPORT_JPEG |
627 AMD_PG_SUPPORT_ATHUB |
628 AMD_PG_SUPPORT_MMHUB;
629 adev->external_rev_id = adev->rev_id + 0x10;
630 break;
631 case IP_VERSION(11, 0, 1):
632 adev->cg_flags =
633 AMD_CG_SUPPORT_GFX_CGCG |
634 AMD_CG_SUPPORT_GFX_CGLS |
635 AMD_CG_SUPPORT_GFX_MGCG |
636 AMD_CG_SUPPORT_GFX_FGCG |
637 AMD_CG_SUPPORT_REPEATER_FGCG |
638 AMD_CG_SUPPORT_GFX_PERF_CLK |
639 AMD_CG_SUPPORT_MC_MGCG |
640 AMD_CG_SUPPORT_MC_LS |
641 AMD_CG_SUPPORT_HDP_MGCG |
642 AMD_CG_SUPPORT_HDP_LS |
643 AMD_CG_SUPPORT_ATHUB_MGCG |
644 AMD_CG_SUPPORT_ATHUB_LS |
645 AMD_CG_SUPPORT_IH_CG |
646 AMD_CG_SUPPORT_BIF_MGCG |
647 AMD_CG_SUPPORT_BIF_LS |
648 AMD_CG_SUPPORT_VCN_MGCG |
649 AMD_CG_SUPPORT_JPEG_MGCG;
650 adev->pg_flags =
651 AMD_PG_SUPPORT_GFX_PG |
652 AMD_PG_SUPPORT_VCN |
653 AMD_PG_SUPPORT_VCN_DPG |
654 AMD_PG_SUPPORT_JPEG;
655 adev->external_rev_id = adev->rev_id + 0x1;
656 break;
657 case IP_VERSION(11, 0, 3):
658 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG |
659 AMD_CG_SUPPORT_JPEG_MGCG |
660 AMD_CG_SUPPORT_GFX_CGCG |
661 AMD_CG_SUPPORT_GFX_CGLS |
662 AMD_CG_SUPPORT_REPEATER_FGCG |
663 AMD_CG_SUPPORT_GFX_MGCG |
664 AMD_CG_SUPPORT_HDP_SD |
665 AMD_CG_SUPPORT_ATHUB_MGCG |
666 AMD_CG_SUPPORT_ATHUB_LS;
667 adev->pg_flags = AMD_PG_SUPPORT_VCN |
668 AMD_PG_SUPPORT_VCN_DPG |
669 AMD_PG_SUPPORT_JPEG;
670 adev->external_rev_id = adev->rev_id + 0x20;
671 break;
672 case IP_VERSION(11, 0, 4):
673 adev->cg_flags =
674 AMD_CG_SUPPORT_GFX_CGCG |
675 AMD_CG_SUPPORT_GFX_CGLS |
676 AMD_CG_SUPPORT_GFX_MGCG |
677 AMD_CG_SUPPORT_GFX_FGCG |
678 AMD_CG_SUPPORT_REPEATER_FGCG |
679 AMD_CG_SUPPORT_GFX_PERF_CLK |
680 AMD_CG_SUPPORT_MC_MGCG |
681 AMD_CG_SUPPORT_MC_LS |
682 AMD_CG_SUPPORT_HDP_MGCG |
683 AMD_CG_SUPPORT_HDP_LS |
684 AMD_CG_SUPPORT_ATHUB_MGCG |
685 AMD_CG_SUPPORT_ATHUB_LS |
686 AMD_CG_SUPPORT_IH_CG |
687 AMD_CG_SUPPORT_BIF_MGCG |
688 AMD_CG_SUPPORT_BIF_LS |
689 AMD_CG_SUPPORT_VCN_MGCG |
690 AMD_CG_SUPPORT_JPEG_MGCG;
691 adev->pg_flags = AMD_PG_SUPPORT_VCN |
692 AMD_PG_SUPPORT_VCN_DPG |
693 AMD_PG_SUPPORT_GFX_PG |
694 AMD_PG_SUPPORT_JPEG;
695 adev->external_rev_id = adev->rev_id + 0x80;
696 break;
697 case IP_VERSION(11, 5, 0):
698 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG |
699 AMD_CG_SUPPORT_JPEG_MGCG |
700 AMD_CG_SUPPORT_GFX_CGCG |
701 AMD_CG_SUPPORT_GFX_CGLS |
702 AMD_CG_SUPPORT_GFX_MGCG |
703 AMD_CG_SUPPORT_GFX_FGCG |
704 AMD_CG_SUPPORT_REPEATER_FGCG |
705 AMD_CG_SUPPORT_GFX_PERF_CLK |
706 AMD_CG_SUPPORT_GFX_3D_CGCG |
707 AMD_CG_SUPPORT_GFX_3D_CGLS |
708 AMD_CG_SUPPORT_MC_MGCG |
709 AMD_CG_SUPPORT_MC_LS |
710 AMD_CG_SUPPORT_HDP_LS |
711 AMD_CG_SUPPORT_HDP_DS |
712 AMD_CG_SUPPORT_HDP_SD |
713 AMD_CG_SUPPORT_ATHUB_MGCG |
714 AMD_CG_SUPPORT_ATHUB_LS |
715 AMD_CG_SUPPORT_IH_CG |
716 AMD_CG_SUPPORT_BIF_MGCG |
717 AMD_CG_SUPPORT_BIF_LS;
718 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG |
719 AMD_PG_SUPPORT_JPEG_DPG |
720 AMD_PG_SUPPORT_VCN |
721 AMD_PG_SUPPORT_JPEG |
722 AMD_PG_SUPPORT_GFX_PG;
723 if (adev->rev_id == 0)
724 adev->external_rev_id = 0x1;
725 else
726 adev->external_rev_id = adev->rev_id + 0x10;
727 break;
728 case IP_VERSION(11, 5, 1):
729 adev->cg_flags =
730 AMD_CG_SUPPORT_GFX_CGCG |
731 AMD_CG_SUPPORT_GFX_CGLS |
732 AMD_CG_SUPPORT_GFX_MGCG |
733 AMD_CG_SUPPORT_GFX_FGCG |
734 AMD_CG_SUPPORT_REPEATER_FGCG |
735 AMD_CG_SUPPORT_GFX_PERF_CLK |
736 AMD_CG_SUPPORT_GFX_3D_CGCG |
737 AMD_CG_SUPPORT_GFX_3D_CGLS |
738 AMD_CG_SUPPORT_MC_MGCG |
739 AMD_CG_SUPPORT_MC_LS |
740 AMD_CG_SUPPORT_HDP_LS |
741 AMD_CG_SUPPORT_HDP_DS |
742 AMD_CG_SUPPORT_HDP_SD |
743 AMD_CG_SUPPORT_ATHUB_MGCG |
744 AMD_CG_SUPPORT_ATHUB_LS |
745 AMD_CG_SUPPORT_IH_CG |
746 AMD_CG_SUPPORT_BIF_MGCG |
747 AMD_CG_SUPPORT_BIF_LS |
748 AMD_CG_SUPPORT_VCN_MGCG |
749 AMD_CG_SUPPORT_JPEG_MGCG;
750 adev->pg_flags =
751 AMD_PG_SUPPORT_GFX_PG |
752 AMD_PG_SUPPORT_VCN |
753 AMD_PG_SUPPORT_VCN_DPG |
754 AMD_PG_SUPPORT_JPEG;
755 adev->external_rev_id = adev->rev_id + 0xc1;
756 break;
757 case IP_VERSION(11, 5, 2):
758 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG |
759 AMD_CG_SUPPORT_JPEG_MGCG |
760 AMD_CG_SUPPORT_GFX_CGCG |
761 AMD_CG_SUPPORT_GFX_CGLS |
762 AMD_CG_SUPPORT_GFX_MGCG |
763 AMD_CG_SUPPORT_GFX_FGCG |
764 AMD_CG_SUPPORT_REPEATER_FGCG |
765 AMD_CG_SUPPORT_GFX_PERF_CLK |
766 AMD_CG_SUPPORT_GFX_3D_CGCG |
767 AMD_CG_SUPPORT_GFX_3D_CGLS |
768 AMD_CG_SUPPORT_MC_MGCG |
769 AMD_CG_SUPPORT_MC_LS |
770 AMD_CG_SUPPORT_HDP_LS |
771 AMD_CG_SUPPORT_HDP_DS |
772 AMD_CG_SUPPORT_HDP_SD |
773 AMD_CG_SUPPORT_ATHUB_MGCG |
774 AMD_CG_SUPPORT_ATHUB_LS |
775 AMD_CG_SUPPORT_IH_CG |
776 AMD_CG_SUPPORT_BIF_MGCG |
777 AMD_CG_SUPPORT_BIF_LS;
778 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG |
779 AMD_PG_SUPPORT_VCN |
780 AMD_PG_SUPPORT_JPEG_DPG |
781 AMD_PG_SUPPORT_JPEG |
782 AMD_PG_SUPPORT_GFX_PG;
783 adev->external_rev_id = adev->rev_id + 0x40;
784 break;
785 case IP_VERSION(11, 5, 3):
786 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG |
787 AMD_CG_SUPPORT_JPEG_MGCG |
788 AMD_CG_SUPPORT_GFX_CGCG |
789 AMD_CG_SUPPORT_GFX_CGLS |
790 AMD_CG_SUPPORT_GFX_MGCG |
791 AMD_CG_SUPPORT_GFX_FGCG |
792 AMD_CG_SUPPORT_REPEATER_FGCG |
793 AMD_CG_SUPPORT_GFX_PERF_CLK |
794 AMD_CG_SUPPORT_GFX_3D_CGCG |
795 AMD_CG_SUPPORT_GFX_3D_CGLS |
796 AMD_CG_SUPPORT_MC_MGCG |
797 AMD_CG_SUPPORT_MC_LS |
798 AMD_CG_SUPPORT_HDP_LS |
799 AMD_CG_SUPPORT_HDP_DS |
800 AMD_CG_SUPPORT_HDP_SD |
801 AMD_CG_SUPPORT_ATHUB_MGCG |
802 AMD_CG_SUPPORT_ATHUB_LS |
803 AMD_CG_SUPPORT_IH_CG |
804 AMD_CG_SUPPORT_BIF_MGCG |
805 AMD_CG_SUPPORT_BIF_LS;
806 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG |
807 AMD_PG_SUPPORT_VCN |
808 AMD_PG_SUPPORT_JPEG_DPG |
809 AMD_PG_SUPPORT_JPEG |
810 AMD_PG_SUPPORT_GFX_PG;
811 adev->external_rev_id = adev->rev_id + 0x50;
812 break;
813 default:
814 /* FIXME: not supported yet */
815 return -EINVAL;
816 }
817
818 if (amdgpu_sriov_vf(adev)) {
819 amdgpu_virt_init_setting(adev);
820 xgpu_nv_mailbox_set_irq_funcs(adev);
821 }
822
823 return 0;
824}
825
826static int soc21_common_late_init(struct amdgpu_ip_block *ip_block)
827{
828 struct amdgpu_device *adev = ip_block->adev;
829
830 if (amdgpu_sriov_vf(adev)) {
831 xgpu_nv_mailbox_get_irq(adev);
832 if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) ||
833 !amdgpu_sriov_is_av1_support(adev)) {
834 amdgpu_virt_update_sriov_video_codec(adev,
835 encode: sriov_vcn_4_0_0_video_codecs_encode_array_vcn1,
836 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn1),
837 decode: sriov_vcn_4_0_0_video_codecs_decode_array_vcn1,
838 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn1));
839 } else {
840 amdgpu_virt_update_sriov_video_codec(adev,
841 encode: sriov_vcn_4_0_0_video_codecs_encode_array_vcn0,
842 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn0),
843 decode: sriov_vcn_4_0_0_video_codecs_decode_array_vcn0,
844 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn0));
845 }
846 } else {
847 if (adev->nbio.ras &&
848 adev->nbio.ras_err_event_athub_irq.funcs)
849 /* don't need to fail gpu late init
850 * if enabling athub_err_event interrupt failed
851 * nbio v4_3 only support fatal error hanlding
852 * just enable the interrupt directly */
853 amdgpu_irq_get(adev, src: &adev->nbio.ras_err_event_athub_irq, type: 0);
854 }
855
856 /* Enable selfring doorbell aperture late because doorbell BAR
857 * aperture will change if resize BAR successfully in gmc sw_init.
858 */
859 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true);
860
861 return 0;
862}
863
864static int soc21_common_sw_init(struct amdgpu_ip_block *ip_block)
865{
866 struct amdgpu_device *adev = ip_block->adev;
867
868 if (amdgpu_sriov_vf(adev))
869 xgpu_nv_mailbox_add_irq_id(adev);
870
871 return 0;
872}
873
874static int soc21_common_hw_init(struct amdgpu_ip_block *ip_block)
875{
876 struct amdgpu_device *adev = ip_block->adev;
877
878 /* enable aspm */
879 soc21_program_aspm(adev);
880 /* setup nbio registers */
881 adev->nbio.funcs->init_registers(adev);
882 /* remap HDP registers to a hole in mmio space,
883 * for the purpose of expose those registers
884 * to process space
885 */
886 if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev))
887 adev->nbio.funcs->remap_hdp_registers(adev);
888 /* enable the doorbell aperture */
889 adev->nbio.funcs->enable_doorbell_aperture(adev, true);
890
891 return 0;
892}
893
894static int soc21_common_hw_fini(struct amdgpu_ip_block *ip_block)
895{
896 struct amdgpu_device *adev = ip_block->adev;
897
898 /* Disable the doorbell aperture and selfring doorbell aperture
899 * separately in hw_fini because soc21_enable_doorbell_aperture
900 * has been removed and there is no need to delay disabling
901 * selfring doorbell.
902 */
903 adev->nbio.funcs->enable_doorbell_aperture(adev, false);
904 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false);
905
906 if (amdgpu_sriov_vf(adev)) {
907 xgpu_nv_mailbox_put_irq(adev);
908 } else {
909 if (adev->nbio.ras &&
910 adev->nbio.ras_err_event_athub_irq.funcs)
911 amdgpu_irq_put(adev, src: &adev->nbio.ras_err_event_athub_irq, type: 0);
912 }
913
914 return 0;
915}
916
917static int soc21_common_suspend(struct amdgpu_ip_block *ip_block)
918{
919 return soc21_common_hw_fini(ip_block);
920}
921
922static bool soc21_need_reset_on_resume(struct amdgpu_device *adev)
923{
924 u32 sol_reg1, sol_reg2;
925
926 /* Will reset for the following suspend abort cases.
927 * 1) Only reset dGPU side.
928 * 2) S3 suspend got aborted and TOS is active.
929 * As for dGPU suspend abort cases the SOL value
930 * will be kept as zero at this resume point.
931 */
932 if (!(adev->flags & AMD_IS_APU) && adev->in_s3) {
933 sol_reg1 = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
934 msleep(msecs: 100);
935 sol_reg2 = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
936
937 return (sol_reg1 != sol_reg2);
938 }
939
940 return false;
941}
942
943static int soc21_common_resume(struct amdgpu_ip_block *ip_block)
944{
945 struct amdgpu_device *adev = ip_block->adev;
946
947 if (soc21_need_reset_on_resume(adev)) {
948 dev_info(adev->dev, "S3 suspend aborted, resetting...");
949 soc21_asic_reset(adev);
950 }
951
952 return soc21_common_hw_init(ip_block);
953}
954
955static bool soc21_common_is_idle(struct amdgpu_ip_block *ip_block)
956{
957 return true;
958}
959
960static int soc21_common_set_clockgating_state(struct amdgpu_ip_block *ip_block,
961 enum amd_clockgating_state state)
962{
963 struct amdgpu_device *adev = ip_block->adev;
964
965 switch (amdgpu_ip_version(adev, ip: NBIO_HWIP, inst: 0)) {
966 case IP_VERSION(4, 3, 0):
967 case IP_VERSION(4, 3, 1):
968 case IP_VERSION(7, 7, 0):
969 case IP_VERSION(7, 7, 1):
970 case IP_VERSION(7, 11, 0):
971 case IP_VERSION(7, 11, 1):
972 case IP_VERSION(7, 11, 2):
973 case IP_VERSION(7, 11, 3):
974 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
975 state == AMD_CG_STATE_GATE);
976 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
977 state == AMD_CG_STATE_GATE);
978 adev->hdp.funcs->update_clock_gating(adev,
979 state == AMD_CG_STATE_GATE);
980 break;
981 default:
982 break;
983 }
984 return 0;
985}
986
987static int soc21_common_set_powergating_state(struct amdgpu_ip_block *ip_block,
988 enum amd_powergating_state state)
989{
990 struct amdgpu_device *adev = ip_block->adev;
991
992 switch (amdgpu_ip_version(adev, ip: LSDMA_HWIP, inst: 0)) {
993 case IP_VERSION(6, 0, 0):
994 case IP_VERSION(6, 0, 2):
995 adev->lsdma.funcs->update_memory_power_gating(adev,
996 state == AMD_PG_STATE_GATE);
997 break;
998 default:
999 break;
1000 }
1001
1002 return 0;
1003}
1004
1005static void soc21_common_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)
1006{
1007 struct amdgpu_device *adev = ip_block->adev;
1008
1009 adev->nbio.funcs->get_clockgating_state(adev, flags);
1010
1011 adev->hdp.funcs->get_clock_gating_state(adev, flags);
1012}
1013
1014static const struct amd_ip_funcs soc21_common_ip_funcs = {
1015 .name = "soc21_common",
1016 .early_init = soc21_common_early_init,
1017 .late_init = soc21_common_late_init,
1018 .sw_init = soc21_common_sw_init,
1019 .hw_init = soc21_common_hw_init,
1020 .hw_fini = soc21_common_hw_fini,
1021 .suspend = soc21_common_suspend,
1022 .resume = soc21_common_resume,
1023 .is_idle = soc21_common_is_idle,
1024 .set_clockgating_state = soc21_common_set_clockgating_state,
1025 .set_powergating_state = soc21_common_set_powergating_state,
1026 .get_clockgating_state = soc21_common_get_clockgating_state,
1027};
1028

source code of linux/drivers/gpu/drm/amd/amdgpu/soc21.c