1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include "smuio/smuio_11_0_0_offset.h"
25#include "smuio/smuio_11_0_0_sh_mask.h"
26
27#include "smu_v11_0_i2c.h"
28#include "amdgpu.h"
29#include "amdgpu_dpm.h"
30#include "soc15_common.h"
31#include <drm/drm_fixed.h>
32#include <drm/drm_drv.h>
33#include "amdgpu_amdkfd.h"
34#include <linux/i2c.h>
35#include <linux/pci.h>
36
37/* error codes */
38#define I2C_OK 0
39#define I2C_NAK_7B_ADDR_NOACK 1
40#define I2C_NAK_TXDATA_NOACK 2
41#define I2C_TIMEOUT 4
42#define I2C_SW_TIMEOUT 8
43#define I2C_ABORT 0x10
44
45#define I2C_X_RESTART BIT(31)
46
47static void smu_v11_0_i2c_set_clock_gating(struct i2c_adapter *control, bool en)
48{
49 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(adap: control);
50 struct amdgpu_device *adev = smu_i2c->adev;
51 uint32_t reg = RREG32_SOC15(SMUIO, 0, mmSMUIO_PWRMGT);
52
53 reg = REG_SET_FIELD(reg, SMUIO_PWRMGT, i2c_clk_gate_en, en ? 1 : 0);
54 WREG32_SOC15(SMUIO, 0, mmSMUIO_PWRMGT, reg);
55}
56
57/* The T_I2C_POLL_US is defined as follows:
58 *
59 * "Define a timer interval (t_i2c_poll) equal to 10 times the
60 * signalling period for the highest I2C transfer speed used in the
61 * system and supported by DW_apb_i2c. For instance, if the highest
62 * I2C data transfer mode is 400 kb/s, then t_i2c_poll is 25 us." --
63 * DesignWare DW_apb_i2c Databook, Version 1.21a, section 3.8.3.1,
64 * page 56, with grammar and syntax corrections.
65 *
66 * Vcc for our device is at 1.8V which puts it at 400 kHz,
67 * see Atmel AT24CM02 datasheet, section 8.3 DC Characteristics table, page 14.
68 *
69 * The procedure to disable the IP block is described in section
70 * 3.8.3 Disabling DW_apb_i2c on page 56.
71 */
72#define I2C_SPEED_MODE_FAST 2
73#define T_I2C_POLL_US 25
74#define I2C_MAX_T_POLL_COUNT 1000
75
76static int smu_v11_0_i2c_enable(struct i2c_adapter *control, bool enable)
77{
78 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(adap: control);
79 struct amdgpu_device *adev = smu_i2c->adev;
80
81 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE, enable ? 1 : 0);
82
83 if (!enable) {
84 int ii;
85
86 for (ii = I2C_MAX_T_POLL_COUNT; ii > 0; ii--) {
87 u32 en_stat = RREG32_SOC15(SMUIO,
88 0,
89 mmCKSVII2C_IC_ENABLE_STATUS);
90 if (REG_GET_FIELD(en_stat, CKSVII2C_IC_ENABLE_STATUS, IC_EN))
91 udelay(T_I2C_POLL_US);
92 else
93 return I2C_OK;
94 }
95
96 return I2C_ABORT;
97 }
98
99 return I2C_OK;
100}
101
102static void smu_v11_0_i2c_clear_status(struct i2c_adapter *control)
103{
104 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(adap: control);
105 struct amdgpu_device *adev = smu_i2c->adev;
106 /* do */
107 {
108 RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_CLR_INTR);
109
110 } /* while (reg_CKSVII2C_ic_clr_intr == 0) */
111}
112
113static void smu_v11_0_i2c_configure(struct i2c_adapter *control)
114{
115 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(adap: control);
116 struct amdgpu_device *adev = smu_i2c->adev;
117 uint32_t reg = 0;
118
119 reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_SLAVE_DISABLE, 1);
120 reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_RESTART_EN, 1);
121 reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_10BITADDR_MASTER, 0);
122 reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_10BITADDR_SLAVE, 0);
123 /* The values of IC_MAX_SPEED_MODE are,
124 * 1: standard mode, 0 - 100 Kb/s,
125 * 2: fast mode, <= 400 Kb/s, or fast mode plus, <= 1000 Kb/s,
126 * 3: high speed mode, <= 3.4 Mb/s.
127 */
128 reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_MAX_SPEED_MODE,
129 I2C_SPEED_MODE_FAST);
130 reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_MASTER_MODE, 1);
131
132 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_CON, reg);
133}
134
135static void smu_v11_0_i2c_set_clock(struct i2c_adapter *control)
136{
137 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(adap: control);
138 struct amdgpu_device *adev = smu_i2c->adev;
139
140 /*
141 * Standard mode speed, These values are taken from SMUIO MAS,
142 * but are different from what is given is
143 * Synopsys spec. The values here are based on assumption
144 * that refclock is 100MHz
145 *
146 * Configuration for standard mode; Speed = 100kbps
147 * Scale linearly, for now only support standard speed clock
148 * This will work only with 100M ref clock
149 *
150 * TBD:Change the calculation to take into account ref clock values also.
151 */
152
153 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_FS_SPKLEN, 2);
154 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_SS_SCL_HCNT, 120);
155 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_SS_SCL_LCNT, 130);
156 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_SDA_HOLD, 20);
157}
158
159static void smu_v11_0_i2c_set_address(struct i2c_adapter *control, u16 address)
160{
161 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(adap: control);
162 struct amdgpu_device *adev = smu_i2c->adev;
163
164 /* The IC_TAR::IC_TAR field is 10-bits wide.
165 * It takes a 7-bit or 10-bit addresses as an address,
166 * i.e. no read/write bit--no wire format, just the address.
167 */
168 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_TAR, address & 0x3FF);
169}
170
171static uint32_t smu_v11_0_i2c_poll_tx_status(struct i2c_adapter *control)
172{
173 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(adap: control);
174 struct amdgpu_device *adev = smu_i2c->adev;
175 uint32_t ret = I2C_OK;
176 uint32_t reg, reg_c_tx_abrt_source;
177
178 /*Check if transmission is completed */
179 unsigned long timeout_counter = jiffies + msecs_to_jiffies(m: 20);
180
181 do {
182 if (time_after(jiffies, timeout_counter)) {
183 ret |= I2C_SW_TIMEOUT;
184 break;
185 }
186
187 reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS);
188
189 } while (REG_GET_FIELD(reg, CKSVII2C_IC_STATUS, TFE) == 0);
190
191 if (ret != I2C_OK)
192 return ret;
193
194 /* This only checks if NAK is received and transaction got aborted */
195 reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_INTR_STAT);
196
197 if (REG_GET_FIELD(reg, CKSVII2C_IC_INTR_STAT, R_TX_ABRT) == 1) {
198 reg_c_tx_abrt_source = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_TX_ABRT_SOURCE);
199 DRM_INFO("TX was terminated, IC_TX_ABRT_SOURCE val is:%x", reg_c_tx_abrt_source);
200
201 /* Check for stop due to NACK */
202 if (REG_GET_FIELD(reg_c_tx_abrt_source,
203 CKSVII2C_IC_TX_ABRT_SOURCE,
204 ABRT_TXDATA_NOACK) == 1) {
205
206 ret |= I2C_NAK_TXDATA_NOACK;
207
208 } else if (REG_GET_FIELD(reg_c_tx_abrt_source,
209 CKSVII2C_IC_TX_ABRT_SOURCE,
210 ABRT_7B_ADDR_NOACK) == 1) {
211
212 ret |= I2C_NAK_7B_ADDR_NOACK;
213 } else {
214 ret |= I2C_ABORT;
215 }
216
217 smu_v11_0_i2c_clear_status(control);
218 }
219
220 return ret;
221}
222
223static uint32_t smu_v11_0_i2c_poll_rx_status(struct i2c_adapter *control)
224{
225 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(adap: control);
226 struct amdgpu_device *adev = smu_i2c->adev;
227 uint32_t ret = I2C_OK;
228 uint32_t reg_ic_status, reg_c_tx_abrt_source;
229
230 reg_c_tx_abrt_source = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_TX_ABRT_SOURCE);
231
232 /* If slave is not present */
233 if (REG_GET_FIELD(reg_c_tx_abrt_source,
234 CKSVII2C_IC_TX_ABRT_SOURCE,
235 ABRT_7B_ADDR_NOACK) == 1) {
236 ret |= I2C_NAK_7B_ADDR_NOACK;
237
238 smu_v11_0_i2c_clear_status(control);
239 } else { /* wait till some data is there in RXFIFO */
240 /* Poll for some byte in RXFIFO */
241 unsigned long timeout_counter = jiffies + msecs_to_jiffies(m: 20);
242
243 do {
244 if (time_after(jiffies, timeout_counter)) {
245 ret |= I2C_SW_TIMEOUT;
246 break;
247 }
248
249 reg_ic_status = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS);
250
251 } while (REG_GET_FIELD(reg_ic_status, CKSVII2C_IC_STATUS, RFNE) == 0);
252 }
253
254 return ret;
255}
256
257/**
258 * smu_v11_0_i2c_transmit - Send a block of data over the I2C bus to a slave device.
259 *
260 * @control: I2C adapter reference
261 * @address: The I2C address of the slave device.
262 * @data: The data to transmit over the bus.
263 * @numbytes: The amount of data to transmit.
264 * @i2c_flag: Flags for transmission
265 *
266 * Returns 0 on success or error.
267 */
268static uint32_t smu_v11_0_i2c_transmit(struct i2c_adapter *control,
269 u16 address, u8 *data,
270 u32 numbytes, u32 i2c_flag)
271{
272 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(adap: control);
273 struct amdgpu_device *adev = smu_i2c->adev;
274 u32 bytes_sent, reg, ret = I2C_OK;
275 unsigned long timeout_counter;
276
277 bytes_sent = 0;
278
279 DRM_DEBUG_DRIVER("I2C_Transmit(), address = %x, bytes = %d , data: ",
280 address, numbytes);
281
282 if (drm_debug_enabled(DRM_UT_DRIVER)) {
283 print_hex_dump(KERN_INFO, prefix_str: "data: ", prefix_type: DUMP_PREFIX_NONE,
284 rowsize: 16, groupsize: 1, buf: data, len: numbytes, ascii: false);
285 }
286
287 /* Set the I2C slave address */
288 smu_v11_0_i2c_set_address(control, address);
289 /* Enable I2C */
290 smu_v11_0_i2c_enable(control, enable: true);
291
292 /* Clear status bits */
293 smu_v11_0_i2c_clear_status(control);
294
295 timeout_counter = jiffies + msecs_to_jiffies(m: 20);
296
297 while (numbytes > 0) {
298 reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS);
299 if (!REG_GET_FIELD(reg, CKSVII2C_IC_STATUS, TFNF)) {
300 /*
301 * We waited for too long for the transmission
302 * FIFO to become not-full. Exit the loop
303 * with error.
304 */
305 if (time_after(jiffies, timeout_counter)) {
306 ret |= I2C_SW_TIMEOUT;
307 goto Err;
308 }
309 } else {
310 reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, DAT,
311 data[bytes_sent]);
312
313 /* Final message, final byte, must generate a
314 * STOP to release the bus, i.e. don't hold
315 * SCL low.
316 */
317 if (numbytes == 1 && i2c_flag & I2C_M_STOP)
318 reg = REG_SET_FIELD(reg,
319 CKSVII2C_IC_DATA_CMD,
320 STOP, 1);
321
322 if (bytes_sent == 0 && i2c_flag & I2C_X_RESTART)
323 reg = REG_SET_FIELD(reg,
324 CKSVII2C_IC_DATA_CMD,
325 RESTART, 1);
326
327 /* Write */
328 reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, CMD, 0);
329 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_DATA_CMD, reg);
330
331 /* Record that the bytes were transmitted */
332 bytes_sent++;
333 numbytes--;
334 }
335 }
336
337 ret = smu_v11_0_i2c_poll_tx_status(control);
338Err:
339 /* Any error, no point in proceeding */
340 if (ret != I2C_OK) {
341 if (ret & I2C_SW_TIMEOUT)
342 DRM_ERROR("TIMEOUT ERROR !!!");
343
344 if (ret & I2C_NAK_7B_ADDR_NOACK)
345 DRM_ERROR("Received I2C_NAK_7B_ADDR_NOACK !!!");
346
347
348 if (ret & I2C_NAK_TXDATA_NOACK)
349 DRM_ERROR("Received I2C_NAK_TXDATA_NOACK !!!");
350 }
351
352 return ret;
353}
354
355
356/**
357 * smu_v11_0_i2c_receive - Receive a block of data over the I2C bus from a slave device.
358 *
359 * @control: I2C adapter reference
360 * @address: The I2C address of the slave device.
361 * @data: Placeholder to store received data.
362 * @numbytes: The amount of data to transmit.
363 * @i2c_flag: Flags for transmission
364 *
365 * Returns 0 on success or error.
366 */
367static uint32_t smu_v11_0_i2c_receive(struct i2c_adapter *control,
368 u16 address, u8 *data,
369 u32 numbytes, u32 i2c_flag)
370{
371 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(adap: control);
372 struct amdgpu_device *adev = smu_i2c->adev;
373 uint32_t bytes_received, ret = I2C_OK;
374
375 bytes_received = 0;
376
377 /* Set the I2C slave address */
378 smu_v11_0_i2c_set_address(control, address);
379
380 /* Enable I2C */
381 smu_v11_0_i2c_enable(control, enable: true);
382
383 while (numbytes > 0) {
384 uint32_t reg = 0;
385
386 smu_v11_0_i2c_clear_status(control);
387
388 /* Prepare transaction */
389 reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, DAT, 0);
390 /* Read */
391 reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, CMD, 1);
392
393 /* Final message, final byte, must generate a STOP
394 * to release the bus, i.e. don't hold SCL low.
395 */
396 if (numbytes == 1 && i2c_flag & I2C_M_STOP)
397 reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD,
398 STOP, 1);
399
400 if (bytes_received == 0 && i2c_flag & I2C_X_RESTART)
401 reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD,
402 RESTART, 1);
403
404 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_DATA_CMD, reg);
405
406 ret = smu_v11_0_i2c_poll_rx_status(control);
407
408 /* Any error, no point in proceeding */
409 if (ret != I2C_OK) {
410 if (ret & I2C_SW_TIMEOUT)
411 DRM_ERROR("TIMEOUT ERROR !!!");
412
413 if (ret & I2C_NAK_7B_ADDR_NOACK)
414 DRM_ERROR("Received I2C_NAK_7B_ADDR_NOACK !!!");
415
416 if (ret & I2C_NAK_TXDATA_NOACK)
417 DRM_ERROR("Received I2C_NAK_TXDATA_NOACK !!!");
418
419 break;
420 }
421
422 reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_DATA_CMD);
423 data[bytes_received] = REG_GET_FIELD(reg, CKSVII2C_IC_DATA_CMD, DAT);
424
425 /* Record that the bytes were received */
426 bytes_received++;
427 numbytes--;
428 }
429
430 DRM_DEBUG_DRIVER("I2C_Receive(), address = %x, bytes = %d, data :",
431 (uint16_t)address, bytes_received);
432
433 if (drm_debug_enabled(DRM_UT_DRIVER)) {
434 print_hex_dump(KERN_INFO, prefix_str: "data: ", prefix_type: DUMP_PREFIX_NONE,
435 rowsize: 16, groupsize: 1, buf: data, len: bytes_received, ascii: false);
436 }
437
438 return ret;
439}
440
441static void smu_v11_0_i2c_abort(struct i2c_adapter *control)
442{
443 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(adap: control);
444 struct amdgpu_device *adev = smu_i2c->adev;
445 uint32_t reg = 0;
446
447 /* Enable I2C engine; */
448 reg = REG_SET_FIELD(reg, CKSVII2C_IC_ENABLE, ENABLE, 1);
449 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE, reg);
450
451 /* Abort previous transaction */
452 reg = REG_SET_FIELD(reg, CKSVII2C_IC_ENABLE, ABORT, 1);
453 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE, reg);
454
455 DRM_DEBUG_DRIVER("I2C_Abort() Done.");
456}
457
458static bool smu_v11_0_i2c_activity_done(struct i2c_adapter *control)
459{
460 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(adap: control);
461 struct amdgpu_device *adev = smu_i2c->adev;
462
463 const uint32_t IDLE_TIMEOUT = 1024;
464 uint32_t timeout_count = 0;
465 uint32_t reg_ic_enable, reg_ic_enable_status, reg_ic_clr_activity;
466
467 reg_ic_enable_status = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE_STATUS);
468 reg_ic_enable = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE);
469
470 if ((REG_GET_FIELD(reg_ic_enable, CKSVII2C_IC_ENABLE, ENABLE) == 0) &&
471 (REG_GET_FIELD(reg_ic_enable_status, CKSVII2C_IC_ENABLE_STATUS, IC_EN) == 1)) {
472 /*
473 * Nobody is using I2C engine, but engine remains active because
474 * someone missed to send STOP
475 */
476 smu_v11_0_i2c_abort(control);
477 } else if (REG_GET_FIELD(reg_ic_enable, CKSVII2C_IC_ENABLE, ENABLE) == 0) {
478 /* Nobody is using I2C engine */
479 return true;
480 }
481
482 /* Keep reading activity bit until it's cleared */
483 do {
484 reg_ic_clr_activity = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_CLR_ACTIVITY);
485
486 if (REG_GET_FIELD(reg_ic_clr_activity,
487 CKSVII2C_IC_CLR_ACTIVITY, CLR_ACTIVITY) == 0)
488 return true;
489
490 ++timeout_count;
491
492 } while (timeout_count < IDLE_TIMEOUT);
493
494 return false;
495}
496
497static void smu_v11_0_i2c_init(struct i2c_adapter *control)
498{
499 int res;
500
501 /* Disable clock gating */
502 smu_v11_0_i2c_set_clock_gating(control, en: false);
503
504 if (!smu_v11_0_i2c_activity_done(control))
505 DRM_WARN("I2C busy !");
506
507 /* Disable I2C */
508 res = smu_v11_0_i2c_enable(control, enable: false);
509 if (res != I2C_OK)
510 smu_v11_0_i2c_abort(control);
511
512 /* Configure I2C to operate as master and in standard mode */
513 smu_v11_0_i2c_configure(control);
514
515 /* Initialize the clock to 50 kHz default */
516 smu_v11_0_i2c_set_clock(control);
517
518}
519
520static void smu_v11_0_i2c_fini(struct i2c_adapter *control)
521{
522 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(adap: control);
523 struct amdgpu_device *adev = smu_i2c->adev;
524 u32 status, enable, en_stat;
525 int res;
526
527 res = smu_v11_0_i2c_enable(control, enable: false);
528 if (res != I2C_OK) {
529 status = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS);
530 enable = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE);
531 en_stat = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE_STATUS);
532
533 /* Nobody is using the I2C engine, yet it remains
534 * active, possibly because someone missed to send
535 * STOP.
536 */
537 DRM_DEBUG_DRIVER("Aborting from fini: status:0x%08x "
538 "enable:0x%08x enable_stat:0x%08x",
539 status, enable, en_stat);
540 smu_v11_0_i2c_abort(control);
541 }
542
543 /* Restore clock gating */
544
545 /*
546 * TODO Reenabling clock gating seems to break subsequent SMU operation
547 * on the I2C bus. My guess is that SMU doesn't disable clock gating like
548 * we do here before working with the bus. So for now just don't restore
549 * it but later work with SMU to see if they have this issue and can
550 * update their code appropriately
551 */
552 /* smu_v11_0_i2c_set_clock_gating(control, true); */
553
554}
555
556static bool smu_v11_0_i2c_bus_lock(struct i2c_adapter *control)
557{
558 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(adap: control);
559 struct amdgpu_device *adev = smu_i2c->adev;
560
561 /* Send PPSMC_MSG_RequestI2CBus */
562 if (!amdgpu_dpm_smu_i2c_bus_access(adev, acquire: true))
563 return true;
564
565 return false;
566}
567
568static bool smu_v11_0_i2c_bus_unlock(struct i2c_adapter *control)
569{
570 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(adap: control);
571 struct amdgpu_device *adev = smu_i2c->adev;
572
573 /* Send PPSMC_MSG_ReleaseI2CBus */
574 if (!amdgpu_dpm_smu_i2c_bus_access(adev, acquire: false))
575 return true;
576
577 return false;
578}
579
580/***************************** I2C GLUE ****************************/
581
582static uint32_t smu_v11_0_i2c_read_data(struct i2c_adapter *control,
583 struct i2c_msg *msg, uint32_t i2c_flag)
584{
585 uint32_t ret;
586
587 ret = smu_v11_0_i2c_receive(control, address: msg->addr, data: msg->buf, numbytes: msg->len, i2c_flag);
588
589 if (ret != I2C_OK)
590 DRM_ERROR("ReadData() - I2C error occurred :%x", ret);
591
592 return ret;
593}
594
595static uint32_t smu_v11_0_i2c_write_data(struct i2c_adapter *control,
596 struct i2c_msg *msg, uint32_t i2c_flag)
597{
598 uint32_t ret;
599
600 ret = smu_v11_0_i2c_transmit(control, address: msg->addr, data: msg->buf, numbytes: msg->len, i2c_flag);
601
602 if (ret != I2C_OK)
603 DRM_ERROR("WriteI2CData() - I2C error occurred :%x", ret);
604
605 return ret;
606
607}
608
609static void lock_bus(struct i2c_adapter *i2c, unsigned int flags)
610{
611 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(adap: i2c);
612 struct amdgpu_device *adev = smu_i2c->adev;
613
614 mutex_lock(&smu_i2c->mutex);
615 if (!smu_v11_0_i2c_bus_lock(control: i2c))
616 DRM_ERROR("Failed to lock the bus from SMU");
617 else
618 adev->pm.bus_locked = true;
619}
620
621static int trylock_bus(struct i2c_adapter *i2c, unsigned int flags)
622{
623 WARN_ONCE(1, "This operation not supposed to run in atomic context!");
624 return false;
625}
626
627static void unlock_bus(struct i2c_adapter *i2c, unsigned int flags)
628{
629 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(adap: i2c);
630 struct amdgpu_device *adev = smu_i2c->adev;
631
632 if (!smu_v11_0_i2c_bus_unlock(control: i2c))
633 DRM_ERROR("Failed to unlock the bus from SMU");
634 else
635 adev->pm.bus_locked = false;
636 mutex_unlock(lock: &smu_i2c->mutex);
637}
638
639static const struct i2c_lock_operations smu_v11_0_i2c_i2c_lock_ops = {
640 .lock_bus = lock_bus,
641 .trylock_bus = trylock_bus,
642 .unlock_bus = unlock_bus,
643};
644
645static int smu_v11_0_i2c_xfer(struct i2c_adapter *i2c_adap,
646 struct i2c_msg *msg, int num)
647{
648 int i, ret;
649 u16 addr, dir;
650
651 smu_v11_0_i2c_init(control: i2c_adap);
652
653 /* From the client's point of view, this sequence of
654 * messages-- the array i2c_msg *msg, is a single transaction
655 * on the bus, starting with START and ending with STOP.
656 *
657 * The client is welcome to send any sequence of messages in
658 * this array, as processing under this function here is
659 * striving to be agnostic.
660 *
661 * Record the first address and direction we see. If either
662 * changes for a subsequent message, generate ReSTART. The
663 * DW_apb_i2c databook, v1.21a, specifies that ReSTART is
664 * generated when the direction changes, with the default IP
665 * block parameter settings, but it doesn't specify if ReSTART
666 * is generated when the address changes (possibly...). We
667 * don't rely on the default IP block parameter settings as
668 * the block is shared and they may change.
669 */
670 if (num > 0) {
671 addr = msg[0].addr;
672 dir = msg[0].flags & I2C_M_RD;
673 }
674
675 for (i = 0; i < num; i++) {
676 u32 i2c_flag = 0;
677
678 if (msg[i].addr != addr || (msg[i].flags ^ dir) & I2C_M_RD) {
679 addr = msg[i].addr;
680 dir = msg[i].flags & I2C_M_RD;
681 i2c_flag |= I2C_X_RESTART;
682 }
683
684 if (i == num - 1) {
685 /* Set the STOP bit on the last message, so
686 * that the IP block generates a STOP after
687 * the last byte of the message.
688 */
689 i2c_flag |= I2C_M_STOP;
690 }
691
692 if (msg[i].flags & I2C_M_RD)
693 ret = smu_v11_0_i2c_read_data(control: i2c_adap,
694 msg: msg + i,
695 i2c_flag);
696 else
697 ret = smu_v11_0_i2c_write_data(control: i2c_adap,
698 msg: msg + i,
699 i2c_flag);
700
701 if (ret != I2C_OK) {
702 num = -EIO;
703 break;
704 }
705 }
706
707 smu_v11_0_i2c_fini(control: i2c_adap);
708 return num;
709}
710
711static u32 smu_v11_0_i2c_func(struct i2c_adapter *adap)
712{
713 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
714}
715
716static const struct i2c_algorithm smu_v11_0_i2c_algo = {
717 .master_xfer = smu_v11_0_i2c_xfer,
718 .functionality = smu_v11_0_i2c_func,
719};
720
721static const struct i2c_adapter_quirks smu_v11_0_i2c_control_quirks = {
722 .flags = I2C_AQ_NO_ZERO_LEN,
723};
724
725int smu_v11_0_i2c_control_init(struct amdgpu_device *adev)
726{
727 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[0];
728 struct i2c_adapter *control = &smu_i2c->adapter;
729 int res;
730
731 smu_i2c->adev = adev;
732 smu_i2c->port = 0;
733 mutex_init(&smu_i2c->mutex);
734 control->owner = THIS_MODULE;
735 control->class = I2C_CLASS_HWMON;
736 control->dev.parent = &adev->pdev->dev;
737 control->algo = &smu_v11_0_i2c_algo;
738 snprintf(buf: control->name, size: sizeof(control->name), fmt: "AMDGPU SMU 0");
739 control->lock_ops = &smu_v11_0_i2c_i2c_lock_ops;
740 control->quirks = &smu_v11_0_i2c_control_quirks;
741 i2c_set_adapdata(adap: control, data: smu_i2c);
742
743 adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
744 adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
745
746 res = devm_i2c_add_adapter(dev: adev->dev, adapter: control);
747 if (res)
748 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
749
750 return res;
751}
752
753void smu_v11_0_i2c_control_fini(struct amdgpu_device *adev)
754{
755 adev->pm.ras_eeprom_i2c_bus = NULL;
756 adev->pm.fru_eeprom_i2c_bus = NULL;
757}
758
759/*
760 * Keep this for future unit test if bugs arise
761 */
762#if 0
763#define I2C_TARGET_ADDR 0xA0
764
765bool smu_v11_0_i2c_test_bus(struct i2c_adapter *control)
766{
767
768 uint32_t ret = I2C_OK;
769 uint8_t data[6] = {0xf, 0, 0xde, 0xad, 0xbe, 0xef};
770
771
772 DRM_INFO("Begin");
773
774 if (!smu_v11_0_i2c_bus_lock(control)) {
775 DRM_ERROR("Failed to lock the bus!.");
776 return false;
777 }
778
779 smu_v11_0_i2c_init(control);
780
781 /* Write 0xde to address 0x0000 on the EEPROM */
782 ret = smu_v11_0_i2c_write_data(control, I2C_TARGET_ADDR, data, 6);
783
784 ret = smu_v11_0_i2c_read_data(control, I2C_TARGET_ADDR, data, 6);
785
786 smu_v11_0_i2c_fini(control);
787
788 smu_v11_0_i2c_bus_unlock(control);
789
790
791 DRM_INFO("End");
792 return true;
793}
794#endif
795

source code of linux/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c