1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/delay.h>
25#include <linux/firmware.h>
26#include <linux/module.h>
27#include <linux/pci.h>
28
29#include "amdgpu.h"
30#include "amdgpu_ucode.h"
31#include "amdgpu_trace.h"
32
33#include "gc/gc_10_1_0_offset.h"
34#include "gc/gc_10_1_0_sh_mask.h"
35#include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h"
36#include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h"
37
38#include "soc15_common.h"
39#include "soc15.h"
40#include "navi10_sdma_pkt_open.h"
41#include "nbio_v2_3.h"
42#include "sdma_common.h"
43#include "sdma_v5_0.h"
44
45MODULE_FIRMWARE("amdgpu/navi10_sdma.bin");
46MODULE_FIRMWARE("amdgpu/navi10_sdma1.bin");
47
48MODULE_FIRMWARE("amdgpu/navi14_sdma.bin");
49MODULE_FIRMWARE("amdgpu/navi14_sdma1.bin");
50
51MODULE_FIRMWARE("amdgpu/navi12_sdma.bin");
52MODULE_FIRMWARE("amdgpu/navi12_sdma1.bin");
53
54MODULE_FIRMWARE("amdgpu/cyan_skillfish2_sdma.bin");
55MODULE_FIRMWARE("amdgpu/cyan_skillfish2_sdma1.bin");
56
57#define SDMA1_REG_OFFSET 0x600
58#define SDMA0_HYP_DEC_REG_START 0x5880
59#define SDMA0_HYP_DEC_REG_END 0x5893
60#define SDMA1_HYP_DEC_REG_OFFSET 0x20
61
62static const struct amdgpu_hwip_reg_entry sdma_reg_list_5_0[] = {
63 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS_REG),
64 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS1_REG),
65 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS2_REG),
66 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS3_REG),
67 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UCODE_CHECKSUM),
68 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RB_RPTR_FETCH_HI),
69 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RB_RPTR_FETCH),
70 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_RD_STATUS),
71 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_WR_STATUS),
72 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_RD_XNACK0),
73 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_RD_XNACK1),
74 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_WR_XNACK0),
75 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_WR_XNACK1),
76 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_CNTL),
77 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_RPTR),
78 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_RPTR_HI),
79 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_WPTR),
80 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_WPTR_HI),
81 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_OFFSET),
82 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_BASE_LO),
83 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_BASE_HI),
84 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_CNTL),
85 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_RPTR),
86 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_SUB_REMAIN),
87 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_DUMMY_REG),
88 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_CNTL),
89 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_RPTR),
90 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_RPTR_HI),
91 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_WPTR),
92 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_WPTR_HI),
93 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_IB_OFFSET),
94 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_IB_BASE_LO),
95 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_IB_BASE_HI),
96 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_DUMMY_REG),
97 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_CNTL),
98 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_RPTR),
99 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_RPTR_HI),
100 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_WPTR),
101 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_WPTR_HI),
102 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_IB_OFFSET),
103 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_IB_BASE_LO),
104 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_IB_BASE_HI),
105 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_DUMMY_REG),
106 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_INT_STATUS),
107 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_VM_CNTL),
108 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS2)
109};
110
111static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev);
112static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev);
113static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev);
114static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev);
115static int sdma_v5_0_stop_queue(struct amdgpu_ring *ring);
116static int sdma_v5_0_restore_queue(struct amdgpu_ring *ring);
117
118static const struct soc15_reg_golden golden_settings_sdma_5[] = {
119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_UTCL1_PAGE, 0x00ffffff, 0x000c5c00),
131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_UTCL1_PAGE, 0x00ffffff, 0x000c5c00)
143};
144
145static const struct soc15_reg_golden golden_settings_sdma_5_sriov[] = {
146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
166};
167
168static const struct soc15_reg_golden golden_settings_sdma_nv10[] = {
169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
171};
172
173static const struct soc15_reg_golden golden_settings_sdma_nv14[] = {
174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
176};
177
178static const struct soc15_reg_golden golden_settings_sdma_nv12[] = {
179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG, 0x001877ff, 0x00000044),
181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044),
182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG, 0x001877ff, 0x00000044),
183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044),
184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
185};
186
187static const struct soc15_reg_golden golden_settings_sdma_cyan_skillfish[] = {
188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG, 0x001877ff, 0x00000044),
190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044),
191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_UTCL1_PAGE, 0x007fffff, 0x004c5c00),
202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG, 0x001877ff, 0x00000044),
204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044),
205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_UTCL1_PAGE, 0x007fffff, 0x004c5c00)
216};
217
218static u32 sdma_v5_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
219{
220 u32 base;
221
222 if (internal_offset >= SDMA0_HYP_DEC_REG_START &&
223 internal_offset <= SDMA0_HYP_DEC_REG_END) {
224 base = adev->reg_offset[GC_HWIP][0][1];
225 if (instance == 1)
226 internal_offset += SDMA1_HYP_DEC_REG_OFFSET;
227 } else {
228 base = adev->reg_offset[GC_HWIP][0][0];
229 if (instance == 1)
230 internal_offset += SDMA1_REG_OFFSET;
231 }
232
233 return base + internal_offset;
234}
235
236static void sdma_v5_0_init_golden_registers(struct amdgpu_device *adev)
237{
238 switch (amdgpu_ip_version(adev, ip: SDMA0_HWIP, inst: 0)) {
239 case IP_VERSION(5, 0, 0):
240 soc15_program_register_sequence(adev,
241 registers: golden_settings_sdma_5,
242 array_size: (const u32)ARRAY_SIZE(golden_settings_sdma_5));
243 soc15_program_register_sequence(adev,
244 registers: golden_settings_sdma_nv10,
245 array_size: (const u32)ARRAY_SIZE(golden_settings_sdma_nv10));
246 break;
247 case IP_VERSION(5, 0, 2):
248 soc15_program_register_sequence(adev,
249 registers: golden_settings_sdma_5,
250 array_size: (const u32)ARRAY_SIZE(golden_settings_sdma_5));
251 soc15_program_register_sequence(adev,
252 registers: golden_settings_sdma_nv14,
253 array_size: (const u32)ARRAY_SIZE(golden_settings_sdma_nv14));
254 break;
255 case IP_VERSION(5, 0, 5):
256 if (amdgpu_sriov_vf(adev))
257 soc15_program_register_sequence(adev,
258 registers: golden_settings_sdma_5_sriov,
259 array_size: (const u32)ARRAY_SIZE(golden_settings_sdma_5_sriov));
260 else
261 soc15_program_register_sequence(adev,
262 registers: golden_settings_sdma_5,
263 array_size: (const u32)ARRAY_SIZE(golden_settings_sdma_5));
264 soc15_program_register_sequence(adev,
265 registers: golden_settings_sdma_nv12,
266 array_size: (const u32)ARRAY_SIZE(golden_settings_sdma_nv12));
267 break;
268 case IP_VERSION(5, 0, 1):
269 soc15_program_register_sequence(adev,
270 registers: golden_settings_sdma_cyan_skillfish,
271 array_size: (const u32)ARRAY_SIZE(golden_settings_sdma_cyan_skillfish));
272 break;
273 default:
274 break;
275 }
276}
277
278/**
279 * sdma_v5_0_init_microcode - load ucode images from disk
280 *
281 * @adev: amdgpu_device pointer
282 *
283 * Use the firmware interface to load the ucode images into
284 * the driver (not loaded into hw).
285 * Returns 0 on success, error on failure.
286 */
287
288// emulation only, won't work on real chip
289// navi10 real chip need to use PSP to load firmware
290static int sdma_v5_0_init_microcode(struct amdgpu_device *adev)
291{
292 int ret, i;
293
294 for (i = 0; i < adev->sdma.num_instances; i++) {
295 ret = amdgpu_sdma_init_microcode(adev, instance: i, duplicate: false);
296 if (ret)
297 return ret;
298 }
299
300 return ret;
301}
302
303static unsigned sdma_v5_0_ring_init_cond_exec(struct amdgpu_ring *ring,
304 uint64_t addr)
305{
306 unsigned ret;
307
308 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
309 amdgpu_ring_write(ring, lower_32_bits(addr));
310 amdgpu_ring_write(ring, upper_32_bits(addr));
311 amdgpu_ring_write(ring, v: 1);
312 /* this is the offset we need patch later */
313 ret = ring->wptr & ring->buf_mask;
314 /* insert dummy here and patch it later */
315 amdgpu_ring_write(ring, v: 0);
316
317 return ret;
318}
319
320/**
321 * sdma_v5_0_ring_get_rptr - get the current read pointer
322 *
323 * @ring: amdgpu ring pointer
324 *
325 * Get the current rptr from the hardware (NAVI10+).
326 */
327static uint64_t sdma_v5_0_ring_get_rptr(struct amdgpu_ring *ring)
328{
329 u64 *rptr;
330
331 /* XXX check if swapping is necessary on BE */
332 rptr = (u64 *)ring->rptr_cpu_addr;
333
334 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
335 return ((*rptr) >> 2);
336}
337
338/**
339 * sdma_v5_0_ring_get_wptr - get the current write pointer
340 *
341 * @ring: amdgpu ring pointer
342 *
343 * Get the current wptr from the hardware (NAVI10+).
344 */
345static uint64_t sdma_v5_0_ring_get_wptr(struct amdgpu_ring *ring)
346{
347 struct amdgpu_device *adev = ring->adev;
348 u64 wptr;
349
350 if (ring->use_doorbell) {
351 /* XXX check if swapping is necessary on BE */
352 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr));
353 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
354 } else {
355 wptr = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI));
356 wptr = wptr << 32;
357 wptr |= RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR));
358 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr);
359 }
360
361 return wptr >> 2;
362}
363
364/**
365 * sdma_v5_0_ring_set_wptr - commit the write pointer
366 *
367 * @ring: amdgpu ring pointer
368 *
369 * Write the wptr back to the hardware (NAVI10+).
370 */
371static void sdma_v5_0_ring_set_wptr(struct amdgpu_ring *ring)
372{
373 struct amdgpu_device *adev = ring->adev;
374
375 DRM_DEBUG("Setting write pointer\n");
376 if (ring->use_doorbell) {
377 DRM_DEBUG("Using doorbell -- "
378 "wptr_offs == 0x%08x "
379 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
380 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
381 ring->wptr_offs,
382 lower_32_bits(ring->wptr << 2),
383 upper_32_bits(ring->wptr << 2));
384 /* XXX check if swapping is necessary on BE */
385 atomic64_set(v: (atomic64_t *)ring->wptr_cpu_addr,
386 i: ring->wptr << 2);
387 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
388 ring->doorbell_index, ring->wptr << 2);
389 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
390 } else {
391 DRM_DEBUG("Not using doorbell -- "
392 "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
393 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
394 ring->me,
395 lower_32_bits(ring->wptr << 2),
396 ring->me,
397 upper_32_bits(ring->wptr << 2));
398 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev,
399 ring->me, mmSDMA0_GFX_RB_WPTR),
400 lower_32_bits(ring->wptr << 2));
401 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev,
402 ring->me, mmSDMA0_GFX_RB_WPTR_HI),
403 upper_32_bits(ring->wptr << 2));
404 }
405}
406
407static void sdma_v5_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
408{
409 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
410 int i;
411
412 for (i = 0; i < count; i++)
413 if (sdma && sdma->burst_nop && (i == 0))
414 amdgpu_ring_write(ring, v: ring->funcs->nop |
415 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
416 else
417 amdgpu_ring_write(ring, v: ring->funcs->nop);
418}
419
420/**
421 * sdma_v5_0_ring_emit_ib - Schedule an IB on the DMA engine
422 *
423 * @ring: amdgpu ring pointer
424 * @job: job to retrieve vmid from
425 * @ib: IB object to schedule
426 * @flags: unused
427 *
428 * Schedule an IB in the DMA ring (NAVI10).
429 */
430static void sdma_v5_0_ring_emit_ib(struct amdgpu_ring *ring,
431 struct amdgpu_job *job,
432 struct amdgpu_ib *ib,
433 uint32_t flags)
434{
435 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
436 uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
437
438 /* An IB packet must end on a 8 DW boundary--the next dword
439 * must be on a 8-dword boundary. Our IB packet below is 6
440 * dwords long, thus add x number of NOPs, such that, in
441 * modular arithmetic,
442 * wptr + 6 + x = 8k, k >= 0, which in C is,
443 * (wptr + 6 + x) % 8 = 0.
444 * The expression below, is a solution of x.
445 */
446 sdma_v5_0_ring_insert_nop(ring, count: (2 - lower_32_bits(ring->wptr)) & 7);
447
448 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
449 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
450 /* base must be 32 byte aligned */
451 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
452 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
453 amdgpu_ring_write(ring, v: ib->length_dw);
454 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
455 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
456}
457
458/**
459 * sdma_v5_0_ring_emit_mem_sync - flush the IB by graphics cache rinse
460 *
461 * @ring: amdgpu ring pointer
462 *
463 * flush the IB by graphics cache rinse.
464 */
465static void sdma_v5_0_ring_emit_mem_sync(struct amdgpu_ring *ring)
466{
467 uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV |
468 SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV |
469 SDMA_GCR_GLI_INV(1);
470
471 /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */
472 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ));
473 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0));
474 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) |
475 SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0));
476 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) |
477 SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16));
478 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) |
479 SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0));
480}
481
482/**
483 * sdma_v5_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
484 *
485 * @ring: amdgpu ring pointer
486 *
487 * Emit an hdp flush packet on the requested DMA ring.
488 */
489static void sdma_v5_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
490{
491 struct amdgpu_device *adev = ring->adev;
492 u32 ref_and_mask = 0;
493 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
494
495 if (ring->me == 0)
496 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0;
497 else
498 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1;
499
500 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
501 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
502 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
503 amdgpu_ring_write(ring, v: (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
504 amdgpu_ring_write(ring, v: (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
505 amdgpu_ring_write(ring, v: ref_and_mask); /* reference */
506 amdgpu_ring_write(ring, v: ref_and_mask); /* mask */
507 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
508 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
509}
510
511/**
512 * sdma_v5_0_ring_emit_fence - emit a fence on the DMA ring
513 *
514 * @ring: amdgpu ring pointer
515 * @addr: address
516 * @seq: sequence number
517 * @flags: fence related flags
518 *
519 * Add a DMA fence packet to the ring to write
520 * the fence seq number and DMA trap packet to generate
521 * an interrupt if needed (NAVI10).
522 */
523static void sdma_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
524 unsigned flags)
525{
526 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
527 /* write the fence */
528 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
529 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */
530 /* zero in first two bits */
531 BUG_ON(addr & 0x3);
532 amdgpu_ring_write(ring, lower_32_bits(addr));
533 amdgpu_ring_write(ring, upper_32_bits(addr));
534 amdgpu_ring_write(ring, lower_32_bits(seq));
535
536 /* optionally write high bits as well */
537 if (write64bit) {
538 addr += 4;
539 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
540 SDMA_PKT_FENCE_HEADER_MTYPE(0x3));
541 /* zero in first two bits */
542 BUG_ON(addr & 0x3);
543 amdgpu_ring_write(ring, lower_32_bits(addr));
544 amdgpu_ring_write(ring, upper_32_bits(addr));
545 amdgpu_ring_write(ring, upper_32_bits(seq));
546 }
547
548 if (flags & AMDGPU_FENCE_FLAG_INT) {
549 /* generate an interrupt */
550 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
551 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
552 }
553}
554
555
556/**
557 * sdma_v5_0_gfx_stop - stop the gfx async dma engines
558 *
559 * @adev: amdgpu_device pointer
560 * @inst_mask: mask of dma engine instances to be disabled
561 * Stop the gfx async dma ring buffers (NAVI10).
562 */
563static void sdma_v5_0_gfx_stop(struct amdgpu_device *adev, uint32_t inst_mask)
564{
565 u32 rb_cntl, ib_cntl;
566 int i;
567
568 for_each_inst(i, inst_mask) {
569 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
570 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
571 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
572 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
573 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
574 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
575 }
576}
577
578/**
579 * sdma_v5_0_rlc_stop - stop the compute async dma engines
580 *
581 * @adev: amdgpu_device pointer
582 *
583 * Stop the compute async dma queues (NAVI10).
584 */
585static void sdma_v5_0_rlc_stop(struct amdgpu_device *adev)
586{
587 /* XXX todo */
588}
589
590/**
591 * sdma_v5_0_ctx_switch_enable - stop the async dma engines context switch
592 *
593 * @adev: amdgpu_device pointer
594 * @enable: enable/disable the DMA MEs context switch.
595 *
596 * Halt or unhalt the async dma engines context switch (NAVI10).
597 */
598static void sdma_v5_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
599{
600 u32 f32_cntl = 0, phase_quantum = 0;
601 int i;
602
603 if (amdgpu_sdma_phase_quantum) {
604 unsigned value = amdgpu_sdma_phase_quantum;
605 unsigned unit = 0;
606
607 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
608 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
609 value = (value + 1) >> 1;
610 unit++;
611 }
612 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
613 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
614 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
615 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
616 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
617 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
618 WARN_ONCE(1,
619 "clamping sdma_phase_quantum to %uK clock cycles\n",
620 value << unit);
621 }
622 phase_quantum =
623 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
624 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
625 }
626
627 for (i = 0; i < adev->sdma.num_instances; i++) {
628 if (!amdgpu_sriov_vf(adev)) {
629 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
630 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
631 AUTO_CTXSW_ENABLE, enable ? 1 : 0);
632 }
633
634 if (enable && amdgpu_sdma_phase_quantum) {
635 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
636 phase_quantum);
637 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
638 phase_quantum);
639 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
640 phase_quantum);
641 }
642 if (!amdgpu_sriov_vf(adev))
643 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
644 }
645
646}
647
648/**
649 * sdma_v5_0_enable - stop the async dma engines
650 *
651 * @adev: amdgpu_device pointer
652 * @enable: enable/disable the DMA MEs.
653 *
654 * Halt or unhalt the async dma engines (NAVI10).
655 */
656static void sdma_v5_0_enable(struct amdgpu_device *adev, bool enable)
657{
658 u32 f32_cntl;
659 int i;
660 uint32_t inst_mask;
661
662 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
663 if (!enable) {
664 sdma_v5_0_gfx_stop(adev, inst_mask: 1 << inst_mask);
665 sdma_v5_0_rlc_stop(adev);
666 }
667
668 if (amdgpu_sriov_vf(adev))
669 return;
670
671 for (i = 0; i < adev->sdma.num_instances; i++) {
672 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
673 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
674 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
675 }
676}
677
678/**
679 * sdma_v5_0_gfx_resume_instance - start/restart a certain sdma engine
680 *
681 * @adev: amdgpu_device pointer
682 * @i: instance
683 * @restore: used to restore wptr when restart
684 *
685 * Set up the gfx DMA ring buffers and enable them. On restart, we will restore wptr and rptr.
686 * Return 0 for success.
687 */
688static int sdma_v5_0_gfx_resume_instance(struct amdgpu_device *adev, int i, bool restore)
689{
690 struct amdgpu_ring *ring;
691 u32 rb_cntl, ib_cntl;
692 u32 rb_bufsz;
693 u32 doorbell;
694 u32 doorbell_offset;
695 u32 temp;
696 u32 wptr_poll_cntl;
697 u64 wptr_gpu_addr;
698
699 ring = &adev->sdma.instance[i].ring;
700
701 if (!amdgpu_sriov_vf(adev))
702 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
703
704 /* Set ring buffer size in dwords */
705 rb_bufsz = order_base_2(ring->ring_size / 4);
706 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
707 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
708#ifdef __BIG_ENDIAN
709 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
710 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
711 RPTR_WRITEBACK_SWAP_ENABLE, 1);
712#endif
713 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
714
715 /* Initialize the ring buffer's read and write pointers */
716 if (restore) {
717 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), lower_32_bits(ring->wptr << 2));
718 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), upper_32_bits(ring->wptr << 2));
719 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));
720 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));
721 } else {
722 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
723 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
724 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
725 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
726 }
727 /* setup the wptr shadow polling */
728 wptr_gpu_addr = ring->wptr_gpu_addr;
729 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
730 lower_32_bits(wptr_gpu_addr));
731 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
732 upper_32_bits(wptr_gpu_addr));
733 wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i,
734 mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
735 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
736 SDMA0_GFX_RB_WPTR_POLL_CNTL,
737 F32_POLL_ENABLE, 1);
738 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),
739 wptr_poll_cntl);
740
741 /* set the wb address whether it's enabled or not */
742 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
743 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);
744 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
745 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
746
747 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
748
749 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE),
750 ring->gpu_addr >> 8);
751 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI),
752 ring->gpu_addr >> 40);
753
754 if (!restore)
755 ring->wptr = 0;
756
757 /* before programing wptr to a less value, need set minor_ptr_update first */
758 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
759
760 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
761 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR),
762 lower_32_bits(ring->wptr << 2));
763 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI),
764 upper_32_bits(ring->wptr << 2));
765 }
766
767 doorbell = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
768 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i,
769 mmSDMA0_GFX_DOORBELL_OFFSET));
770
771 if (ring->use_doorbell) {
772 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
773 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,
774 OFFSET, ring->doorbell_index);
775 } else {
776 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
777 }
778 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
779 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET),
780 doorbell_offset);
781
782 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
783 ring->doorbell_index, 20);
784
785 if (amdgpu_sriov_vf(adev))
786 sdma_v5_0_ring_set_wptr(ring);
787
788 /* set minor_ptr_update to 0 after wptr programed */
789 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
790
791 if (!amdgpu_sriov_vf(adev)) {
792 /* set utc l1 enable flag always to 1 */
793 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
794 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
795
796 /* enable MCBP */
797 temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);
798 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
799
800 /* Set up RESP_MODE to non-copy addresses */
801 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));
802 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
803 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
804 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);
805
806 /* program default cache read and write policy */
807 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));
808 /* clean read policy and write policy bits */
809 temp &= 0xFF0FFF;
810 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | (CACHE_WRITE_POLICY_L2__DEFAULT << 14));
811 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);
812 }
813
814 if (!amdgpu_sriov_vf(adev)) {
815 /* unhalt engine */
816 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
817 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
818 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);
819 }
820
821 /* enable DMA RB */
822 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
823 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
824
825 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
826 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
827#ifdef __BIG_ENDIAN
828 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
829#endif
830 /* enable DMA IBs */
831 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
832
833 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
834 sdma_v5_0_ctx_switch_enable(adev, enable: true);
835 sdma_v5_0_enable(adev, enable: true);
836 }
837
838 return amdgpu_ring_test_helper(ring);
839}
840
841/**
842 * sdma_v5_0_gfx_resume - setup and start the async dma engines
843 *
844 * @adev: amdgpu_device pointer
845 *
846 * Set up the gfx DMA ring buffers and enable them (NAVI10).
847 * Returns 0 for success, error for failure.
848 */
849static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev)
850{
851 int i, r;
852
853 for (i = 0; i < adev->sdma.num_instances; i++) {
854 r = sdma_v5_0_gfx_resume_instance(adev, i, restore: false);
855 if (r)
856 return r;
857 }
858
859 return 0;
860}
861
862/**
863 * sdma_v5_0_rlc_resume - setup and start the async dma engines
864 *
865 * @adev: amdgpu_device pointer
866 *
867 * Set up the compute DMA queues and enable them (NAVI10).
868 * Returns 0 for success, error for failure.
869 */
870static int sdma_v5_0_rlc_resume(struct amdgpu_device *adev)
871{
872 return 0;
873}
874
875/**
876 * sdma_v5_0_load_microcode - load the sDMA ME ucode
877 *
878 * @adev: amdgpu_device pointer
879 *
880 * Loads the sDMA0/1 ucode.
881 * Returns 0 for success, -EINVAL if the ucode is not available.
882 */
883static int sdma_v5_0_load_microcode(struct amdgpu_device *adev)
884{
885 const struct sdma_firmware_header_v1_0 *hdr;
886 const __le32 *fw_data;
887 u32 fw_size;
888 int i, j;
889
890 /* halt the MEs */
891 sdma_v5_0_enable(adev, enable: false);
892
893 for (i = 0; i < adev->sdma.num_instances; i++) {
894 if (!adev->sdma.instance[i].fw)
895 return -EINVAL;
896
897 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
898 amdgpu_ucode_print_sdma_hdr(hdr: &hdr->header);
899 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
900
901 fw_data = (const __le32 *)
902 (adev->sdma.instance[i].fw->data +
903 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
904
905 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0);
906
907 for (j = 0; j < fw_size; j++) {
908 if (amdgpu_emu_mode == 1 && j % 500 == 0)
909 msleep(msecs: 1);
910 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
911 }
912
913 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
914 }
915
916 return 0;
917}
918
919/**
920 * sdma_v5_0_start - setup and start the async dma engines
921 *
922 * @adev: amdgpu_device pointer
923 *
924 * Set up the DMA engines and enable them (NAVI10).
925 * Returns 0 for success, error for failure.
926 */
927static int sdma_v5_0_start(struct amdgpu_device *adev)
928{
929 int r = 0;
930
931 if (amdgpu_sriov_vf(adev)) {
932 sdma_v5_0_ctx_switch_enable(adev, enable: false);
933 sdma_v5_0_enable(adev, enable: false);
934
935 /* set RB registers */
936 r = sdma_v5_0_gfx_resume(adev);
937 return r;
938 }
939
940 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
941 r = sdma_v5_0_load_microcode(adev);
942 if (r)
943 return r;
944 }
945
946 /* unhalt the MEs */
947 sdma_v5_0_enable(adev, enable: true);
948 /* enable sdma ring preemption */
949 sdma_v5_0_ctx_switch_enable(adev, enable: true);
950
951 /* start the gfx rings and rlc compute queues */
952 r = sdma_v5_0_gfx_resume(adev);
953 if (r)
954 return r;
955 r = sdma_v5_0_rlc_resume(adev);
956
957 return r;
958}
959
960static int sdma_v5_0_mqd_init(struct amdgpu_device *adev, void *mqd,
961 struct amdgpu_mqd_prop *prop)
962{
963 struct v10_sdma_mqd *m = mqd;
964 uint64_t wb_gpu_addr;
965
966 m->sdmax_rlcx_rb_cntl =
967 order_base_2(prop->queue_size / 4) << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT |
968 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
969 6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT |
970 1 << SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT;
971
972 m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8);
973 m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8);
974
975 m->sdmax_rlcx_rb_wptr_poll_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, 0,
976 mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
977
978 wb_gpu_addr = prop->wptr_gpu_addr;
979 m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr);
980 m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr);
981
982 wb_gpu_addr = prop->rptr_gpu_addr;
983 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr);
984 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr);
985
986 m->sdmax_rlcx_ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, 0,
987 mmSDMA0_GFX_IB_CNTL));
988
989 m->sdmax_rlcx_doorbell_offset =
990 prop->doorbell_index << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT;
991
992 m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_RLC0_DOORBELL, ENABLE, 1);
993
994 return 0;
995}
996
997static void sdma_v5_0_set_mqd_funcs(struct amdgpu_device *adev)
998{
999 adev->mqds[AMDGPU_HW_IP_DMA].mqd_size = sizeof(struct v10_sdma_mqd);
1000 adev->mqds[AMDGPU_HW_IP_DMA].init_mqd = sdma_v5_0_mqd_init;
1001}
1002
1003/**
1004 * sdma_v5_0_ring_test_ring - simple async dma engine test
1005 *
1006 * @ring: amdgpu_ring structure holding ring information
1007 *
1008 * Test the DMA engine by writing using it to write an
1009 * value to memory. (NAVI10).
1010 * Returns 0 for success, error for failure.
1011 */
1012static int sdma_v5_0_ring_test_ring(struct amdgpu_ring *ring)
1013{
1014 struct amdgpu_device *adev = ring->adev;
1015 unsigned i;
1016 unsigned index;
1017 int r;
1018 u32 tmp;
1019 u64 gpu_addr;
1020
1021 tmp = 0xCAFEDEAD;
1022
1023 r = amdgpu_device_wb_get(adev, wb: &index);
1024 if (r) {
1025 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
1026 return r;
1027 }
1028
1029 gpu_addr = adev->wb.gpu_addr + (index * 4);
1030 adev->wb.wb[index] = cpu_to_le32(tmp);
1031
1032 r = amdgpu_ring_alloc(ring, ndw: 20);
1033 if (r) {
1034 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
1035 amdgpu_device_wb_free(adev, wb: index);
1036 return r;
1037 }
1038
1039 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1040 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
1041 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
1042 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
1043 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
1044 amdgpu_ring_write(ring, v: 0xDEADBEEF);
1045 amdgpu_ring_commit(ring);
1046
1047 for (i = 0; i < adev->usec_timeout; i++) {
1048 tmp = le32_to_cpu(adev->wb.wb[index]);
1049 if (tmp == 0xDEADBEEF)
1050 break;
1051 if (amdgpu_emu_mode == 1)
1052 msleep(msecs: 1);
1053 else
1054 udelay(usec: 1);
1055 }
1056
1057 if (i >= adev->usec_timeout)
1058 r = -ETIMEDOUT;
1059
1060 amdgpu_device_wb_free(adev, wb: index);
1061
1062 return r;
1063}
1064
1065/**
1066 * sdma_v5_0_ring_test_ib - test an IB on the DMA engine
1067 *
1068 * @ring: amdgpu_ring structure holding ring information
1069 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
1070 *
1071 * Test a simple IB in the DMA ring (NAVI10).
1072 * Returns 0 on success, error on failure.
1073 */
1074static int sdma_v5_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1075{
1076 struct amdgpu_device *adev = ring->adev;
1077 struct amdgpu_ib ib;
1078 struct dma_fence *f = NULL;
1079 unsigned index;
1080 long r;
1081 u32 tmp = 0;
1082 u64 gpu_addr;
1083
1084 tmp = 0xCAFEDEAD;
1085 memset(&ib, 0, sizeof(ib));
1086
1087 r = amdgpu_device_wb_get(adev, wb: &index);
1088 if (r) {
1089 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
1090 return r;
1091 }
1092
1093 gpu_addr = adev->wb.gpu_addr + (index * 4);
1094 adev->wb.wb[index] = cpu_to_le32(tmp);
1095
1096 r = amdgpu_ib_get(adev, NULL, size: 256,
1097 pool: AMDGPU_IB_POOL_DIRECT, ib: &ib);
1098 if (r) {
1099 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
1100 goto err0;
1101 }
1102
1103 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1104 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1105 ib.ptr[1] = lower_32_bits(gpu_addr);
1106 ib.ptr[2] = upper_32_bits(gpu_addr);
1107 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
1108 ib.ptr[4] = 0xDEADBEEF;
1109 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1110 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1111 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1112 ib.length_dw = 8;
1113
1114 r = amdgpu_ib_schedule(ring, num_ibs: 1, ibs: &ib, NULL, f: &f);
1115 if (r)
1116 goto err1;
1117
1118 r = dma_fence_wait_timeout(f, intr: false, timeout);
1119 if (r == 0) {
1120 DRM_ERROR("amdgpu: IB test timed out\n");
1121 r = -ETIMEDOUT;
1122 goto err1;
1123 } else if (r < 0) {
1124 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1125 goto err1;
1126 }
1127
1128 tmp = le32_to_cpu(adev->wb.wb[index]);
1129
1130 if (tmp == 0xDEADBEEF)
1131 r = 0;
1132 else
1133 r = -EINVAL;
1134
1135err1:
1136 amdgpu_ib_free(ib: &ib, NULL);
1137 dma_fence_put(fence: f);
1138err0:
1139 amdgpu_device_wb_free(adev, wb: index);
1140 return r;
1141}
1142
1143
1144/**
1145 * sdma_v5_0_vm_copy_pte - update PTEs by copying them from the GART
1146 *
1147 * @ib: indirect buffer to fill with commands
1148 * @pe: addr of the page entry
1149 * @src: src addr to copy from
1150 * @count: number of page entries to update
1151 *
1152 * Update PTEs by copying them from the GART using sDMA (NAVI10).
1153 */
1154static void sdma_v5_0_vm_copy_pte(struct amdgpu_ib *ib,
1155 uint64_t pe, uint64_t src,
1156 unsigned count)
1157{
1158 unsigned bytes = count * 8;
1159
1160 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1161 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1162 ib->ptr[ib->length_dw++] = bytes - 1;
1163 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1164 ib->ptr[ib->length_dw++] = lower_32_bits(src);
1165 ib->ptr[ib->length_dw++] = upper_32_bits(src);
1166 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1167 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1168
1169}
1170
1171/**
1172 * sdma_v5_0_vm_write_pte - update PTEs by writing them manually
1173 *
1174 * @ib: indirect buffer to fill with commands
1175 * @pe: addr of the page entry
1176 * @value: dst addr to write into pe
1177 * @count: number of page entries to update
1178 * @incr: increase next addr by incr bytes
1179 *
1180 * Update PTEs by writing them manually using sDMA (NAVI10).
1181 */
1182static void sdma_v5_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1183 uint64_t value, unsigned count,
1184 uint32_t incr)
1185{
1186 unsigned ndw = count * 2;
1187
1188 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1189 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1190 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1191 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1192 ib->ptr[ib->length_dw++] = ndw - 1;
1193 for (; ndw > 0; ndw -= 2) {
1194 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1195 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1196 value += incr;
1197 }
1198}
1199
1200/**
1201 * sdma_v5_0_vm_set_pte_pde - update the page tables using sDMA
1202 *
1203 * @ib: indirect buffer to fill with commands
1204 * @pe: addr of the page entry
1205 * @addr: dst addr to write into pe
1206 * @count: number of page entries to update
1207 * @incr: increase next addr by incr bytes
1208 * @flags: access flags
1209 *
1210 * Update the page tables using sDMA (NAVI10).
1211 */
1212static void sdma_v5_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1213 uint64_t pe,
1214 uint64_t addr, unsigned count,
1215 uint32_t incr, uint64_t flags)
1216{
1217 /* for physically contiguous pages (vram) */
1218 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1219 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1220 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1221 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1222 ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1223 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1224 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1225 ib->ptr[ib->length_dw++] = incr; /* increment size */
1226 ib->ptr[ib->length_dw++] = 0;
1227 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1228}
1229
1230/**
1231 * sdma_v5_0_ring_pad_ib - pad the IB
1232 * @ring: amdgpu_ring structure holding ring information
1233 * @ib: indirect buffer to fill with padding
1234 *
1235 * Pad the IB with NOPs to a boundary multiple of 8.
1236 */
1237static void sdma_v5_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1238{
1239 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1240 u32 pad_count;
1241 int i;
1242
1243 pad_count = (-ib->length_dw) & 0x7;
1244 for (i = 0; i < pad_count; i++)
1245 if (sdma && sdma->burst_nop && (i == 0))
1246 ib->ptr[ib->length_dw++] =
1247 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1248 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1249 else
1250 ib->ptr[ib->length_dw++] =
1251 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1252}
1253
1254
1255/**
1256 * sdma_v5_0_ring_emit_pipeline_sync - sync the pipeline
1257 *
1258 * @ring: amdgpu_ring pointer
1259 *
1260 * Make sure all previous operations are completed (CIK).
1261 */
1262static void sdma_v5_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1263{
1264 uint32_t seq = ring->fence_drv.sync_seq;
1265 uint64_t addr = ring->fence_drv.gpu_addr;
1266
1267 /* wait for idle */
1268 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1269 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1270 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1271 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1272 amdgpu_ring_write(ring, v: addr & 0xfffffffc);
1273 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1274 amdgpu_ring_write(ring, v: seq); /* reference */
1275 amdgpu_ring_write(ring, v: 0xffffffff); /* mask */
1276 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1277 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1278}
1279
1280
1281/**
1282 * sdma_v5_0_ring_emit_vm_flush - vm flush using sDMA
1283 *
1284 * @ring: amdgpu_ring pointer
1285 * @vmid: vmid number to use
1286 * @pd_addr: address
1287 *
1288 * Update the page table base and flush the VM TLB
1289 * using sDMA (NAVI10).
1290 */
1291static void sdma_v5_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1292 unsigned vmid, uint64_t pd_addr)
1293{
1294 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1295}
1296
1297static void sdma_v5_0_ring_emit_wreg(struct amdgpu_ring *ring,
1298 uint32_t reg, uint32_t val)
1299{
1300 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1301 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1302 amdgpu_ring_write(ring, v: reg);
1303 amdgpu_ring_write(ring, v: val);
1304}
1305
1306static void sdma_v5_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1307 uint32_t val, uint32_t mask)
1308{
1309 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1310 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1311 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1312 amdgpu_ring_write(ring, v: reg << 2);
1313 amdgpu_ring_write(ring, v: 0);
1314 amdgpu_ring_write(ring, v: val); /* reference */
1315 amdgpu_ring_write(ring, v: mask); /* mask */
1316 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1317 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1318}
1319
1320static void sdma_v5_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
1321 uint32_t reg0, uint32_t reg1,
1322 uint32_t ref, uint32_t mask)
1323{
1324 amdgpu_ring_emit_wreg(ring, reg0, ref);
1325 /* wait for a cycle to reset vm_inv_eng*_ack */
1326 amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0);
1327 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
1328}
1329
1330static int sdma_v5_0_soft_reset_engine(struct amdgpu_device *adev, u32 instance_id)
1331{
1332 u32 grbm_soft_reset;
1333 u32 tmp;
1334
1335 grbm_soft_reset = REG_SET_FIELD(0,
1336 GRBM_SOFT_RESET, SOFT_RESET_SDMA0,
1337 1);
1338 grbm_soft_reset <<= instance_id;
1339
1340 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
1341 tmp |= grbm_soft_reset;
1342 DRM_DEBUG("GRBM_SOFT_RESET=0x%08X\n", tmp);
1343 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
1344 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
1345
1346 udelay(usec: 50);
1347
1348 tmp &= ~grbm_soft_reset;
1349 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
1350 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
1351 return 0;
1352}
1353
1354static const struct amdgpu_sdma_funcs sdma_v5_0_sdma_funcs = {
1355 .stop_kernel_queue = &sdma_v5_0_stop_queue,
1356 .start_kernel_queue = &sdma_v5_0_restore_queue,
1357 .soft_reset_kernel_queue = &sdma_v5_0_soft_reset_engine,
1358};
1359
1360static int sdma_v5_0_early_init(struct amdgpu_ip_block *ip_block)
1361{
1362 struct amdgpu_device *adev = ip_block->adev;
1363 int r;
1364
1365 r = sdma_v5_0_init_microcode(adev);
1366 if (r)
1367 return r;
1368
1369 sdma_v5_0_set_ring_funcs(adev);
1370 sdma_v5_0_set_buffer_funcs(adev);
1371 sdma_v5_0_set_vm_pte_funcs(adev);
1372 sdma_v5_0_set_irq_funcs(adev);
1373 sdma_v5_0_set_mqd_funcs(adev);
1374
1375 return 0;
1376}
1377
1378
1379static int sdma_v5_0_sw_init(struct amdgpu_ip_block *ip_block)
1380{
1381 struct amdgpu_ring *ring;
1382 int r, i;
1383 struct amdgpu_device *adev = ip_block->adev;
1384 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_5_0);
1385 uint32_t *ptr;
1386
1387 /* SDMA trap event */
1388 r = amdgpu_irq_add_id(adev, client_id: SOC15_IH_CLIENTID_SDMA0,
1389 SDMA0_5_0__SRCID__SDMA_TRAP,
1390 source: &adev->sdma.trap_irq);
1391 if (r)
1392 return r;
1393
1394 /* SDMA trap event */
1395 r = amdgpu_irq_add_id(adev, client_id: SOC15_IH_CLIENTID_SDMA1,
1396 SDMA1_5_0__SRCID__SDMA_TRAP,
1397 source: &adev->sdma.trap_irq);
1398 if (r)
1399 return r;
1400
1401 for (i = 0; i < adev->sdma.num_instances; i++) {
1402 mutex_init(&adev->sdma.instance[i].engine_reset_mutex);
1403 adev->sdma.instance[i].funcs = &sdma_v5_0_sdma_funcs;
1404 ring = &adev->sdma.instance[i].ring;
1405 ring->ring_obj = NULL;
1406 ring->use_doorbell = true;
1407
1408 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i,
1409 ring->use_doorbell?"true":"false");
1410
1411 ring->doorbell_index = (i == 0) ?
1412 (adev->doorbell_index.sdma_engine[0] << 1) //get DWORD offset
1413 : (adev->doorbell_index.sdma_engine[1] << 1); // get DWORD offset
1414
1415 ring->vm_hub = AMDGPU_GFXHUB(0);
1416 sprintf(buf: ring->name, fmt: "sdma%d", i);
1417 r = amdgpu_ring_init(adev, ring, max_dw: 1024, irq_src: &adev->sdma.trap_irq,
1418 irq_type: (i == 0) ? AMDGPU_SDMA_IRQ_INSTANCE0 :
1419 AMDGPU_SDMA_IRQ_INSTANCE1,
1420 hw_prio: AMDGPU_RING_PRIO_DEFAULT, NULL);
1421 if (r)
1422 return r;
1423 }
1424
1425 adev->sdma.supported_reset =
1426 amdgpu_get_soft_full_reset_mask(ring: &adev->sdma.instance[0].ring);
1427 switch (amdgpu_ip_version(adev, ip: SDMA0_HWIP, inst: 0)) {
1428 case IP_VERSION(5, 0, 0):
1429 case IP_VERSION(5, 0, 2):
1430 case IP_VERSION(5, 0, 5):
1431 if ((adev->sdma.instance[0].fw_version >= 35) &&
1432 !amdgpu_sriov_vf(adev) &&
1433 !adev->debug_disable_gpu_ring_reset)
1434 adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;
1435 break;
1436 default:
1437 break;
1438 }
1439
1440 /* Allocate memory for SDMA IP Dump buffer */
1441 ptr = kcalloc(adev->sdma.num_instances * reg_count, sizeof(uint32_t), GFP_KERNEL);
1442 if (ptr)
1443 adev->sdma.ip_dump = ptr;
1444 else
1445 DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n");
1446
1447 r = amdgpu_sdma_sysfs_reset_mask_init(adev);
1448 if (r)
1449 return r;
1450
1451 return r;
1452}
1453
1454static int sdma_v5_0_sw_fini(struct amdgpu_ip_block *ip_block)
1455{
1456 struct amdgpu_device *adev = ip_block->adev;
1457 int i;
1458
1459 for (i = 0; i < adev->sdma.num_instances; i++)
1460 amdgpu_ring_fini(ring: &adev->sdma.instance[i].ring);
1461
1462 amdgpu_sdma_sysfs_reset_mask_fini(adev);
1463 amdgpu_sdma_destroy_inst_ctx(adev, duplicate: false);
1464
1465 kfree(objp: adev->sdma.ip_dump);
1466
1467 return 0;
1468}
1469
1470static int sdma_v5_0_hw_init(struct amdgpu_ip_block *ip_block)
1471{
1472 int r;
1473 struct amdgpu_device *adev = ip_block->adev;
1474
1475 sdma_v5_0_init_golden_registers(adev);
1476
1477 r = sdma_v5_0_start(adev);
1478
1479 return r;
1480}
1481
1482static int sdma_v5_0_hw_fini(struct amdgpu_ip_block *ip_block)
1483{
1484 struct amdgpu_device *adev = ip_block->adev;
1485
1486 if (amdgpu_sriov_vf(adev))
1487 return 0;
1488
1489 sdma_v5_0_ctx_switch_enable(adev, enable: false);
1490 sdma_v5_0_enable(adev, enable: false);
1491
1492 return 0;
1493}
1494
1495static int sdma_v5_0_suspend(struct amdgpu_ip_block *ip_block)
1496{
1497 return sdma_v5_0_hw_fini(ip_block);
1498}
1499
1500static int sdma_v5_0_resume(struct amdgpu_ip_block *ip_block)
1501{
1502 return sdma_v5_0_hw_init(ip_block);
1503}
1504
1505static bool sdma_v5_0_is_idle(struct amdgpu_ip_block *ip_block)
1506{
1507 struct amdgpu_device *adev = ip_block->adev;
1508 u32 i;
1509
1510 for (i = 0; i < adev->sdma.num_instances; i++) {
1511 u32 tmp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
1512
1513 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1514 return false;
1515 }
1516
1517 return true;
1518}
1519
1520static int sdma_v5_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
1521{
1522 unsigned i;
1523 u32 sdma0, sdma1;
1524 struct amdgpu_device *adev = ip_block->adev;
1525
1526 for (i = 0; i < adev->usec_timeout; i++) {
1527 sdma0 = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));
1528 sdma1 = RREG32(sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));
1529
1530 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK)
1531 return 0;
1532 udelay(usec: 1);
1533 }
1534 return -ETIMEDOUT;
1535}
1536
1537static int sdma_v5_0_soft_reset(struct amdgpu_ip_block *ip_block)
1538{
1539 /* todo */
1540
1541 return 0;
1542}
1543
1544static int sdma_v5_0_reset_queue(struct amdgpu_ring *ring,
1545 unsigned int vmid,
1546 struct amdgpu_fence *timedout_fence)
1547{
1548 struct amdgpu_device *adev = ring->adev;
1549 int r;
1550
1551 if (ring->me >= adev->sdma.num_instances) {
1552 dev_err(adev->dev, "sdma instance not found\n");
1553 return -EINVAL;
1554 }
1555
1556 amdgpu_ring_reset_helper_begin(ring, guilty_fence: timedout_fence);
1557
1558 amdgpu_amdkfd_suspend(adev, suspend_proc: true);
1559 r = amdgpu_sdma_reset_engine(adev, instance_id: ring->me, caller_handles_kernel_queues: true);
1560 amdgpu_amdkfd_resume(adev, resume_proc: true);
1561 if (r)
1562 return r;
1563
1564 return amdgpu_ring_reset_helper_end(ring, guilty_fence: timedout_fence);
1565}
1566
1567static int sdma_v5_0_stop_queue(struct amdgpu_ring *ring)
1568{
1569 u32 f32_cntl, freeze, cntl, stat1_reg;
1570 struct amdgpu_device *adev = ring->adev;
1571 int i, j, r = 0;
1572
1573 if (amdgpu_sriov_vf(adev))
1574 return -EINVAL;
1575
1576 i = ring->me;
1577 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id: 0);
1578
1579 /* stop queue */
1580 sdma_v5_0_gfx_stop(adev, inst_mask: 1 << i);
1581
1582 /* engine stop SDMA1_F32_CNTL.HALT to 1 and SDMAx_FREEZE freeze bit to 1 */
1583 freeze = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_FREEZE));
1584 freeze = REG_SET_FIELD(freeze, SDMA0_FREEZE, FREEZE, 1);
1585 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_FREEZE), freeze);
1586
1587 for (j = 0; j < adev->usec_timeout; j++) {
1588 freeze = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_FREEZE));
1589 if (REG_GET_FIELD(freeze, SDMA0_FREEZE, FROZEN) & 1)
1590 break;
1591 udelay(usec: 1);
1592 }
1593
1594 /* check sdma copy engine all idle if frozen not received*/
1595 if (j == adev->usec_timeout) {
1596 stat1_reg = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_STATUS1_REG));
1597 if ((stat1_reg & 0x3FF) != 0x3FF) {
1598 DRM_ERROR("cannot soft reset as sdma not idle\n");
1599 r = -ETIMEDOUT;
1600 goto err0;
1601 }
1602 }
1603
1604 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
1605 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
1606 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
1607
1608 cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
1609 cntl = REG_SET_FIELD(cntl, SDMA0_CNTL, UTC_L1_ENABLE, 0);
1610 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), cntl);
1611err0:
1612 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id: 0);
1613 return r;
1614}
1615
1616static int sdma_v5_0_restore_queue(struct amdgpu_ring *ring)
1617{
1618 struct amdgpu_device *adev = ring->adev;
1619 u32 inst_id = ring->me;
1620 u32 freeze;
1621 int r;
1622
1623 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id: 0);
1624 /* unfreeze*/
1625 freeze = RREG32(sdma_v5_0_get_reg_offset(adev, inst_id, mmSDMA0_FREEZE));
1626 freeze = REG_SET_FIELD(freeze, SDMA0_FREEZE, FREEZE, 0);
1627 WREG32(sdma_v5_0_get_reg_offset(adev, inst_id, mmSDMA0_FREEZE), freeze);
1628
1629 r = sdma_v5_0_gfx_resume_instance(adev, i: inst_id, restore: true);
1630 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id: 0);
1631
1632 return r;
1633}
1634
1635static int sdma_v5_0_ring_preempt_ib(struct amdgpu_ring *ring)
1636{
1637 int i, r = 0;
1638 struct amdgpu_device *adev = ring->adev;
1639 u32 index = 0;
1640 u64 sdma_gfx_preempt;
1641
1642 amdgpu_sdma_get_index_from_ring(ring, index: &index);
1643 if (index == 0)
1644 sdma_gfx_preempt = mmSDMA0_GFX_PREEMPT;
1645 else
1646 sdma_gfx_preempt = mmSDMA1_GFX_PREEMPT;
1647
1648 /* assert preemption condition */
1649 amdgpu_ring_set_preempt_cond_exec(ring, cond_exec: false);
1650
1651 /* emit the trailing fence */
1652 ring->trail_seq += 1;
1653 amdgpu_ring_alloc(ring, ndw: 10);
1654 sdma_v5_0_ring_emit_fence(ring, addr: ring->trail_fence_gpu_addr,
1655 seq: ring->trail_seq, flags: 0);
1656 amdgpu_ring_commit(ring);
1657
1658 /* assert IB preemption */
1659 WREG32(sdma_gfx_preempt, 1);
1660
1661 /* poll the trailing fence */
1662 for (i = 0; i < adev->usec_timeout; i++) {
1663 if (ring->trail_seq ==
1664 le32_to_cpu(*(ring->trail_fence_cpu_addr)))
1665 break;
1666 udelay(usec: 1);
1667 }
1668
1669 if (i >= adev->usec_timeout) {
1670 r = -EINVAL;
1671 DRM_ERROR("ring %d failed to be preempted\n", ring->idx);
1672 }
1673
1674 /* deassert IB preemption */
1675 WREG32(sdma_gfx_preempt, 0);
1676
1677 /* deassert the preemption condition */
1678 amdgpu_ring_set_preempt_cond_exec(ring, cond_exec: true);
1679 return r;
1680}
1681
1682static int sdma_v5_0_set_trap_irq_state(struct amdgpu_device *adev,
1683 struct amdgpu_irq_src *source,
1684 unsigned type,
1685 enum amdgpu_interrupt_state state)
1686{
1687 u32 sdma_cntl;
1688
1689 if (!amdgpu_sriov_vf(adev)) {
1690 u32 reg_offset = (type == AMDGPU_SDMA_IRQ_INSTANCE0) ?
1691 sdma_v5_0_get_reg_offset(adev, instance: 0, mmSDMA0_CNTL) :
1692 sdma_v5_0_get_reg_offset(adev, instance: 1, mmSDMA0_CNTL);
1693
1694 sdma_cntl = RREG32(reg_offset);
1695 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1696 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1697 WREG32(reg_offset, sdma_cntl);
1698 }
1699
1700 return 0;
1701}
1702
1703static int sdma_v5_0_process_trap_irq(struct amdgpu_device *adev,
1704 struct amdgpu_irq_src *source,
1705 struct amdgpu_iv_entry *entry)
1706{
1707 uint32_t mes_queue_id = entry->src_data[0];
1708
1709 DRM_DEBUG("IH: SDMA trap\n");
1710
1711 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) {
1712 struct amdgpu_mes_queue *queue;
1713
1714 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK;
1715
1716 spin_lock(lock: &adev->mes.queue_id_lock);
1717 queue = idr_find(&adev->mes.queue_id_idr, id: mes_queue_id);
1718 if (queue) {
1719 DRM_DEBUG("process smda queue id = %d\n", mes_queue_id);
1720 amdgpu_fence_process(ring: queue->ring);
1721 }
1722 spin_unlock(lock: &adev->mes.queue_id_lock);
1723 return 0;
1724 }
1725
1726 switch (entry->client_id) {
1727 case SOC15_IH_CLIENTID_SDMA0:
1728 switch (entry->ring_id) {
1729 case 0:
1730 amdgpu_fence_process(ring: &adev->sdma.instance[0].ring);
1731 break;
1732 case 1:
1733 /* XXX compute */
1734 break;
1735 case 2:
1736 /* XXX compute */
1737 break;
1738 case 3:
1739 /* XXX page queue*/
1740 break;
1741 }
1742 break;
1743 case SOC15_IH_CLIENTID_SDMA1:
1744 switch (entry->ring_id) {
1745 case 0:
1746 amdgpu_fence_process(ring: &adev->sdma.instance[1].ring);
1747 break;
1748 case 1:
1749 /* XXX compute */
1750 break;
1751 case 2:
1752 /* XXX compute */
1753 break;
1754 case 3:
1755 /* XXX page queue*/
1756 break;
1757 }
1758 break;
1759 }
1760 return 0;
1761}
1762
1763static int sdma_v5_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1764 struct amdgpu_irq_src *source,
1765 struct amdgpu_iv_entry *entry)
1766{
1767 return 0;
1768}
1769
1770static void sdma_v5_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
1771 bool enable)
1772{
1773 uint32_t data, def;
1774 int i;
1775
1776 for (i = 0; i < adev->sdma.num_instances; i++) {
1777 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1778 /* Enable sdma clock gating */
1779 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1780 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1781 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1782 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1783 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1784 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1785 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1786 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1787 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1788 if (def != data)
1789 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1790 } else {
1791 /* Disable sdma clock gating */
1792 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1793 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1794 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1795 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1796 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1797 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1798 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1799 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1800 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1801 if (def != data)
1802 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1803 }
1804 }
1805}
1806
1807static void sdma_v5_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
1808 bool enable)
1809{
1810 uint32_t data, def;
1811 int i;
1812
1813 for (i = 0; i < adev->sdma.num_instances; i++) {
1814 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1815 /* Enable sdma mem light sleep */
1816 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1817 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1818 if (def != data)
1819 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1820
1821 } else {
1822 /* Disable sdma mem light sleep */
1823 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1824 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1825 if (def != data)
1826 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1827
1828 }
1829 }
1830}
1831
1832static int sdma_v5_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
1833 enum amd_clockgating_state state)
1834{
1835 struct amdgpu_device *adev = ip_block->adev;
1836
1837 if (amdgpu_sriov_vf(adev))
1838 return 0;
1839
1840 switch (amdgpu_ip_version(adev, ip: SDMA0_HWIP, inst: 0)) {
1841 case IP_VERSION(5, 0, 0):
1842 case IP_VERSION(5, 0, 2):
1843 case IP_VERSION(5, 0, 5):
1844 sdma_v5_0_update_medium_grain_clock_gating(adev,
1845 enable: state == AMD_CG_STATE_GATE);
1846 sdma_v5_0_update_medium_grain_light_sleep(adev,
1847 enable: state == AMD_CG_STATE_GATE);
1848 break;
1849 default:
1850 break;
1851 }
1852
1853 return 0;
1854}
1855
1856static int sdma_v5_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
1857 enum amd_powergating_state state)
1858{
1859 return 0;
1860}
1861
1862static void sdma_v5_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)
1863{
1864 struct amdgpu_device *adev = ip_block->adev;
1865 int data;
1866
1867 if (amdgpu_sriov_vf(adev))
1868 *flags = 0;
1869
1870 /* AMD_CG_SUPPORT_SDMA_MGCG */
1871 data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL));
1872 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK))
1873 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
1874
1875 /* AMD_CG_SUPPORT_SDMA_LS */
1876 data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL));
1877 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1878 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1879}
1880
1881static void sdma_v5_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p)
1882{
1883 struct amdgpu_device *adev = ip_block->adev;
1884 int i, j;
1885 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_5_0);
1886 uint32_t instance_offset;
1887
1888 if (!adev->sdma.ip_dump)
1889 return;
1890
1891 drm_printf(p, f: "num_instances:%d\n", adev->sdma.num_instances);
1892 for (i = 0; i < adev->sdma.num_instances; i++) {
1893 instance_offset = i * reg_count;
1894 drm_printf(p, f: "\nInstance:%d\n", i);
1895
1896 for (j = 0; j < reg_count; j++)
1897 drm_printf(p, f: "%-50s \t 0x%08x\n", sdma_reg_list_5_0[j].reg_name,
1898 adev->sdma.ip_dump[instance_offset + j]);
1899 }
1900}
1901
1902static void sdma_v5_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
1903{
1904 struct amdgpu_device *adev = ip_block->adev;
1905 int i, j;
1906 uint32_t instance_offset;
1907 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_5_0);
1908
1909 if (!adev->sdma.ip_dump)
1910 return;
1911
1912 amdgpu_gfx_off_ctrl(adev, enable: false);
1913 for (i = 0; i < adev->sdma.num_instances; i++) {
1914 instance_offset = i * reg_count;
1915 for (j = 0; j < reg_count; j++)
1916 adev->sdma.ip_dump[instance_offset + j] =
1917 RREG32(sdma_v5_0_get_reg_offset(adev, i,
1918 sdma_reg_list_5_0[j].reg_offset));
1919 }
1920 amdgpu_gfx_off_ctrl(adev, enable: true);
1921}
1922
1923static const struct amd_ip_funcs sdma_v5_0_ip_funcs = {
1924 .name = "sdma_v5_0",
1925 .early_init = sdma_v5_0_early_init,
1926 .sw_init = sdma_v5_0_sw_init,
1927 .sw_fini = sdma_v5_0_sw_fini,
1928 .hw_init = sdma_v5_0_hw_init,
1929 .hw_fini = sdma_v5_0_hw_fini,
1930 .suspend = sdma_v5_0_suspend,
1931 .resume = sdma_v5_0_resume,
1932 .is_idle = sdma_v5_0_is_idle,
1933 .wait_for_idle = sdma_v5_0_wait_for_idle,
1934 .soft_reset = sdma_v5_0_soft_reset,
1935 .set_clockgating_state = sdma_v5_0_set_clockgating_state,
1936 .set_powergating_state = sdma_v5_0_set_powergating_state,
1937 .get_clockgating_state = sdma_v5_0_get_clockgating_state,
1938 .dump_ip_state = sdma_v5_0_dump_ip_state,
1939 .print_ip_state = sdma_v5_0_print_ip_state,
1940};
1941
1942static const struct amdgpu_ring_funcs sdma_v5_0_ring_funcs = {
1943 .type = AMDGPU_RING_TYPE_SDMA,
1944 .align_mask = 0xf,
1945 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1946 .support_64bit_ptrs = true,
1947 .secure_submission_supported = true,
1948 .get_rptr = sdma_v5_0_ring_get_rptr,
1949 .get_wptr = sdma_v5_0_ring_get_wptr,
1950 .set_wptr = sdma_v5_0_ring_set_wptr,
1951 .emit_frame_size =
1952 5 + /* sdma_v5_0_ring_init_cond_exec */
1953 6 + /* sdma_v5_0_ring_emit_hdp_flush */
1954 3 + /* hdp_invalidate */
1955 6 + /* sdma_v5_0_ring_emit_pipeline_sync */
1956 /* sdma_v5_0_ring_emit_vm_flush */
1957 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1958 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 * 2 +
1959 10 + 10 + 10, /* sdma_v5_0_ring_emit_fence x3 for user fence, vm fence */
1960 .emit_ib_size = 5 + 7 + 6, /* sdma_v5_0_ring_emit_ib */
1961 .emit_ib = sdma_v5_0_ring_emit_ib,
1962 .emit_mem_sync = sdma_v5_0_ring_emit_mem_sync,
1963 .emit_fence = sdma_v5_0_ring_emit_fence,
1964 .emit_pipeline_sync = sdma_v5_0_ring_emit_pipeline_sync,
1965 .emit_vm_flush = sdma_v5_0_ring_emit_vm_flush,
1966 .emit_hdp_flush = sdma_v5_0_ring_emit_hdp_flush,
1967 .test_ring = sdma_v5_0_ring_test_ring,
1968 .test_ib = sdma_v5_0_ring_test_ib,
1969 .insert_nop = sdma_v5_0_ring_insert_nop,
1970 .pad_ib = sdma_v5_0_ring_pad_ib,
1971 .emit_wreg = sdma_v5_0_ring_emit_wreg,
1972 .emit_reg_wait = sdma_v5_0_ring_emit_reg_wait,
1973 .emit_reg_write_reg_wait = sdma_v5_0_ring_emit_reg_write_reg_wait,
1974 .init_cond_exec = sdma_v5_0_ring_init_cond_exec,
1975 .preempt_ib = sdma_v5_0_ring_preempt_ib,
1976 .reset = sdma_v5_0_reset_queue,
1977};
1978
1979static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev)
1980{
1981 int i;
1982
1983 for (i = 0; i < adev->sdma.num_instances; i++) {
1984 adev->sdma.instance[i].ring.funcs = &sdma_v5_0_ring_funcs;
1985 adev->sdma.instance[i].ring.me = i;
1986 }
1987}
1988
1989static const struct amdgpu_irq_src_funcs sdma_v5_0_trap_irq_funcs = {
1990 .set = sdma_v5_0_set_trap_irq_state,
1991 .process = sdma_v5_0_process_trap_irq,
1992};
1993
1994static const struct amdgpu_irq_src_funcs sdma_v5_0_illegal_inst_irq_funcs = {
1995 .process = sdma_v5_0_process_illegal_inst_irq,
1996};
1997
1998static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev)
1999{
2000 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
2001 adev->sdma.num_instances;
2002 adev->sdma.trap_irq.funcs = &sdma_v5_0_trap_irq_funcs;
2003 adev->sdma.illegal_inst_irq.funcs = &sdma_v5_0_illegal_inst_irq_funcs;
2004}
2005
2006/**
2007 * sdma_v5_0_emit_copy_buffer - copy buffer using the sDMA engine
2008 *
2009 * @ib: indirect buffer to copy to
2010 * @src_offset: src GPU address
2011 * @dst_offset: dst GPU address
2012 * @byte_count: number of bytes to xfer
2013 * @copy_flags: copy flags for the buffers
2014 *
2015 * Copy GPU buffers using the DMA engine (NAVI10).
2016 * Used by the amdgpu ttm implementation to move pages if
2017 * registered as the asic copy callback.
2018 */
2019static void sdma_v5_0_emit_copy_buffer(struct amdgpu_ib *ib,
2020 uint64_t src_offset,
2021 uint64_t dst_offset,
2022 uint32_t byte_count,
2023 uint32_t copy_flags)
2024{
2025 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
2026 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
2027 SDMA_PKT_COPY_LINEAR_HEADER_TMZ((copy_flags & AMDGPU_COPY_FLAGS_TMZ) ? 1 : 0);
2028 ib->ptr[ib->length_dw++] = byte_count - 1;
2029 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
2030 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
2031 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
2032 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
2033 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
2034}
2035
2036/**
2037 * sdma_v5_0_emit_fill_buffer - fill buffer using the sDMA engine
2038 *
2039 * @ib: indirect buffer to fill
2040 * @src_data: value to write to buffer
2041 * @dst_offset: dst GPU address
2042 * @byte_count: number of bytes to xfer
2043 *
2044 * Fill GPU buffers using the DMA engine (NAVI10).
2045 */
2046static void sdma_v5_0_emit_fill_buffer(struct amdgpu_ib *ib,
2047 uint32_t src_data,
2048 uint64_t dst_offset,
2049 uint32_t byte_count)
2050{
2051 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
2052 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
2053 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
2054 ib->ptr[ib->length_dw++] = src_data;
2055 ib->ptr[ib->length_dw++] = byte_count - 1;
2056}
2057
2058static const struct amdgpu_buffer_funcs sdma_v5_0_buffer_funcs = {
2059 .copy_max_bytes = 0x400000,
2060 .copy_num_dw = 7,
2061 .emit_copy_buffer = sdma_v5_0_emit_copy_buffer,
2062
2063 .fill_max_bytes = 0x400000,
2064 .fill_num_dw = 5,
2065 .emit_fill_buffer = sdma_v5_0_emit_fill_buffer,
2066};
2067
2068static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev)
2069{
2070 if (adev->mman.buffer_funcs == NULL) {
2071 adev->mman.buffer_funcs = &sdma_v5_0_buffer_funcs;
2072 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
2073 }
2074}
2075
2076static const struct amdgpu_vm_pte_funcs sdma_v5_0_vm_pte_funcs = {
2077 .copy_pte_num_dw = 7,
2078 .copy_pte = sdma_v5_0_vm_copy_pte,
2079 .write_pte = sdma_v5_0_vm_write_pte,
2080 .set_pte_pde = sdma_v5_0_vm_set_pte_pde,
2081};
2082
2083static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev)
2084{
2085 unsigned i;
2086
2087 if (adev->vm_manager.vm_pte_funcs == NULL) {
2088 adev->vm_manager.vm_pte_funcs = &sdma_v5_0_vm_pte_funcs;
2089 for (i = 0; i < adev->sdma.num_instances; i++) {
2090 adev->vm_manager.vm_pte_scheds[i] =
2091 &adev->sdma.instance[i].ring.sched;
2092 }
2093 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
2094 }
2095}
2096
2097const struct amdgpu_ip_block_version sdma_v5_0_ip_block = {
2098 .type = AMD_IP_BLOCK_TYPE_SDMA,
2099 .major = 5,
2100 .minor = 0,
2101 .rev = 0,
2102 .funcs = &sdma_v5_0_ip_funcs,
2103};
2104

source code of linux/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c