1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include <linux/slab.h>
25#include <linux/module.h>
26#include <linux/pci.h>
27
28#include <drm/amdgpu_drm.h>
29
30#include "amdgpu.h"
31#include "amdgpu_atombios.h"
32#include "amdgpu_ih.h"
33#include "amdgpu_uvd.h"
34#include "amdgpu_vce.h"
35#include "amdgpu_ucode.h"
36#include "amdgpu_psp.h"
37#include "atom.h"
38#include "amd_pcie.h"
39
40#include "gc/gc_10_1_0_offset.h"
41#include "gc/gc_10_1_0_sh_mask.h"
42#include "mp/mp_11_0_offset.h"
43
44#include "soc15.h"
45#include "soc15_common.h"
46#include "gmc_v10_0.h"
47#include "gfxhub_v2_0.h"
48#include "mmhub_v2_0.h"
49#include "nbio_v2_3.h"
50#include "nbio_v7_2.h"
51#include "hdp_v5_0.h"
52#include "nv.h"
53#include "navi10_ih.h"
54#include "gfx_v10_0.h"
55#include "sdma_v5_0.h"
56#include "sdma_v5_2.h"
57#include "vcn_v2_0.h"
58#include "jpeg_v2_0.h"
59#include "vcn_v3_0.h"
60#include "jpeg_v3_0.h"
61#include "amdgpu_vkms.h"
62#include "mxgpu_nv.h"
63#include "smuio_v11_0.h"
64#include "smuio_v11_0_6.h"
65
66static const struct amd_ip_funcs nv_common_ip_funcs;
67
68/* Navi */
69static const struct amdgpu_video_codec_info nv_video_codecs_encode_array[] = {
70 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},
71 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 0)},
72};
73
74static const struct amdgpu_video_codecs nv_video_codecs_encode = {
75 .codec_count = ARRAY_SIZE(nv_video_codecs_encode_array),
76 .codec_array = nv_video_codecs_encode_array,
77};
78
79/* Navi1x */
80static const struct amdgpu_video_codec_info nv_video_codecs_decode_array[] = {
81 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 1920, 1088, 3)},
82 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 1920, 1088, 5)},
83 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
84 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 1920, 1088, 4)},
85 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
86 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 8192, 8192, 0)},
87 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
88};
89
90static const struct amdgpu_video_codecs nv_video_codecs_decode = {
91 .codec_count = ARRAY_SIZE(nv_video_codecs_decode_array),
92 .codec_array = nv_video_codecs_decode_array,
93};
94
95/* Sienna Cichlid */
96static const struct amdgpu_video_codec_info sc_video_codecs_encode_array[] = {
97 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},
98 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)},
99};
100
101static const struct amdgpu_video_codecs sc_video_codecs_encode = {
102 .codec_count = ARRAY_SIZE(sc_video_codecs_encode_array),
103 .codec_array = sc_video_codecs_encode_array,
104};
105
106static const struct amdgpu_video_codec_info sc_video_codecs_decode_array_vcn0[] = {
107 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 1920, 1088, 3)},
108 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 1920, 1088, 5)},
109 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
110 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 1920, 1088, 4)},
111 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
112 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},
113 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
114 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
115};
116
117static const struct amdgpu_video_codec_info sc_video_codecs_decode_array_vcn1[] = {
118 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 1920, 1088, 3)},
119 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 1920, 1088, 5)},
120 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
121 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 1920, 1088, 4)},
122 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
123 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},
124 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
125};
126
127static const struct amdgpu_video_codecs sc_video_codecs_decode_vcn0 = {
128 .codec_count = ARRAY_SIZE(sc_video_codecs_decode_array_vcn0),
129 .codec_array = sc_video_codecs_decode_array_vcn0,
130};
131
132static const struct amdgpu_video_codecs sc_video_codecs_decode_vcn1 = {
133 .codec_count = ARRAY_SIZE(sc_video_codecs_decode_array_vcn1),
134 .codec_array = sc_video_codecs_decode_array_vcn1,
135};
136
137/* SRIOV Sienna Cichlid, not const since data is controlled by host */
138static struct amdgpu_video_codec_info sriov_sc_video_codecs_encode_array[] = {
139 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},
140 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)},
141};
142
143static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array_vcn0[] = {
144 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 1920, 1088, 3)},
145 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 1920, 1088, 5)},
146 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
147 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 1920, 1088, 4)},
148 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
149 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},
150 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
151 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
152};
153
154static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array_vcn1[] = {
155 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 1920, 1088, 3)},
156 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 1920, 1088, 5)},
157 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
158 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 1920, 1088, 4)},
159 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
160 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},
161 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
162};
163
164static struct amdgpu_video_codecs sriov_sc_video_codecs_encode = {
165 .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_encode_array),
166 .codec_array = sriov_sc_video_codecs_encode_array,
167};
168
169static struct amdgpu_video_codecs sriov_sc_video_codecs_decode_vcn0 = {
170 .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn0),
171 .codec_array = sriov_sc_video_codecs_decode_array_vcn0,
172};
173
174static struct amdgpu_video_codecs sriov_sc_video_codecs_decode_vcn1 = {
175 .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn1),
176 .codec_array = sriov_sc_video_codecs_decode_array_vcn1,
177};
178
179/* Beige Goby*/
180static const struct amdgpu_video_codec_info bg_video_codecs_decode_array[] = {
181 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
182 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
183 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
184};
185
186static const struct amdgpu_video_codecs bg_video_codecs_decode = {
187 .codec_count = ARRAY_SIZE(bg_video_codecs_decode_array),
188 .codec_array = bg_video_codecs_decode_array,
189};
190
191static const struct amdgpu_video_codecs bg_video_codecs_encode = {
192 .codec_count = 0,
193 .codec_array = NULL,
194};
195
196/* Yellow Carp*/
197static const struct amdgpu_video_codec_info yc_video_codecs_decode_array[] = {
198 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
199 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
200 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
201 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},
202 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
203};
204
205static const struct amdgpu_video_codecs yc_video_codecs_decode = {
206 .codec_count = ARRAY_SIZE(yc_video_codecs_decode_array),
207 .codec_array = yc_video_codecs_decode_array,
208};
209
210static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode,
211 const struct amdgpu_video_codecs **codecs)
212{
213 if (adev->vcn.num_vcn_inst == hweight8(adev->vcn.harvest_config))
214 return -EINVAL;
215
216 switch (amdgpu_ip_version(adev, ip: UVD_HWIP, inst: 0)) {
217 case IP_VERSION(3, 0, 0):
218 case IP_VERSION(3, 0, 64):
219 case IP_VERSION(3, 0, 192):
220 if (amdgpu_sriov_vf(adev)) {
221 if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) {
222 if (encode)
223 *codecs = &sriov_sc_video_codecs_encode;
224 else
225 *codecs = &sriov_sc_video_codecs_decode_vcn1;
226 } else {
227 if (encode)
228 *codecs = &sriov_sc_video_codecs_encode;
229 else
230 *codecs = &sriov_sc_video_codecs_decode_vcn0;
231 }
232 } else {
233 if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) {
234 if (encode)
235 *codecs = &sc_video_codecs_encode;
236 else
237 *codecs = &sc_video_codecs_decode_vcn1;
238 } else {
239 if (encode)
240 *codecs = &sc_video_codecs_encode;
241 else
242 *codecs = &sc_video_codecs_decode_vcn0;
243 }
244 }
245 return 0;
246 case IP_VERSION(3, 0, 16):
247 case IP_VERSION(3, 0, 2):
248 if (encode)
249 *codecs = &sc_video_codecs_encode;
250 else
251 *codecs = &sc_video_codecs_decode_vcn0;
252 return 0;
253 case IP_VERSION(3, 1, 1):
254 case IP_VERSION(3, 1, 2):
255 if (encode)
256 *codecs = &sc_video_codecs_encode;
257 else
258 *codecs = &yc_video_codecs_decode;
259 return 0;
260 case IP_VERSION(3, 0, 33):
261 if (encode)
262 *codecs = &bg_video_codecs_encode;
263 else
264 *codecs = &bg_video_codecs_decode;
265 return 0;
266 case IP_VERSION(2, 0, 0):
267 case IP_VERSION(2, 0, 2):
268 if (encode)
269 *codecs = &nv_video_codecs_encode;
270 else
271 *codecs = &nv_video_codecs_decode;
272 return 0;
273 default:
274 return -EINVAL;
275 }
276}
277
278static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg)
279{
280 unsigned long flags, address, data;
281 u32 r;
282
283 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
284 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
285
286 spin_lock_irqsave(&adev->didt_idx_lock, flags);
287 WREG32(address, (reg));
288 r = RREG32(data);
289 spin_unlock_irqrestore(lock: &adev->didt_idx_lock, flags);
290 return r;
291}
292
293static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
294{
295 unsigned long flags, address, data;
296
297 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
298 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
299
300 spin_lock_irqsave(&adev->didt_idx_lock, flags);
301 WREG32(address, (reg));
302 WREG32(data, (v));
303 spin_unlock_irqrestore(lock: &adev->didt_idx_lock, flags);
304}
305
306static u32 nv_get_config_memsize(struct amdgpu_device *adev)
307{
308 return adev->nbio.funcs->get_memsize(adev);
309}
310
311static u32 nv_get_xclk(struct amdgpu_device *adev)
312{
313 return adev->clock.spll.reference_freq;
314}
315
316
317void nv_grbm_select(struct amdgpu_device *adev,
318 u32 me, u32 pipe, u32 queue, u32 vmid)
319{
320 u32 grbm_gfx_cntl = 0;
321 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
322 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
323 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
324 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
325
326 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl);
327}
328
329static bool nv_read_disabled_bios(struct amdgpu_device *adev)
330{
331 /* todo */
332 return false;
333}
334
335static struct soc15_allowed_register_entry nv_allowed_read_registers[] = {
336 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
337 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
338 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
339 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
340 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
341 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
342 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
343 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
344 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
345 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
346 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
347 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
348 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
349 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
350 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
351 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)},
352 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
353 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
354 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
355};
356
357static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
358 u32 sh_num, u32 reg_offset)
359{
360 uint32_t val;
361
362 mutex_lock(&adev->grbm_idx_mutex);
363 if (se_num != 0xffffffff || sh_num != 0xffffffff)
364 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0);
365
366 val = RREG32(reg_offset);
367
368 if (se_num != 0xffffffff || sh_num != 0xffffffff)
369 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
370 mutex_unlock(lock: &adev->grbm_idx_mutex);
371 return val;
372}
373
374static uint32_t nv_get_register_value(struct amdgpu_device *adev,
375 bool indexed, u32 se_num,
376 u32 sh_num, u32 reg_offset)
377{
378 if (indexed) {
379 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset);
380 } else {
381 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
382 return adev->gfx.config.gb_addr_config;
383 return RREG32(reg_offset);
384 }
385}
386
387static int nv_read_register(struct amdgpu_device *adev, u32 se_num,
388 u32 sh_num, u32 reg_offset, u32 *value)
389{
390 uint32_t i;
391 struct soc15_allowed_register_entry *en;
392
393 *value = 0;
394 for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) {
395 en = &nv_allowed_read_registers[i];
396 if (!adev->reg_offset[en->hwip][en->inst])
397 continue;
398 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
399 + en->reg_offset))
400 continue;
401
402 *value = nv_get_register_value(adev,
403 indexed: nv_allowed_read_registers[i].grbm_indexed,
404 se_num, sh_num, reg_offset);
405 return 0;
406 }
407 return -EINVAL;
408}
409
410static int nv_asic_mode2_reset(struct amdgpu_device *adev)
411{
412 u32 i;
413 int ret = 0;
414
415 amdgpu_atombios_scratch_regs_engine_hung(adev, hung: true);
416
417 /* disable BM */
418 pci_clear_master(dev: adev->pdev);
419
420 amdgpu_device_cache_pci_state(pdev: adev->pdev);
421
422 ret = amdgpu_dpm_mode2_reset(adev);
423 if (ret)
424 dev_err(adev->dev, "GPU mode2 reset failed\n");
425
426 amdgpu_device_load_pci_state(pdev: adev->pdev);
427
428 /* wait for asic to come out of reset */
429 for (i = 0; i < adev->usec_timeout; i++) {
430 u32 memsize = adev->nbio.funcs->get_memsize(adev);
431
432 if (memsize != 0xffffffff)
433 break;
434 udelay(usec: 1);
435 }
436
437 amdgpu_atombios_scratch_regs_engine_hung(adev, hung: false);
438
439 return ret;
440}
441
442static enum amd_reset_method
443nv_asic_reset_method(struct amdgpu_device *adev)
444{
445 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
446 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
447 amdgpu_reset_method == AMD_RESET_METHOD_BACO ||
448 amdgpu_reset_method == AMD_RESET_METHOD_PCI)
449 return amdgpu_reset_method;
450
451 if (amdgpu_reset_method != -1)
452 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
453 amdgpu_reset_method);
454
455 switch (amdgpu_ip_version(adev, ip: MP1_HWIP, inst: 0)) {
456 case IP_VERSION(11, 5, 0):
457 case IP_VERSION(11, 5, 2):
458 case IP_VERSION(13, 0, 1):
459 case IP_VERSION(13, 0, 3):
460 case IP_VERSION(13, 0, 5):
461 case IP_VERSION(13, 0, 8):
462 return AMD_RESET_METHOD_MODE2;
463 case IP_VERSION(11, 0, 7):
464 case IP_VERSION(11, 0, 11):
465 case IP_VERSION(11, 0, 12):
466 case IP_VERSION(11, 0, 13):
467 return AMD_RESET_METHOD_MODE1;
468 default:
469 if (amdgpu_dpm_is_baco_supported(adev))
470 return AMD_RESET_METHOD_BACO;
471 else
472 return AMD_RESET_METHOD_MODE1;
473 }
474}
475
476static int nv_asic_reset(struct amdgpu_device *adev)
477{
478 int ret = 0;
479
480 switch (nv_asic_reset_method(adev)) {
481 case AMD_RESET_METHOD_PCI:
482 dev_info(adev->dev, "PCI reset\n");
483 ret = amdgpu_device_pci_reset(adev);
484 break;
485 case AMD_RESET_METHOD_BACO:
486 dev_info(adev->dev, "BACO reset\n");
487 ret = amdgpu_dpm_baco_reset(adev);
488 break;
489 case AMD_RESET_METHOD_MODE2:
490 dev_info(adev->dev, "MODE2 reset\n");
491 ret = nv_asic_mode2_reset(adev);
492 break;
493 default:
494 dev_info(adev->dev, "MODE1 reset\n");
495 ret = amdgpu_device_mode1_reset(adev);
496 break;
497 }
498
499 return ret;
500}
501
502static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
503{
504 /* todo */
505 return 0;
506}
507
508static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
509{
510 /* todo */
511 return 0;
512}
513
514static void nv_program_aspm(struct amdgpu_device *adev)
515{
516 if (!amdgpu_device_should_use_aspm(adev))
517 return;
518
519 if (adev->nbio.funcs->program_aspm)
520 adev->nbio.funcs->program_aspm(adev);
521
522}
523
524const struct amdgpu_ip_block_version nv_common_ip_block = {
525 .type = AMD_IP_BLOCK_TYPE_COMMON,
526 .major = 1,
527 .minor = 0,
528 .rev = 0,
529 .funcs = &nv_common_ip_funcs,
530};
531
532void nv_set_virt_ops(struct amdgpu_device *adev)
533{
534 adev->virt.ops = &xgpu_nv_virt_ops;
535}
536
537static bool nv_need_full_reset(struct amdgpu_device *adev)
538{
539 return true;
540}
541
542static bool nv_need_reset_on_init(struct amdgpu_device *adev)
543{
544 u32 sol_reg;
545
546 if (adev->flags & AMD_IS_APU)
547 return false;
548
549 /* Check sOS sign of life register to confirm sys driver and sOS
550 * are already been loaded.
551 */
552 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
553 if (sol_reg)
554 return true;
555
556 return false;
557}
558
559static void nv_init_doorbell_index(struct amdgpu_device *adev)
560{
561 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ;
562 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0;
563 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1;
564 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2;
565 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3;
566 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4;
567 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5;
568 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6;
569 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7;
570 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START;
571 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END;
572 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0;
573 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1;
574 adev->doorbell_index.gfx_userqueue_start =
575 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START;
576 adev->doorbell_index.gfx_userqueue_end =
577 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END;
578 adev->doorbell_index.mes_ring0 = AMDGPU_NAVI10_DOORBELL_MES_RING0;
579 adev->doorbell_index.mes_ring1 = AMDGPU_NAVI10_DOORBELL_MES_RING1;
580 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0;
581 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1;
582 adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2;
583 adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3;
584 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH;
585 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1;
586 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3;
587 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5;
588 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7;
589 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP;
590 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP;
591
592 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1;
593 adev->doorbell_index.sdma_doorbell_range = 20;
594}
595
596static void nv_pre_asic_init(struct amdgpu_device *adev)
597{
598}
599
600static int nv_update_umd_stable_pstate(struct amdgpu_device *adev,
601 bool enter)
602{
603 if (enter)
604 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id: 0);
605 else
606 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id: 0);
607
608 if (adev->gfx.funcs->update_perfmon_mgcg)
609 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter);
610
611 if (adev->nbio.funcs->enable_aspm &&
612 amdgpu_device_should_use_aspm(adev))
613 adev->nbio.funcs->enable_aspm(adev, !enter);
614
615 return 0;
616}
617
618static const struct amdgpu_asic_funcs nv_asic_funcs = {
619 .read_disabled_bios = &nv_read_disabled_bios,
620 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom,
621 .read_register = &nv_read_register,
622 .reset = &nv_asic_reset,
623 .reset_method = &nv_asic_reset_method,
624 .get_xclk = &nv_get_xclk,
625 .set_uvd_clocks = &nv_set_uvd_clocks,
626 .set_vce_clocks = &nv_set_vce_clocks,
627 .get_config_memsize = &nv_get_config_memsize,
628 .init_doorbell_index = &nv_init_doorbell_index,
629 .need_full_reset = &nv_need_full_reset,
630 .need_reset_on_init = &nv_need_reset_on_init,
631 .get_pcie_replay_count = &amdgpu_nbio_get_pcie_replay_count,
632 .supports_baco = &amdgpu_dpm_is_baco_supported,
633 .pre_asic_init = &nv_pre_asic_init,
634 .update_umd_stable_pstate = &nv_update_umd_stable_pstate,
635 .query_video_codecs = &nv_query_video_codecs,
636};
637
638static int nv_common_early_init(struct amdgpu_ip_block *ip_block)
639{
640 struct amdgpu_device *adev = ip_block->adev;
641
642 adev->nbio.funcs->set_reg_remap(adev);
643 adev->smc_rreg = NULL;
644 adev->smc_wreg = NULL;
645 adev->pcie_rreg = &amdgpu_device_indirect_rreg;
646 adev->pcie_wreg = &amdgpu_device_indirect_wreg;
647 adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64;
648 adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64;
649 adev->pciep_rreg = amdgpu_device_pcie_port_rreg;
650 adev->pciep_wreg = amdgpu_device_pcie_port_wreg;
651
652 /* TODO: will add them during VCN v2 implementation */
653 adev->uvd_ctx_rreg = NULL;
654 adev->uvd_ctx_wreg = NULL;
655
656 adev->didt_rreg = &nv_didt_rreg;
657 adev->didt_wreg = &nv_didt_wreg;
658
659 adev->asic_funcs = &nv_asic_funcs;
660
661 adev->rev_id = amdgpu_device_get_rev_id(adev);
662 adev->external_rev_id = 0xff;
663 /* TODO: split the GC and PG flags based on the relevant IP version for which
664 * they are relevant.
665 */
666 switch (amdgpu_ip_version(adev, ip: GC_HWIP, inst: 0)) {
667 case IP_VERSION(10, 1, 10):
668 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
669 AMD_CG_SUPPORT_GFX_CGCG |
670 AMD_CG_SUPPORT_IH_CG |
671 AMD_CG_SUPPORT_HDP_MGCG |
672 AMD_CG_SUPPORT_HDP_LS |
673 AMD_CG_SUPPORT_SDMA_MGCG |
674 AMD_CG_SUPPORT_SDMA_LS |
675 AMD_CG_SUPPORT_MC_MGCG |
676 AMD_CG_SUPPORT_MC_LS |
677 AMD_CG_SUPPORT_ATHUB_MGCG |
678 AMD_CG_SUPPORT_ATHUB_LS |
679 AMD_CG_SUPPORT_VCN_MGCG |
680 AMD_CG_SUPPORT_JPEG_MGCG |
681 AMD_CG_SUPPORT_BIF_MGCG |
682 AMD_CG_SUPPORT_BIF_LS;
683 adev->pg_flags = AMD_PG_SUPPORT_VCN |
684 AMD_PG_SUPPORT_VCN_DPG |
685 AMD_PG_SUPPORT_JPEG |
686 AMD_PG_SUPPORT_ATHUB;
687 adev->external_rev_id = adev->rev_id + 0x1;
688 break;
689 case IP_VERSION(10, 1, 1):
690 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
691 AMD_CG_SUPPORT_GFX_CGCG |
692 AMD_CG_SUPPORT_IH_CG |
693 AMD_CG_SUPPORT_HDP_MGCG |
694 AMD_CG_SUPPORT_HDP_LS |
695 AMD_CG_SUPPORT_SDMA_MGCG |
696 AMD_CG_SUPPORT_SDMA_LS |
697 AMD_CG_SUPPORT_MC_MGCG |
698 AMD_CG_SUPPORT_MC_LS |
699 AMD_CG_SUPPORT_ATHUB_MGCG |
700 AMD_CG_SUPPORT_ATHUB_LS |
701 AMD_CG_SUPPORT_VCN_MGCG |
702 AMD_CG_SUPPORT_JPEG_MGCG |
703 AMD_CG_SUPPORT_BIF_MGCG |
704 AMD_CG_SUPPORT_BIF_LS;
705 adev->pg_flags = AMD_PG_SUPPORT_VCN |
706 AMD_PG_SUPPORT_JPEG |
707 AMD_PG_SUPPORT_VCN_DPG;
708 adev->external_rev_id = adev->rev_id + 20;
709 break;
710 case IP_VERSION(10, 1, 2):
711 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
712 AMD_CG_SUPPORT_GFX_MGLS |
713 AMD_CG_SUPPORT_GFX_CGCG |
714 AMD_CG_SUPPORT_GFX_CP_LS |
715 AMD_CG_SUPPORT_GFX_RLC_LS |
716 AMD_CG_SUPPORT_IH_CG |
717 AMD_CG_SUPPORT_HDP_MGCG |
718 AMD_CG_SUPPORT_HDP_LS |
719 AMD_CG_SUPPORT_SDMA_MGCG |
720 AMD_CG_SUPPORT_SDMA_LS |
721 AMD_CG_SUPPORT_MC_MGCG |
722 AMD_CG_SUPPORT_MC_LS |
723 AMD_CG_SUPPORT_ATHUB_MGCG |
724 AMD_CG_SUPPORT_ATHUB_LS |
725 AMD_CG_SUPPORT_VCN_MGCG |
726 AMD_CG_SUPPORT_JPEG_MGCG;
727 adev->pg_flags = AMD_PG_SUPPORT_VCN |
728 AMD_PG_SUPPORT_VCN_DPG |
729 AMD_PG_SUPPORT_JPEG |
730 AMD_PG_SUPPORT_ATHUB;
731 /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0,
732 * as a consequence, the rev_id and external_rev_id are wrong.
733 * workaround it by hardcoding rev_id to 0 (default value).
734 */
735 if (amdgpu_sriov_vf(adev))
736 adev->rev_id = 0;
737 adev->external_rev_id = adev->rev_id + 0xa;
738 break;
739 case IP_VERSION(10, 3, 0):
740 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
741 AMD_CG_SUPPORT_GFX_CGCG |
742 AMD_CG_SUPPORT_GFX_CGLS |
743 AMD_CG_SUPPORT_GFX_3D_CGCG |
744 AMD_CG_SUPPORT_MC_MGCG |
745 AMD_CG_SUPPORT_VCN_MGCG |
746 AMD_CG_SUPPORT_JPEG_MGCG |
747 AMD_CG_SUPPORT_HDP_MGCG |
748 AMD_CG_SUPPORT_HDP_LS |
749 AMD_CG_SUPPORT_IH_CG |
750 AMD_CG_SUPPORT_MC_LS;
751 adev->pg_flags = AMD_PG_SUPPORT_VCN |
752 AMD_PG_SUPPORT_VCN_DPG |
753 AMD_PG_SUPPORT_JPEG |
754 AMD_PG_SUPPORT_ATHUB |
755 AMD_PG_SUPPORT_MMHUB;
756 if (amdgpu_sriov_vf(adev)) {
757 /* hypervisor control CG and PG enablement */
758 adev->cg_flags = 0;
759 adev->pg_flags = 0;
760 }
761 adev->external_rev_id = adev->rev_id + 0x28;
762 break;
763 case IP_VERSION(10, 3, 2):
764 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
765 AMD_CG_SUPPORT_GFX_CGCG |
766 AMD_CG_SUPPORT_GFX_CGLS |
767 AMD_CG_SUPPORT_GFX_3D_CGCG |
768 AMD_CG_SUPPORT_VCN_MGCG |
769 AMD_CG_SUPPORT_JPEG_MGCG |
770 AMD_CG_SUPPORT_MC_MGCG |
771 AMD_CG_SUPPORT_MC_LS |
772 AMD_CG_SUPPORT_HDP_MGCG |
773 AMD_CG_SUPPORT_HDP_LS |
774 AMD_CG_SUPPORT_IH_CG;
775 adev->pg_flags = AMD_PG_SUPPORT_VCN |
776 AMD_PG_SUPPORT_VCN_DPG |
777 AMD_PG_SUPPORT_JPEG |
778 AMD_PG_SUPPORT_ATHUB |
779 AMD_PG_SUPPORT_MMHUB;
780 adev->external_rev_id = adev->rev_id + 0x32;
781 break;
782 case IP_VERSION(10, 3, 1):
783 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
784 AMD_CG_SUPPORT_GFX_MGLS |
785 AMD_CG_SUPPORT_GFX_CP_LS |
786 AMD_CG_SUPPORT_GFX_RLC_LS |
787 AMD_CG_SUPPORT_GFX_CGCG |
788 AMD_CG_SUPPORT_GFX_CGLS |
789 AMD_CG_SUPPORT_GFX_3D_CGCG |
790 AMD_CG_SUPPORT_GFX_3D_CGLS |
791 AMD_CG_SUPPORT_MC_MGCG |
792 AMD_CG_SUPPORT_MC_LS |
793 AMD_CG_SUPPORT_GFX_FGCG |
794 AMD_CG_SUPPORT_VCN_MGCG |
795 AMD_CG_SUPPORT_SDMA_MGCG |
796 AMD_CG_SUPPORT_SDMA_LS |
797 AMD_CG_SUPPORT_JPEG_MGCG;
798 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
799 AMD_PG_SUPPORT_VCN |
800 AMD_PG_SUPPORT_VCN_DPG |
801 AMD_PG_SUPPORT_JPEG;
802 if (adev->apu_flags & AMD_APU_IS_VANGOGH)
803 adev->external_rev_id = adev->rev_id + 0x01;
804 break;
805 case IP_VERSION(10, 3, 4):
806 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
807 AMD_CG_SUPPORT_GFX_CGCG |
808 AMD_CG_SUPPORT_GFX_CGLS |
809 AMD_CG_SUPPORT_GFX_3D_CGCG |
810 AMD_CG_SUPPORT_VCN_MGCG |
811 AMD_CG_SUPPORT_JPEG_MGCG |
812 AMD_CG_SUPPORT_MC_MGCG |
813 AMD_CG_SUPPORT_MC_LS |
814 AMD_CG_SUPPORT_HDP_MGCG |
815 AMD_CG_SUPPORT_HDP_LS |
816 AMD_CG_SUPPORT_IH_CG;
817 adev->pg_flags = AMD_PG_SUPPORT_VCN |
818 AMD_PG_SUPPORT_VCN_DPG |
819 AMD_PG_SUPPORT_JPEG |
820 AMD_PG_SUPPORT_ATHUB |
821 AMD_PG_SUPPORT_MMHUB;
822 adev->external_rev_id = adev->rev_id + 0x3c;
823 break;
824 case IP_VERSION(10, 3, 5):
825 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
826 AMD_CG_SUPPORT_GFX_CGCG |
827 AMD_CG_SUPPORT_GFX_CGLS |
828 AMD_CG_SUPPORT_GFX_3D_CGCG |
829 AMD_CG_SUPPORT_MC_MGCG |
830 AMD_CG_SUPPORT_MC_LS |
831 AMD_CG_SUPPORT_HDP_MGCG |
832 AMD_CG_SUPPORT_HDP_LS |
833 AMD_CG_SUPPORT_IH_CG |
834 AMD_CG_SUPPORT_VCN_MGCG;
835 adev->pg_flags = AMD_PG_SUPPORT_VCN |
836 AMD_PG_SUPPORT_VCN_DPG |
837 AMD_PG_SUPPORT_ATHUB |
838 AMD_PG_SUPPORT_MMHUB;
839 adev->external_rev_id = adev->rev_id + 0x46;
840 break;
841 case IP_VERSION(10, 3, 3):
842 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
843 AMD_CG_SUPPORT_GFX_MGLS |
844 AMD_CG_SUPPORT_GFX_CGCG |
845 AMD_CG_SUPPORT_GFX_CGLS |
846 AMD_CG_SUPPORT_GFX_3D_CGCG |
847 AMD_CG_SUPPORT_GFX_3D_CGLS |
848 AMD_CG_SUPPORT_GFX_RLC_LS |
849 AMD_CG_SUPPORT_GFX_CP_LS |
850 AMD_CG_SUPPORT_GFX_FGCG |
851 AMD_CG_SUPPORT_MC_MGCG |
852 AMD_CG_SUPPORT_MC_LS |
853 AMD_CG_SUPPORT_SDMA_LS |
854 AMD_CG_SUPPORT_HDP_MGCG |
855 AMD_CG_SUPPORT_HDP_LS |
856 AMD_CG_SUPPORT_ATHUB_MGCG |
857 AMD_CG_SUPPORT_ATHUB_LS |
858 AMD_CG_SUPPORT_IH_CG |
859 AMD_CG_SUPPORT_VCN_MGCG |
860 AMD_CG_SUPPORT_JPEG_MGCG |
861 AMD_CG_SUPPORT_SDMA_MGCG;
862 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
863 AMD_PG_SUPPORT_VCN |
864 AMD_PG_SUPPORT_VCN_DPG |
865 AMD_PG_SUPPORT_JPEG;
866 if (adev->pdev->device == 0x1681)
867 adev->external_rev_id = 0x20;
868 else
869 adev->external_rev_id = adev->rev_id + 0x01;
870 break;
871 case IP_VERSION(10, 1, 3):
872 case IP_VERSION(10, 1, 4):
873 adev->cg_flags = 0;
874 adev->pg_flags = 0;
875 adev->external_rev_id = adev->rev_id + 0x82;
876 break;
877 case IP_VERSION(10, 3, 6):
878 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
879 AMD_CG_SUPPORT_GFX_MGLS |
880 AMD_CG_SUPPORT_GFX_CGCG |
881 AMD_CG_SUPPORT_GFX_CGLS |
882 AMD_CG_SUPPORT_GFX_3D_CGCG |
883 AMD_CG_SUPPORT_GFX_3D_CGLS |
884 AMD_CG_SUPPORT_GFX_RLC_LS |
885 AMD_CG_SUPPORT_GFX_CP_LS |
886 AMD_CG_SUPPORT_GFX_FGCG |
887 AMD_CG_SUPPORT_MC_MGCG |
888 AMD_CG_SUPPORT_MC_LS |
889 AMD_CG_SUPPORT_SDMA_LS |
890 AMD_CG_SUPPORT_HDP_MGCG |
891 AMD_CG_SUPPORT_HDP_LS |
892 AMD_CG_SUPPORT_ATHUB_MGCG |
893 AMD_CG_SUPPORT_ATHUB_LS |
894 AMD_CG_SUPPORT_IH_CG |
895 AMD_CG_SUPPORT_VCN_MGCG |
896 AMD_CG_SUPPORT_JPEG_MGCG;
897 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
898 AMD_PG_SUPPORT_VCN |
899 AMD_PG_SUPPORT_VCN_DPG |
900 AMD_PG_SUPPORT_JPEG;
901 adev->external_rev_id = adev->rev_id + 0x01;
902 break;
903 case IP_VERSION(10, 3, 7):
904 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
905 AMD_CG_SUPPORT_GFX_MGLS |
906 AMD_CG_SUPPORT_GFX_CGCG |
907 AMD_CG_SUPPORT_GFX_CGLS |
908 AMD_CG_SUPPORT_GFX_3D_CGCG |
909 AMD_CG_SUPPORT_GFX_3D_CGLS |
910 AMD_CG_SUPPORT_GFX_RLC_LS |
911 AMD_CG_SUPPORT_GFX_CP_LS |
912 AMD_CG_SUPPORT_GFX_FGCG |
913 AMD_CG_SUPPORT_MC_MGCG |
914 AMD_CG_SUPPORT_MC_LS |
915 AMD_CG_SUPPORT_SDMA_LS |
916 AMD_CG_SUPPORT_HDP_MGCG |
917 AMD_CG_SUPPORT_HDP_LS |
918 AMD_CG_SUPPORT_ATHUB_MGCG |
919 AMD_CG_SUPPORT_ATHUB_LS |
920 AMD_CG_SUPPORT_IH_CG |
921 AMD_CG_SUPPORT_VCN_MGCG |
922 AMD_CG_SUPPORT_JPEG_MGCG |
923 AMD_CG_SUPPORT_SDMA_MGCG;
924 adev->pg_flags = AMD_PG_SUPPORT_VCN |
925 AMD_PG_SUPPORT_VCN_DPG |
926 AMD_PG_SUPPORT_JPEG |
927 AMD_PG_SUPPORT_GFX_PG;
928 adev->external_rev_id = adev->rev_id + 0x01;
929 break;
930 default:
931 /* FIXME: not supported yet */
932 return -EINVAL;
933 }
934
935 if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK)
936 adev->pg_flags &= ~(AMD_PG_SUPPORT_VCN |
937 AMD_PG_SUPPORT_VCN_DPG |
938 AMD_PG_SUPPORT_JPEG);
939
940 if (amdgpu_sriov_vf(adev)) {
941 amdgpu_virt_init_setting(adev);
942 xgpu_nv_mailbox_set_irq_funcs(adev);
943 }
944
945 return 0;
946}
947
948static int nv_common_late_init(struct amdgpu_ip_block *ip_block)
949{
950 struct amdgpu_device *adev = ip_block->adev;
951
952 if (amdgpu_sriov_vf(adev)) {
953 xgpu_nv_mailbox_get_irq(adev);
954 if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) {
955 amdgpu_virt_update_sriov_video_codec(adev,
956 encode: sriov_sc_video_codecs_encode_array,
957 ARRAY_SIZE(sriov_sc_video_codecs_encode_array),
958 decode: sriov_sc_video_codecs_decode_array_vcn1,
959 ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn1));
960 } else {
961 amdgpu_virt_update_sriov_video_codec(adev,
962 encode: sriov_sc_video_codecs_encode_array,
963 ARRAY_SIZE(sriov_sc_video_codecs_encode_array),
964 decode: sriov_sc_video_codecs_decode_array_vcn0,
965 ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn0));
966 }
967 }
968
969 /* Enable selfring doorbell aperture late because doorbell BAR
970 * aperture will change if resize BAR successfully in gmc sw_init.
971 */
972 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true);
973
974 return 0;
975}
976
977static int nv_common_sw_init(struct amdgpu_ip_block *ip_block)
978{
979 struct amdgpu_device *adev = ip_block->adev;
980
981 if (amdgpu_sriov_vf(adev))
982 xgpu_nv_mailbox_add_irq_id(adev);
983
984 return 0;
985}
986
987static int nv_common_hw_init(struct amdgpu_ip_block *ip_block)
988{
989 struct amdgpu_device *adev = ip_block->adev;
990
991 if (adev->nbio.funcs->apply_lc_spc_mode_wa)
992 adev->nbio.funcs->apply_lc_spc_mode_wa(adev);
993
994 if (adev->nbio.funcs->apply_l1_link_width_reconfig_wa)
995 adev->nbio.funcs->apply_l1_link_width_reconfig_wa(adev);
996
997 /* enable aspm */
998 nv_program_aspm(adev);
999 /* setup nbio registers */
1000 adev->nbio.funcs->init_registers(adev);
1001 /* remap HDP registers to a hole in mmio space,
1002 * for the purpose of expose those registers
1003 * to process space
1004 */
1005 if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev))
1006 adev->nbio.funcs->remap_hdp_registers(adev);
1007 /* enable the doorbell aperture */
1008 adev->nbio.funcs->enable_doorbell_aperture(adev, true);
1009
1010 return 0;
1011}
1012
1013static int nv_common_hw_fini(struct amdgpu_ip_block *ip_block)
1014{
1015 struct amdgpu_device *adev = ip_block->adev;
1016
1017 /* Disable the doorbell aperture and selfring doorbell aperture
1018 * separately in hw_fini because nv_enable_doorbell_aperture
1019 * has been removed and there is no need to delay disabling
1020 * selfring doorbell.
1021 */
1022 adev->nbio.funcs->enable_doorbell_aperture(adev, false);
1023 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false);
1024
1025 return 0;
1026}
1027
1028static int nv_common_suspend(struct amdgpu_ip_block *ip_block)
1029{
1030 return nv_common_hw_fini(ip_block);
1031}
1032
1033static int nv_common_resume(struct amdgpu_ip_block *ip_block)
1034{
1035 return nv_common_hw_init(ip_block);
1036}
1037
1038static bool nv_common_is_idle(struct amdgpu_ip_block *ip_block)
1039{
1040 return true;
1041}
1042
1043static int nv_common_set_clockgating_state(struct amdgpu_ip_block *ip_block,
1044 enum amd_clockgating_state state)
1045{
1046 struct amdgpu_device *adev = ip_block->adev;
1047
1048 if (amdgpu_sriov_vf(adev))
1049 return 0;
1050
1051 switch (amdgpu_ip_version(adev, ip: NBIO_HWIP, inst: 0)) {
1052 case IP_VERSION(2, 3, 0):
1053 case IP_VERSION(2, 3, 1):
1054 case IP_VERSION(2, 3, 2):
1055 case IP_VERSION(3, 3, 0):
1056 case IP_VERSION(3, 3, 1):
1057 case IP_VERSION(3, 3, 2):
1058 case IP_VERSION(3, 3, 3):
1059 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1060 state == AMD_CG_STATE_GATE);
1061 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1062 state == AMD_CG_STATE_GATE);
1063 adev->hdp.funcs->update_clock_gating(adev,
1064 state == AMD_CG_STATE_GATE);
1065 adev->smuio.funcs->update_rom_clock_gating(adev,
1066 state == AMD_CG_STATE_GATE);
1067 break;
1068 default:
1069 break;
1070 }
1071 return 0;
1072}
1073
1074static int nv_common_set_powergating_state(struct amdgpu_ip_block *ip_block,
1075 enum amd_powergating_state state)
1076{
1077 /* TODO */
1078 return 0;
1079}
1080
1081static void nv_common_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)
1082{
1083 struct amdgpu_device *adev = ip_block->adev;
1084
1085 if (amdgpu_sriov_vf(adev))
1086 *flags = 0;
1087
1088 adev->nbio.funcs->get_clockgating_state(adev, flags);
1089
1090 adev->hdp.funcs->get_clock_gating_state(adev, flags);
1091
1092 adev->smuio.funcs->get_clock_gating_state(adev, flags);
1093}
1094
1095static const struct amd_ip_funcs nv_common_ip_funcs = {
1096 .name = "nv_common",
1097 .early_init = nv_common_early_init,
1098 .late_init = nv_common_late_init,
1099 .sw_init = nv_common_sw_init,
1100 .hw_init = nv_common_hw_init,
1101 .hw_fini = nv_common_hw_fini,
1102 .suspend = nv_common_suspend,
1103 .resume = nv_common_resume,
1104 .is_idle = nv_common_is_idle,
1105 .set_clockgating_state = nv_common_set_clockgating_state,
1106 .set_powergating_state = nv_common_set_powergating_state,
1107 .get_clockgating_state = nv_common_get_clockgating_state,
1108};
1109

source code of linux/drivers/gpu/drm/amd/amdgpu/nv.c