1/*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include "amdgpu.h"
24#include "nbio_v7_4.h"
25#include "amdgpu_ras.h"
26
27#include "nbio/nbio_7_4_offset.h"
28#include "nbio/nbio_7_4_sh_mask.h"
29#include "nbio/nbio_7_4_0_smn.h"
30#include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
31#include <uapi/linux/kfd_ioctl.h>
32
33#define smnPCIE_LC_CNTL 0x11140280
34#define smnPCIE_LC_CNTL3 0x111402d4
35#define smnPCIE_LC_CNTL6 0x111402ec
36#define smnPCIE_LC_CNTL7 0x111402f0
37#define smnNBIF_MGCG_CTRL_LCLK 0x1013a21c
38#define smnRCC_BIF_STRAP3 0x1012348c
39#define RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK 0x0000FFFFL
40#define RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK 0xFFFF0000L
41#define smnRCC_BIF_STRAP5 0x10123494
42#define RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK 0x0000FFFFL
43#define smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2 0x1014008c
44#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
45#define smnBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP 0x10140324
46#define smnPSWUSP0_PCIE_LC_CNTL2 0x111402c4
47#define smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL 0x10123538
48#define smnRCC_BIF_STRAP2 0x10123488
49#define RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK 0x00004000L
50#define RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT 0x0
51#define RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT 0x10
52#define RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT 0x0
53
54/*
55 * These are nbio v7_4_1 registers mask. Temporarily define these here since
56 * nbio v7_4_1 header is incomplete.
57 */
58#define GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L /* Don't use. Firmware uses this bit internally */
59#define GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L
60#define GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L
61#define GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L
62#define GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L
63#define GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L
64#define GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L
65#define GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L
66#define GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L
67
68#define mmBIF_MMSCH1_DOORBELL_RANGE 0x01dc
69#define mmBIF_MMSCH1_DOORBELL_RANGE_BASE_IDX 2
70//BIF_MMSCH1_DOORBELL_RANGE
71#define BIF_MMSCH1_DOORBELL_RANGE__OFFSET__SHIFT 0x2
72#define BIF_MMSCH1_DOORBELL_RANGE__SIZE__SHIFT 0x10
73#define BIF_MMSCH1_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL
74#define BIF_MMSCH1_DOORBELL_RANGE__SIZE_MASK 0x001F0000L
75
76#define BIF_MMSCH1_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL
77#define BIF_MMSCH1_DOORBELL_RANGE__SIZE_MASK 0x001F0000L
78
79#define mmBIF_MMSCH1_DOORBELL_RANGE_ALDE 0x01d8
80#define mmBIF_MMSCH1_DOORBELL_RANGE_ALDE_BASE_IDX 2
81//BIF_MMSCH1_DOORBELL_ALDE_RANGE
82#define BIF_MMSCH1_DOORBELL_RANGE_ALDE__OFFSET__SHIFT 0x2
83#define BIF_MMSCH1_DOORBELL_RANGE_ALDE__SIZE__SHIFT 0x10
84#define BIF_MMSCH1_DOORBELL_RANGE_ALDE__OFFSET_MASK 0x00000FFCL
85#define BIF_MMSCH1_DOORBELL_RANGE_ALDE__SIZE_MASK 0x001F0000L
86
87#define mmRCC_DEV0_EPF0_STRAP0_ALDE 0x0015
88#define mmRCC_DEV0_EPF0_STRAP0_ALDE_BASE_IDX 2
89
90#define mmBIF_DOORBELL_INT_CNTL_ALDE 0x00fe
91#define mmBIF_DOORBELL_INT_CNTL_ALDE_BASE_IDX 2
92#define BIF_DOORBELL_INT_CNTL_ALDE__DOORBELL_INTERRUPT_DISABLE__SHIFT 0x18
93#define BIF_DOORBELL_INT_CNTL_ALDE__DOORBELL_INTERRUPT_DISABLE_MASK 0x01000000L
94
95#define mmBIF_INTR_CNTL_ALDE 0x0101
96#define mmBIF_INTR_CNTL_ALDE_BASE_IDX 2
97
98static void nbio_v7_4_query_ras_error_count(struct amdgpu_device *adev,
99 void *ras_error_status);
100
101static void nbio_v7_4_remap_hdp_registers(struct amdgpu_device *adev)
102{
103 WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
104 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
105 WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL,
106 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
107}
108
109static u32 nbio_v7_4_get_rev_id(struct amdgpu_device *adev)
110{
111 u32 tmp;
112
113 if (adev->asic_type == CHIP_ALDEBARAN)
114 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0_ALDE);
115 else
116 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
117
118 tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
119 tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
120
121 return tmp;
122}
123
124static void nbio_v7_4_mc_access_enable(struct amdgpu_device *adev, bool enable)
125{
126 if (enable)
127 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN,
128 BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
129 else
130 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0);
131}
132
133static u32 nbio_v7_4_get_memsize(struct amdgpu_device *adev)
134{
135 return RREG32_SOC15(NBIO, 0, mmRCC_CONFIG_MEMSIZE);
136}
137
138static void nbio_v7_4_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
139 bool use_doorbell, int doorbell_index, int doorbell_size)
140{
141 u32 reg, doorbell_range;
142
143 if (instance < 2) {
144 reg = instance +
145 SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE);
146 } else {
147 /*
148 * These registers address of SDMA2~7 is not consecutive
149 * from SDMA0~1. Need plus 4 dwords offset.
150 *
151 * BIF_SDMA0_DOORBELL_RANGE: 0x3bc0
152 * BIF_SDMA1_DOORBELL_RANGE: 0x3bc4
153 * BIF_SDMA2_DOORBELL_RANGE: 0x3bd8
154 * BIF_SDMA4_DOORBELL_RANGE:
155 * ARCTURUS: 0x3be0
156 * ALDEBARAN: 0x3be4
157 */
158 if (adev->asic_type == CHIP_ALDEBARAN && instance == 4)
159 reg = instance + 0x4 + 0x1 +
160 SOC15_REG_OFFSET(NBIO, 0,
161 mmBIF_SDMA0_DOORBELL_RANGE);
162 else
163 reg = instance + 0x4 +
164 SOC15_REG_OFFSET(NBIO, 0,
165 mmBIF_SDMA0_DOORBELL_RANGE);
166 }
167
168 doorbell_range = RREG32(reg);
169
170 if (use_doorbell) {
171 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
172 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, doorbell_size);
173 } else
174 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
175
176 WREG32(reg, doorbell_range);
177}
178
179static void nbio_v7_4_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell,
180 int doorbell_index, int instance)
181{
182 u32 reg;
183 u32 doorbell_range;
184
185 if (instance) {
186 if (adev->asic_type == CHIP_ALDEBARAN)
187 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH1_DOORBELL_RANGE_ALDE);
188 else
189 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH1_DOORBELL_RANGE);
190 } else
191 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE);
192
193 doorbell_range = RREG32(reg);
194
195 if (use_doorbell) {
196 doorbell_range = REG_SET_FIELD(doorbell_range,
197 BIF_MMSCH0_DOORBELL_RANGE, OFFSET,
198 doorbell_index);
199 doorbell_range = REG_SET_FIELD(doorbell_range,
200 BIF_MMSCH0_DOORBELL_RANGE, SIZE, 8);
201 } else
202 doorbell_range = REG_SET_FIELD(doorbell_range,
203 BIF_MMSCH0_DOORBELL_RANGE, SIZE, 0);
204
205 WREG32(reg, doorbell_range);
206}
207
208static void nbio_v7_4_enable_doorbell_aperture(struct amdgpu_device *adev,
209 bool enable)
210{
211 WREG32_FIELD15(NBIO, 0, RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0);
212}
213
214static void nbio_v7_4_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
215 bool enable)
216{
217 u32 tmp = 0;
218
219 if (enable) {
220 tmp = REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_EN, 1) |
221 REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_MODE, 1) |
222 REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_SIZE, 0);
223
224 WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_BASE_LOW,
225 lower_32_bits(adev->doorbell.base));
226 WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH,
227 upper_32_bits(adev->doorbell.base));
228 }
229
230 WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_CNTL, tmp);
231}
232
233static void nbio_v7_4_ih_doorbell_range(struct amdgpu_device *adev,
234 bool use_doorbell, int doorbell_index)
235{
236 u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE);
237
238 if (use_doorbell) {
239 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index);
240 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 8);
241 } else
242 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0);
243
244 WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range);
245}
246
247
248static void nbio_v7_4_update_medium_grain_clock_gating(struct amdgpu_device *adev,
249 bool enable)
250{
251 //TODO: Add support for v7.4
252}
253
254static void nbio_v7_4_update_medium_grain_light_sleep(struct amdgpu_device *adev,
255 bool enable)
256{
257 uint32_t def, data;
258
259 def = data = RREG32_PCIE(smnPCIE_CNTL2);
260 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
261 data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
262 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
263 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
264 } else {
265 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
266 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
267 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
268 }
269
270 if (def != data)
271 WREG32_PCIE(smnPCIE_CNTL2, data);
272}
273
274static void nbio_v7_4_get_clockgating_state(struct amdgpu_device *adev,
275 u64 *flags)
276{
277 int data;
278
279 /* AMD_CG_SUPPORT_BIF_MGCG */
280 data = RREG32_PCIE(smnCPM_CONTROL);
281 if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK)
282 *flags |= AMD_CG_SUPPORT_BIF_MGCG;
283
284 /* AMD_CG_SUPPORT_BIF_LS */
285 data = RREG32_PCIE(smnPCIE_CNTL2);
286 if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
287 *flags |= AMD_CG_SUPPORT_BIF_LS;
288}
289
290static void nbio_v7_4_ih_control(struct amdgpu_device *adev)
291{
292 u32 interrupt_cntl;
293
294 /* setup interrupt control */
295 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
296 interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL);
297 /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
298 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
299 */
300 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
301 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
302 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
303 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl);
304}
305
306static u32 nbio_v7_4_get_hdp_flush_req_offset(struct amdgpu_device *adev)
307{
308 return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ);
309}
310
311static u32 nbio_v7_4_get_hdp_flush_done_offset(struct amdgpu_device *adev)
312{
313 return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE);
314}
315
316static u32 nbio_v7_4_get_pcie_index_offset(struct amdgpu_device *adev)
317{
318 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2);
319}
320
321static u32 nbio_v7_4_get_pcie_data_offset(struct amdgpu_device *adev)
322{
323 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2);
324}
325
326const struct nbio_hdp_flush_reg nbio_v7_4_hdp_flush_reg = {
327 .ref_and_mask_cp0 = GPU_HDP_FLUSH_DONE__CP0_MASK,
328 .ref_and_mask_cp1 = GPU_HDP_FLUSH_DONE__CP1_MASK,
329 .ref_and_mask_cp2 = GPU_HDP_FLUSH_DONE__CP2_MASK,
330 .ref_and_mask_cp3 = GPU_HDP_FLUSH_DONE__CP3_MASK,
331 .ref_and_mask_cp4 = GPU_HDP_FLUSH_DONE__CP4_MASK,
332 .ref_and_mask_cp5 = GPU_HDP_FLUSH_DONE__CP5_MASK,
333 .ref_and_mask_cp6 = GPU_HDP_FLUSH_DONE__CP6_MASK,
334 .ref_and_mask_cp7 = GPU_HDP_FLUSH_DONE__CP7_MASK,
335 .ref_and_mask_cp8 = GPU_HDP_FLUSH_DONE__CP8_MASK,
336 .ref_and_mask_cp9 = GPU_HDP_FLUSH_DONE__CP9_MASK,
337 .ref_and_mask_sdma0 = GPU_HDP_FLUSH_DONE__SDMA0_MASK,
338 .ref_and_mask_sdma1 = GPU_HDP_FLUSH_DONE__SDMA1_MASK,
339};
340
341static void nbio_v7_4_init_registers(struct amdgpu_device *adev)
342{
343 uint32_t baco_cntl;
344
345 if (amdgpu_ip_version(adev, ip: NBIO_HWIP, inst: 0) == IP_VERSION(7, 4, 4) &&
346 !amdgpu_sriov_vf(adev)) {
347 baco_cntl = RREG32_SOC15(NBIO, 0, mmBACO_CNTL);
348 if (baco_cntl &
349 (BACO_CNTL__BACO_DUMMY_EN_MASK | BACO_CNTL__BACO_EN_MASK)) {
350 baco_cntl &= ~(BACO_CNTL__BACO_DUMMY_EN_MASK |
351 BACO_CNTL__BACO_EN_MASK);
352 dev_dbg(adev->dev, "Unsetting baco dummy mode %x",
353 baco_cntl);
354 WREG32_SOC15(NBIO, 0, mmBACO_CNTL, baco_cntl);
355 }
356 }
357}
358
359static void nbio_v7_4_handle_ras_controller_intr_no_bifring(struct amdgpu_device *adev)
360{
361 uint32_t bif_doorbell_intr_cntl;
362 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head: adev->nbio.ras_if);
363 struct ras_err_data err_data;
364 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
365
366 if (amdgpu_ras_error_data_init(err_data: &err_data))
367 return;
368
369 if (adev->asic_type == CHIP_ALDEBARAN)
370 bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL_ALDE);
371 else
372 bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL);
373
374 if (REG_GET_FIELD(bif_doorbell_intr_cntl,
375 BIF_DOORBELL_INT_CNTL, RAS_CNTLR_INTERRUPT_STATUS)) {
376 /* driver has to clear the interrupt status when bif ring is disabled */
377 bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,
378 BIF_DOORBELL_INT_CNTL,
379 RAS_CNTLR_INTERRUPT_CLEAR, 1);
380 if (adev->asic_type == CHIP_ALDEBARAN)
381 WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL_ALDE, bif_doorbell_intr_cntl);
382 else
383 WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl);
384
385 if (ras && !ras->disable_ras_err_cnt_harvest && obj) {
386 /*
387 * clear error status after ras_controller_intr
388 * according to hw team and count ue number
389 * for query
390 */
391 nbio_v7_4_query_ras_error_count(adev, ras_error_status: &err_data);
392
393 /* logging on error cnt and printing for awareness */
394 obj->err_data.ue_count += err_data.ue_count;
395 obj->err_data.ce_count += err_data.ce_count;
396
397 if (err_data.ce_count)
398 dev_info(adev->dev, "%ld correctable hardware "
399 "errors detected in %s block\n",
400 obj->err_data.ce_count,
401 get_ras_block_str(adev->nbio.ras_if));
402
403 if (err_data.ue_count)
404 dev_info(adev->dev, "%ld uncorrectable hardware "
405 "errors detected in %s block\n",
406 obj->err_data.ue_count,
407 get_ras_block_str(adev->nbio.ras_if));
408 }
409
410 dev_info(adev->dev, "RAS controller interrupt triggered "
411 "by NBIF error\n");
412
413 /* ras_controller_int is dedicated for nbif ras error,
414 * not the global interrupt for sync flood
415 */
416 amdgpu_ras_global_ras_isr(adev);
417 }
418
419 amdgpu_ras_error_data_fini(err_data: &err_data);
420}
421
422static void nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring(struct amdgpu_device *adev)
423{
424 uint32_t bif_doorbell_intr_cntl;
425
426 if (adev->asic_type == CHIP_ALDEBARAN)
427 bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL_ALDE);
428 else
429 bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL);
430
431 if (REG_GET_FIELD(bif_doorbell_intr_cntl,
432 BIF_DOORBELL_INT_CNTL, RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS)) {
433 /* driver has to clear the interrupt status when bif ring is disabled */
434 bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,
435 BIF_DOORBELL_INT_CNTL,
436 RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR, 1);
437
438 if (adev->asic_type == CHIP_ALDEBARAN)
439 WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL_ALDE, bif_doorbell_intr_cntl);
440 else
441 WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl);
442
443 amdgpu_ras_global_ras_isr(adev);
444 }
445}
446
447
448static int nbio_v7_4_set_ras_controller_irq_state(struct amdgpu_device *adev,
449 struct amdgpu_irq_src *src,
450 unsigned type,
451 enum amdgpu_interrupt_state state)
452{
453 /* The ras_controller_irq enablement should be done in psp bl when it
454 * tries to enable ras feature. Driver only need to set the correct interrupt
455 * vector for bare-metal and sriov use case respectively
456 */
457 uint32_t bif_intr_cntl;
458
459 if (adev->asic_type == CHIP_ALDEBARAN)
460 bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL_ALDE);
461 else
462 bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL);
463
464 if (state == AMDGPU_IRQ_STATE_ENABLE) {
465 /* set interrupt vector select bit to 0 to select
466 * vetcor 1 for bare metal case */
467 bif_intr_cntl = REG_SET_FIELD(bif_intr_cntl,
468 BIF_INTR_CNTL,
469 RAS_INTR_VEC_SEL, 0);
470
471 if (adev->asic_type == CHIP_ALDEBARAN)
472 WREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL_ALDE, bif_intr_cntl);
473 else
474 WREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL, bif_intr_cntl);
475
476 }
477
478 return 0;
479}
480
481static int nbio_v7_4_process_ras_controller_irq(struct amdgpu_device *adev,
482 struct amdgpu_irq_src *source,
483 struct amdgpu_iv_entry *entry)
484{
485 /* By design, the ih cookie for ras_controller_irq should be written
486 * to BIFring instead of general iv ring. However, due to known bif ring
487 * hw bug, it has to be disabled. There is no chance the process function
488 * will be involked. Just left it as a dummy one.
489 */
490 return 0;
491}
492
493static int nbio_v7_4_set_ras_err_event_athub_irq_state(struct amdgpu_device *adev,
494 struct amdgpu_irq_src *src,
495 unsigned type,
496 enum amdgpu_interrupt_state state)
497{
498 /* The ras_controller_irq enablement should be done in psp bl when it
499 * tries to enable ras feature. Driver only need to set the correct interrupt
500 * vector for bare-metal and sriov use case respectively
501 */
502 uint32_t bif_intr_cntl;
503
504 if (adev->asic_type == CHIP_ALDEBARAN)
505 bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL_ALDE);
506 else
507 bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL);
508
509 if (state == AMDGPU_IRQ_STATE_ENABLE) {
510 /* set interrupt vector select bit to 0 to select
511 * vetcor 1 for bare metal case */
512 bif_intr_cntl = REG_SET_FIELD(bif_intr_cntl,
513 BIF_INTR_CNTL,
514 RAS_INTR_VEC_SEL, 0);
515
516 if (adev->asic_type == CHIP_ALDEBARAN)
517 WREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL_ALDE, bif_intr_cntl);
518 else
519 WREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL, bif_intr_cntl);
520 }
521
522 return 0;
523}
524
525static int nbio_v7_4_process_err_event_athub_irq(struct amdgpu_device *adev,
526 struct amdgpu_irq_src *source,
527 struct amdgpu_iv_entry *entry)
528{
529 /* By design, the ih cookie for err_event_athub_irq should be written
530 * to BIFring instead of general iv ring. However, due to known bif ring
531 * hw bug, it has to be disabled. There is no chance the process function
532 * will be involked. Just left it as a dummy one.
533 */
534 return 0;
535}
536
537static const struct amdgpu_irq_src_funcs nbio_v7_4_ras_controller_irq_funcs = {
538 .set = nbio_v7_4_set_ras_controller_irq_state,
539 .process = nbio_v7_4_process_ras_controller_irq,
540};
541
542static const struct amdgpu_irq_src_funcs nbio_v7_4_ras_err_event_athub_irq_funcs = {
543 .set = nbio_v7_4_set_ras_err_event_athub_irq_state,
544 .process = nbio_v7_4_process_err_event_athub_irq,
545};
546
547static int nbio_v7_4_init_ras_controller_interrupt (struct amdgpu_device *adev)
548{
549 int r;
550
551 /* init the irq funcs */
552 adev->nbio.ras_controller_irq.funcs =
553 &nbio_v7_4_ras_controller_irq_funcs;
554 adev->nbio.ras_controller_irq.num_types = 1;
555
556 /* register ras controller interrupt */
557 r = amdgpu_irq_add_id(adev, client_id: SOC15_IH_CLIENTID_BIF,
558 NBIF_7_4__SRCID__RAS_CONTROLLER_INTERRUPT,
559 source: &adev->nbio.ras_controller_irq);
560
561 return r;
562}
563
564static int nbio_v7_4_init_ras_err_event_athub_interrupt (struct amdgpu_device *adev)
565{
566
567 int r;
568
569 /* init the irq funcs */
570 adev->nbio.ras_err_event_athub_irq.funcs =
571 &nbio_v7_4_ras_err_event_athub_irq_funcs;
572 adev->nbio.ras_err_event_athub_irq.num_types = 1;
573
574 /* register ras err event athub interrupt */
575 r = amdgpu_irq_add_id(adev, client_id: SOC15_IH_CLIENTID_BIF,
576 NBIF_7_4__SRCID__ERREVENT_ATHUB_INTERRUPT,
577 source: &adev->nbio.ras_err_event_athub_irq);
578
579 return r;
580}
581
582#define smnPARITY_ERROR_STATUS_UNCORR_GRP2 0x13a20030
583#define smnPARITY_ERROR_STATUS_UNCORR_GRP2_ALDE 0x13b20030
584#define smnRAS_GLOBAL_STATUS_LO_ALDE 0x13b20020
585
586static void nbio_v7_4_query_ras_error_count(struct amdgpu_device *adev,
587 void *ras_error_status)
588{
589 uint32_t global_sts, central_sts, int_eoi, parity_sts;
590 uint32_t corr, fatal, non_fatal;
591 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
592
593 if (adev->asic_type == CHIP_ALDEBARAN)
594 global_sts = RREG32_PCIE(smnRAS_GLOBAL_STATUS_LO_ALDE);
595 else
596 global_sts = RREG32_PCIE(smnRAS_GLOBAL_STATUS_LO);
597
598 corr = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO, ParityErrCorr);
599 fatal = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO, ParityErrFatal);
600 non_fatal = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO,
601 ParityErrNonFatal);
602
603 if (adev->asic_type == CHIP_ALDEBARAN)
604 parity_sts = RREG32_PCIE(smnPARITY_ERROR_STATUS_UNCORR_GRP2_ALDE);
605 else
606 parity_sts = RREG32_PCIE(smnPARITY_ERROR_STATUS_UNCORR_GRP2);
607
608 if (corr)
609 err_data->ce_count++;
610 if (fatal)
611 err_data->ue_count++;
612
613 if (corr || fatal || non_fatal) {
614 central_sts = RREG32_PCIE(smnBIFL_RAS_CENTRAL_STATUS);
615
616 /* clear error status register */
617 if (adev->asic_type == CHIP_ALDEBARAN)
618 WREG32_PCIE(smnRAS_GLOBAL_STATUS_LO_ALDE, global_sts);
619 else
620 WREG32_PCIE(smnRAS_GLOBAL_STATUS_LO, global_sts);
621
622 if (fatal)
623 {
624 /* clear parity fatal error indication field */
625 if (adev->asic_type == CHIP_ALDEBARAN)
626 WREG32_PCIE(smnPARITY_ERROR_STATUS_UNCORR_GRP2_ALDE, parity_sts);
627 else
628 WREG32_PCIE(smnPARITY_ERROR_STATUS_UNCORR_GRP2, parity_sts);
629 }
630
631 if (REG_GET_FIELD(central_sts, BIFL_RAS_CENTRAL_STATUS,
632 BIFL_RasContller_Intr_Recv)) {
633 /* clear interrupt status register */
634 WREG32_PCIE(smnBIFL_RAS_CENTRAL_STATUS, central_sts);
635 int_eoi = RREG32_PCIE(smnIOHC_INTERRUPT_EOI);
636 int_eoi = REG_SET_FIELD(int_eoi,
637 IOHC_INTERRUPT_EOI, SMI_EOI, 1);
638 WREG32_PCIE(smnIOHC_INTERRUPT_EOI, int_eoi);
639 }
640 }
641}
642
643static void nbio_v7_4_enable_doorbell_interrupt(struct amdgpu_device *adev,
644 bool enable)
645{
646 if (adev->asic_type == CHIP_ALDEBARAN)
647 WREG32_FIELD15(NBIO, 0, BIF_DOORBELL_INT_CNTL_ALDE,
648 DOORBELL_INTERRUPT_DISABLE, enable ? 0 : 1);
649 else
650 WREG32_FIELD15(NBIO, 0, BIF_DOORBELL_INT_CNTL,
651 DOORBELL_INTERRUPT_DISABLE, enable ? 0 : 1);
652}
653
654const struct amdgpu_ras_block_hw_ops nbio_v7_4_ras_hw_ops = {
655 .query_ras_error_count = nbio_v7_4_query_ras_error_count,
656};
657
658struct amdgpu_nbio_ras nbio_v7_4_ras = {
659 .ras_block = {
660 .ras_comm = {
661 .name = "pcie_bif",
662 .block = AMDGPU_RAS_BLOCK__PCIE_BIF,
663 .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
664 },
665 .hw_ops = &nbio_v7_4_ras_hw_ops,
666 .ras_late_init = amdgpu_nbio_ras_late_init,
667 },
668 .handle_ras_controller_intr_no_bifring = nbio_v7_4_handle_ras_controller_intr_no_bifring,
669 .handle_ras_err_event_athub_intr_no_bifring = nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring,
670 .init_ras_controller_interrupt = nbio_v7_4_init_ras_controller_interrupt,
671 .init_ras_err_event_athub_interrupt = nbio_v7_4_init_ras_err_event_athub_interrupt,
672};
673
674
675#ifdef CONFIG_PCIEASPM
676static void nbio_v7_4_program_ltr(struct amdgpu_device *adev)
677{
678 uint32_t def, data;
679
680 WREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL, 0x75EB);
681
682 def = data = RREG32_PCIE(smnRCC_BIF_STRAP2);
683 data &= ~RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK;
684 if (def != data)
685 WREG32_PCIE(smnRCC_BIF_STRAP2, data);
686
687 def = data = RREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL);
688 data &= ~EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK;
689 if (def != data)
690 WREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL, data);
691
692 def = data = RREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2);
693 data |= BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK;
694 if (def != data)
695 WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data);
696}
697#endif
698
699static void nbio_v7_4_program_aspm(struct amdgpu_device *adev)
700{
701#ifdef CONFIG_PCIEASPM
702 uint32_t def, data;
703
704 if (amdgpu_ip_version(adev, ip: NBIO_HWIP, inst: 0) == IP_VERSION(7, 4, 4))
705 return;
706
707 def = data = RREG32_PCIE(smnPCIE_LC_CNTL);
708 data &= ~PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK;
709 data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK;
710 data |= PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK;
711 if (def != data)
712 WREG32_PCIE(smnPCIE_LC_CNTL, data);
713
714 def = data = RREG32_PCIE(smnPCIE_LC_CNTL7);
715 data |= PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK;
716 if (def != data)
717 WREG32_PCIE(smnPCIE_LC_CNTL7, data);
718
719 def = data = RREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK);
720 data |= NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK_MASK;
721 if (def != data)
722 WREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK, data);
723
724 def = data = RREG32_PCIE(smnPCIE_LC_CNTL3);
725 data |= PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK;
726 if (def != data)
727 WREG32_PCIE(smnPCIE_LC_CNTL3, data);
728
729 def = data = RREG32_PCIE(smnRCC_BIF_STRAP3);
730 data &= ~RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK;
731 data &= ~RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK;
732 if (def != data)
733 WREG32_PCIE(smnRCC_BIF_STRAP3, data);
734
735 def = data = RREG32_PCIE(smnRCC_BIF_STRAP5);
736 data &= ~RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK;
737 if (def != data)
738 WREG32_PCIE(smnRCC_BIF_STRAP5, data);
739
740 def = data = RREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2);
741 data &= ~BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK;
742 if (def != data)
743 WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data);
744
745 WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP, 0x10011001);
746
747 def = data = RREG32_PCIE(smnPSWUSP0_PCIE_LC_CNTL2);
748 data |= PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK |
749 PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK;
750 data &= ~PSWUSP0_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK;
751 if (def != data)
752 WREG32_PCIE(smnPSWUSP0_PCIE_LC_CNTL2, data);
753
754 def = data = RREG32_PCIE(smnPCIE_LC_CNTL6);
755 data |= PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK |
756 PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN_MASK;
757 if (def != data)
758 WREG32_PCIE(smnPCIE_LC_CNTL6, data);
759
760 /* Don't bother about LTR if LTR is not enabled
761 * in the path */
762 if (adev->pdev->ltr_path)
763 nbio_v7_4_program_ltr(adev);
764
765 def = data = RREG32_PCIE(smnRCC_BIF_STRAP3);
766 data |= 0x5DE0 << RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT;
767 data |= 0x0010 << RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT;
768 if (def != data)
769 WREG32_PCIE(smnRCC_BIF_STRAP3, data);
770
771 def = data = RREG32_PCIE(smnRCC_BIF_STRAP5);
772 data |= 0x0010 << RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT;
773 if (def != data)
774 WREG32_PCIE(smnRCC_BIF_STRAP5, data);
775
776 def = data = RREG32_PCIE(smnPCIE_LC_CNTL);
777 data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK;
778 data |= 0x9 << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT;
779 data |= 0x1 << PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT;
780 if (def != data)
781 WREG32_PCIE(smnPCIE_LC_CNTL, data);
782
783 def = data = RREG32_PCIE(smnPCIE_LC_CNTL3);
784 data &= ~PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK;
785 if (def != data)
786 WREG32_PCIE(smnPCIE_LC_CNTL3, data);
787#endif
788}
789
790#define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
791
792static void nbio_v7_4_set_reg_remap(struct amdgpu_device *adev)
793{
794 if (!amdgpu_sriov_vf(adev) && (PAGE_SIZE <= 4096)) {
795 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
796 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
797 } else {
798 adev->rmmio_remap.reg_offset =
799 SOC15_REG_OFFSET(NBIO, 0,
800 mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2;
801 adev->rmmio_remap.bus_addr = 0;
802 }
803}
804
805const struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
806 .get_hdp_flush_req_offset = nbio_v7_4_get_hdp_flush_req_offset,
807 .get_hdp_flush_done_offset = nbio_v7_4_get_hdp_flush_done_offset,
808 .get_pcie_index_offset = nbio_v7_4_get_pcie_index_offset,
809 .get_pcie_data_offset = nbio_v7_4_get_pcie_data_offset,
810 .get_rev_id = nbio_v7_4_get_rev_id,
811 .mc_access_enable = nbio_v7_4_mc_access_enable,
812 .get_memsize = nbio_v7_4_get_memsize,
813 .sdma_doorbell_range = nbio_v7_4_sdma_doorbell_range,
814 .vcn_doorbell_range = nbio_v7_4_vcn_doorbell_range,
815 .enable_doorbell_aperture = nbio_v7_4_enable_doorbell_aperture,
816 .enable_doorbell_selfring_aperture = nbio_v7_4_enable_doorbell_selfring_aperture,
817 .ih_doorbell_range = nbio_v7_4_ih_doorbell_range,
818 .enable_doorbell_interrupt = nbio_v7_4_enable_doorbell_interrupt,
819 .update_medium_grain_clock_gating = nbio_v7_4_update_medium_grain_clock_gating,
820 .update_medium_grain_light_sleep = nbio_v7_4_update_medium_grain_light_sleep,
821 .get_clockgating_state = nbio_v7_4_get_clockgating_state,
822 .ih_control = nbio_v7_4_ih_control,
823 .init_registers = nbio_v7_4_init_registers,
824 .remap_hdp_registers = nbio_v7_4_remap_hdp_registers,
825 .program_aspm = nbio_v7_4_program_aspm,
826 .set_reg_remap = nbio_v7_4_set_reg_remap,
827};
828

source code of linux/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c