1/*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include "amdgpu.h"
24#include "nbio_v7_2.h"
25
26#include "nbio/nbio_7_2_0_offset.h"
27#include "nbio/nbio_7_2_0_sh_mask.h"
28#include <uapi/linux/kfd_ioctl.h>
29
30#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_YC 0x0015
31#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_YC_BASE_IDX 2
32#define regBIF_BX0_BIF_FB_EN_YC 0x0100
33#define regBIF_BX0_BIF_FB_EN_YC_BASE_IDX 2
34#define regBIF1_PCIE_MST_CTRL_3 0x4601c6
35#define regBIF1_PCIE_MST_CTRL_3_BASE_IDX 5
36#define BIF1_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_MODE__SHIFT \
37 0x1b
38#define BIF1_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV__SHIFT \
39 0x1c
40#define BIF1_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_MODE_MASK \
41 0x08000000L
42#define BIF1_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV_MASK \
43 0x30000000L
44#define regBIF1_PCIE_TX_POWER_CTRL_1 0x460187
45#define regBIF1_PCIE_TX_POWER_CTRL_1_BASE_IDX 5
46#define BIF1_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK 0x00000001L
47#define BIF1_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK 0x00000008L
48
49static void nbio_v7_2_remap_hdp_registers(struct amdgpu_device *adev)
50{
51 WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL,
52 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
53 WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL,
54 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
55}
56
57static u32 nbio_v7_2_get_rev_id(struct amdgpu_device *adev)
58{
59 u32 tmp;
60
61 switch (amdgpu_ip_version(adev, ip: NBIO_HWIP, inst: 0)) {
62 case IP_VERSION(7, 2, 1):
63 case IP_VERSION(7, 3, 0):
64 case IP_VERSION(7, 5, 0):
65 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_YC);
66 break;
67 default:
68 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);
69 break;
70 }
71
72 tmp &= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
73 tmp >>= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
74
75 return tmp;
76}
77
78static void nbio_v7_2_mc_access_enable(struct amdgpu_device *adev, bool enable)
79{
80 switch (amdgpu_ip_version(adev, ip: NBIO_HWIP, inst: 0)) {
81 case IP_VERSION(7, 2, 1):
82 case IP_VERSION(7, 3, 0):
83 case IP_VERSION(7, 5, 0):
84 if (enable)
85 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN_YC,
86 BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK |
87 BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK);
88 else
89 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN_YC, 0);
90 break;
91 default:
92 if (enable)
93 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN,
94 BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK |
95 BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK);
96 else
97 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 0);
98 break;
99 }
100}
101
102static u32 nbio_v7_2_get_memsize(struct amdgpu_device *adev)
103{
104 return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE);
105}
106
107static void nbio_v7_2_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
108 bool use_doorbell, int doorbell_index,
109 int doorbell_size)
110{
111 u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_SDMA0_DOORBELL_RANGE);
112 u32 doorbell_range = RREG32_PCIE_PORT(reg);
113
114 if (use_doorbell) {
115 doorbell_range = REG_SET_FIELD(doorbell_range,
116 GDC0_BIF_SDMA0_DOORBELL_RANGE,
117 OFFSET, doorbell_index);
118 doorbell_range = REG_SET_FIELD(doorbell_range,
119 GDC0_BIF_SDMA0_DOORBELL_RANGE,
120 SIZE, doorbell_size);
121 } else {
122 doorbell_range = REG_SET_FIELD(doorbell_range,
123 GDC0_BIF_SDMA0_DOORBELL_RANGE,
124 SIZE, 0);
125 }
126
127 WREG32_PCIE_PORT(reg, doorbell_range);
128}
129
130static void nbio_v7_2_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell,
131 int doorbell_index, int instance)
132{
133 u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_VCN0_DOORBELL_RANGE);
134 u32 doorbell_range = RREG32_PCIE_PORT(reg);
135
136 if (use_doorbell) {
137 doorbell_range = REG_SET_FIELD(doorbell_range,
138 GDC0_BIF_VCN0_DOORBELL_RANGE, OFFSET,
139 doorbell_index);
140 doorbell_range = REG_SET_FIELD(doorbell_range,
141 GDC0_BIF_VCN0_DOORBELL_RANGE, SIZE, 8);
142 } else {
143 doorbell_range = REG_SET_FIELD(doorbell_range,
144 GDC0_BIF_VCN0_DOORBELL_RANGE, SIZE, 0);
145 }
146
147 WREG32_PCIE_PORT(reg, doorbell_range);
148}
149
150static void nbio_v7_2_enable_doorbell_aperture(struct amdgpu_device *adev,
151 bool enable)
152{
153 u32 reg;
154
155 reg = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN);
156 reg = REG_SET_FIELD(reg, RCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN,
157 BIF_DOORBELL_APER_EN, enable ? 1 : 0);
158
159 WREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN, reg);
160}
161
162static void nbio_v7_2_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
163 bool enable)
164{
165 u32 tmp = 0;
166
167 if (enable) {
168 tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
169 DOORBELL_SELFRING_GPA_APER_EN, 1) |
170 REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
171 DOORBELL_SELFRING_GPA_APER_MODE, 1) |
172 REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
173 DOORBELL_SELFRING_GPA_APER_SIZE, 0);
174
175 WREG32_SOC15(NBIO, 0,
176 regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW,
177 lower_32_bits(adev->doorbell.base));
178 WREG32_SOC15(NBIO, 0,
179 regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH,
180 upper_32_bits(adev->doorbell.base));
181 }
182
183 WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
184 tmp);
185}
186
187
188static void nbio_v7_2_ih_doorbell_range(struct amdgpu_device *adev,
189 bool use_doorbell, int doorbell_index)
190{
191 u32 ih_doorbell_range = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_IH_DOORBELL_RANGE));
192
193 if (use_doorbell) {
194 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
195 GDC0_BIF_IH_DOORBELL_RANGE, OFFSET,
196 doorbell_index);
197 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
198 GDC0_BIF_IH_DOORBELL_RANGE, SIZE,
199 2);
200 } else {
201 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
202 GDC0_BIF_IH_DOORBELL_RANGE, SIZE,
203 0);
204 }
205
206 WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_IH_DOORBELL_RANGE),
207 ih_doorbell_range);
208}
209
210static void nbio_v7_2_ih_control(struct amdgpu_device *adev)
211{
212 u32 interrupt_cntl;
213
214 /* setup interrupt control */
215 WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL2,
216 adev->dummy_page_addr >> 8);
217
218 interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL);
219 /*
220 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
221 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
222 */
223 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL,
224 IH_DUMMY_RD_OVERRIDE, 0);
225
226 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
227 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL,
228 IH_REQ_NONSNOOP_EN, 0);
229
230 WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL, interrupt_cntl);
231}
232
233static void nbio_v7_2_update_medium_grain_clock_gating(struct amdgpu_device *adev,
234 bool enable)
235{
236 uint32_t def, data;
237
238 def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regCPM_CONTROL));
239 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG)) {
240 data |= (CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK |
241 CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK |
242 CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK |
243 CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK |
244 CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK |
245 CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK);
246 } else {
247 data &= ~(CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK |
248 CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK |
249 CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK |
250 CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK |
251 CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK |
252 CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK);
253 }
254
255 if (def != data)
256 WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regCPM_CONTROL), data);
257}
258
259static void nbio_v7_2_update_medium_grain_light_sleep(struct amdgpu_device *adev,
260 bool enable)
261{
262 uint32_t def, data;
263
264 switch (amdgpu_ip_version(adev, ip: NBIO_HWIP, inst: 0)) {
265 case IP_VERSION(7, 2, 1):
266 case IP_VERSION(7, 3, 0):
267 case IP_VERSION(7, 5, 0):
268 def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2));
269 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
270 data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK;
271 else
272 data &= ~PCIE_CNTL2__SLV_MEM_LS_EN_MASK;
273
274 if (def != data)
275 WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2), data);
276
277 def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0,
278 regBIF1_PCIE_TX_POWER_CTRL_1));
279 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
280 data |= (BIF1_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK |
281 BIF1_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK);
282 else
283 data &= ~(BIF1_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK |
284 BIF1_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK);
285
286 if (def != data)
287 WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_TX_POWER_CTRL_1),
288 data);
289 break;
290 default:
291 def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2));
292 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
293 data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
294 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
295 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
296 else
297 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
298 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
299 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
300
301 if (def != data)
302 WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2), data);
303 break;
304 }
305}
306
307static void nbio_v7_2_get_clockgating_state(struct amdgpu_device *adev,
308 u64 *flags)
309{
310 int data;
311
312 /* AMD_CG_SUPPORT_BIF_MGCG */
313 data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regCPM_CONTROL));
314 if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK)
315 *flags |= AMD_CG_SUPPORT_BIF_MGCG;
316
317 /* AMD_CG_SUPPORT_BIF_LS */
318 data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2));
319 if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
320 *flags |= AMD_CG_SUPPORT_BIF_LS;
321}
322
323static u32 nbio_v7_2_get_hdp_flush_req_offset(struct amdgpu_device *adev)
324{
325 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_REQ);
326}
327
328static u32 nbio_v7_2_get_hdp_flush_done_offset(struct amdgpu_device *adev)
329{
330 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_DONE);
331}
332
333static u32 nbio_v7_2_get_pcie_index_offset(struct amdgpu_device *adev)
334{
335 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX2);
336}
337
338static u32 nbio_v7_2_get_pcie_data_offset(struct amdgpu_device *adev)
339{
340 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_DATA2);
341}
342
343static u32 nbio_v7_2_get_pcie_port_index_offset(struct amdgpu_device *adev)
344{
345 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_INDEX);
346}
347
348static u32 nbio_v7_2_get_pcie_port_data_offset(struct amdgpu_device *adev)
349{
350 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_DATA);
351}
352
353const struct nbio_hdp_flush_reg nbio_v7_2_hdp_flush_reg = {
354 .ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK,
355 .ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK,
356 .ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK,
357 .ref_and_mask_cp3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK,
358 .ref_and_mask_cp4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK,
359 .ref_and_mask_cp5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK,
360 .ref_and_mask_cp6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK,
361 .ref_and_mask_cp7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK,
362 .ref_and_mask_cp8 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK,
363 .ref_and_mask_cp9 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK,
364 .ref_and_mask_sdma0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK,
365 .ref_and_mask_sdma1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK,
366};
367
368static void nbio_v7_2_init_registers(struct amdgpu_device *adev)
369{
370 uint32_t def, data;
371 switch (amdgpu_ip_version(adev, ip: NBIO_HWIP, inst: 0)) {
372 case IP_VERSION(7, 2, 1):
373 case IP_VERSION(7, 3, 0):
374 case IP_VERSION(7, 5, 0):
375 def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_MST_CTRL_3));
376 data = REG_SET_FIELD(data, BIF1_PCIE_MST_CTRL_3,
377 CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);
378 data = REG_SET_FIELD(data, BIF1_PCIE_MST_CTRL_3,
379 CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);
380
381 if (def != data)
382 WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_MST_CTRL_3), data);
383 break;
384 default:
385 def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CONFIG_CNTL));
386 data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL,
387 CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);
388 data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL,
389 CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);
390
391 if (def != data)
392 WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CONFIG_CNTL), data);
393 break;
394 }
395
396 switch (amdgpu_ip_version(adev, ip: NBIO_HWIP, inst: 0)) {
397 case IP_VERSION(7, 3, 0):
398 case IP_VERSION(7, 5, 1):
399 data = RREG32_SOC15(NBIO, 0, regRCC_DEV2_EPF0_STRAP2);
400 data &= ~RCC_DEV2_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV2_F0_MASK;
401 WREG32_SOC15(NBIO, 0, regRCC_DEV2_EPF0_STRAP2, data);
402 break;
403 }
404}
405
406#define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
407
408static void nbio_v7_2_set_reg_remap(struct amdgpu_device *adev)
409{
410 if (!amdgpu_sriov_vf(adev) && (PAGE_SIZE <= 4096)) {
411 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
412 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
413 } else {
414 adev->rmmio_remap.reg_offset =
415 SOC15_REG_OFFSET(NBIO, 0,
416 regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2;
417 adev->rmmio_remap.bus_addr = 0;
418 }
419}
420
421const struct amdgpu_nbio_funcs nbio_v7_2_funcs = {
422 .get_hdp_flush_req_offset = nbio_v7_2_get_hdp_flush_req_offset,
423 .get_hdp_flush_done_offset = nbio_v7_2_get_hdp_flush_done_offset,
424 .get_pcie_index_offset = nbio_v7_2_get_pcie_index_offset,
425 .get_pcie_data_offset = nbio_v7_2_get_pcie_data_offset,
426 .get_pcie_port_index_offset = nbio_v7_2_get_pcie_port_index_offset,
427 .get_pcie_port_data_offset = nbio_v7_2_get_pcie_port_data_offset,
428 .get_rev_id = nbio_v7_2_get_rev_id,
429 .mc_access_enable = nbio_v7_2_mc_access_enable,
430 .get_memsize = nbio_v7_2_get_memsize,
431 .sdma_doorbell_range = nbio_v7_2_sdma_doorbell_range,
432 .vcn_doorbell_range = nbio_v7_2_vcn_doorbell_range,
433 .enable_doorbell_aperture = nbio_v7_2_enable_doorbell_aperture,
434 .enable_doorbell_selfring_aperture = nbio_v7_2_enable_doorbell_selfring_aperture,
435 .ih_doorbell_range = nbio_v7_2_ih_doorbell_range,
436 .update_medium_grain_clock_gating = nbio_v7_2_update_medium_grain_clock_gating,
437 .update_medium_grain_light_sleep = nbio_v7_2_update_medium_grain_light_sleep,
438 .get_clockgating_state = nbio_v7_2_get_clockgating_state,
439 .ih_control = nbio_v7_2_ih_control,
440 .init_registers = nbio_v7_2_init_registers,
441 .remap_hdp_registers = nbio_v7_2_remap_hdp_registers,
442 .set_reg_remap = nbio_v7_2_set_reg_remap,
443};
444

source code of linux/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c