1/*
2 * Copyright 2023 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef __MMSCH_V5_0_H__
25#define __MMSCH_V5_0_H__
26
27#include "amdgpu_vcn.h"
28
29#define MMSCH_VERSION_MAJOR 5
30#define MMSCH_VERSION_MINOR 0
31#define MMSCH_VERSION (MMSCH_VERSION_MAJOR << 16 | MMSCH_VERSION_MINOR)
32
33#define RB_ENABLED (1 << 0)
34#define RB4_ENABLED (1 << 1)
35
36#define MMSCH_VF_ENGINE_STATUS__PASS 0x1
37
38#define MMSCH_VF_MAILBOX_RESP__OK 0x1
39#define MMSCH_VF_MAILBOX_RESP__INCOMPLETE 0x2
40#define MMSCH_VF_MAILBOX_RESP__FAILED 0x3
41#define MMSCH_VF_MAILBOX_RESP__FAILED_SMALL_CTX_SIZE 0x4
42#define MMSCH_VF_MAILBOX_RESP__UNKNOWN_CMD 0x5
43
44enum mmsch_v5_0_command_type {
45 MMSCH_COMMAND__DIRECT_REG_WRITE = 0,
46 MMSCH_COMMAND__DIRECT_REG_POLLING = 2,
47 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE = 3,
48 MMSCH_COMMAND__INDIRECT_REG_WRITE = 8,
49 MMSCH_COMMAND__END = 0xf
50};
51
52struct mmsch_v5_0_table_info {
53 uint32_t init_status;
54 uint32_t table_offset;
55 uint32_t table_size;
56};
57
58struct mmsch_v5_0_init_header {
59 uint32_t version;
60 uint32_t total_size;
61 struct mmsch_v5_0_table_info vcn0;
62 struct mmsch_v5_0_table_info mjpegdec0[5];
63 struct mmsch_v5_0_table_info mjpegdec1[5];
64};
65
66struct mmsch_v5_0_cmd_direct_reg_header {
67 uint32_t reg_offset : 28;
68 uint32_t command_type : 4;
69};
70
71struct mmsch_v5_0_cmd_indirect_reg_header {
72 uint32_t reg_offset : 20;
73 uint32_t reg_idx_space : 8;
74 uint32_t command_type : 4;
75};
76
77struct mmsch_v5_0_cmd_direct_write {
78 struct mmsch_v5_0_cmd_direct_reg_header cmd_header;
79 uint32_t reg_value;
80};
81
82struct mmsch_v5_0_cmd_direct_read_modify_write {
83 struct mmsch_v5_0_cmd_direct_reg_header cmd_header;
84 uint32_t write_data;
85 uint32_t mask_value;
86};
87
88struct mmsch_v5_0_cmd_direct_polling {
89 struct mmsch_v5_0_cmd_direct_reg_header cmd_header;
90 uint32_t mask_value;
91 uint32_t wait_value;
92};
93
94struct mmsch_v5_0_cmd_end {
95 struct mmsch_v5_0_cmd_direct_reg_header cmd_header;
96};
97
98struct mmsch_v5_0_cmd_indirect_write {
99 struct mmsch_v5_0_cmd_indirect_reg_header cmd_header;
100 uint32_t reg_value;
101};
102
103#define MMSCH_V5_0_INSERT_DIRECT_RD_MOD_WT(reg, mask, data) { \
104 size = sizeof(struct mmsch_v5_0_cmd_direct_read_modify_write); \
105 size_dw = size / 4; \
106 direct_rd_mod_wt.cmd_header.reg_offset = reg; \
107 direct_rd_mod_wt.mask_value = mask; \
108 direct_rd_mod_wt.write_data = data; \
109 memcpy((void *)table_loc, &direct_rd_mod_wt, size); \
110 table_loc += size_dw; \
111 table_size += size_dw; \
112}
113
114#define MMSCH_V5_0_INSERT_DIRECT_WT(reg, value) { \
115 size = sizeof(struct mmsch_v5_0_cmd_direct_write); \
116 size_dw = size / 4; \
117 direct_wt.cmd_header.reg_offset = reg; \
118 direct_wt.reg_value = value; \
119 memcpy((void *)table_loc, &direct_wt, size); \
120 table_loc += size_dw; \
121 table_size += size_dw; \
122}
123
124#define MMSCH_V5_0_INSERT_DIRECT_POLL(reg, mask, wait) { \
125 size = sizeof(struct mmsch_v5_0_cmd_direct_polling); \
126 size_dw = size / 4; \
127 direct_poll.cmd_header.reg_offset = reg; \
128 direct_poll.mask_value = mask; \
129 direct_poll.wait_value = wait; \
130 memcpy((void *)table_loc, &direct_poll, size); \
131 table_loc += size_dw; \
132 table_size += size_dw; \
133}
134
135#define MMSCH_V5_0_INSERT_END() { \
136 size = sizeof(struct mmsch_v5_0_cmd_end); \
137 size_dw = size / 4; \
138 memcpy((void *)table_loc, &end, size); \
139 table_loc += size_dw; \
140 table_size += size_dw; \
141}
142
143#endif
144
145

source code of linux/drivers/gpu/drm/amd/amdgpu/mmsch_v5_0.h