1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include "amdgpu.h"
25#include "amdgpu_jpeg.h"
26#include "soc15.h"
27#include "soc15d.h"
28#include "jpeg_v2_0.h"
29#include "jpeg_v2_5.h"
30
31#include "vcn/vcn_2_5_offset.h"
32#include "vcn/vcn_2_5_sh_mask.h"
33#include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"
34
35#define mmUVD_JPEG_PITCH_INTERNAL_OFFSET 0x401f
36
37#define JPEG25_MAX_HW_INSTANCES_ARCTURUS 2
38
39static const struct amdgpu_hwip_reg_entry jpeg_reg_list_2_5[] = {
40 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_POWER_STATUS),
41 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_INT_STAT),
42 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_RPTR),
43 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_WPTR),
44 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_CNTL),
45 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_SIZE),
46 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_STATUS),
47 SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_ADDR_MODE),
48 SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG),
49 SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_Y_GFX10_TILING_SURFACE),
50 SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_UV_GFX10_TILING_SURFACE),
51 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_PITCH),
52 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_UV_PITCH),
53};
54
55static void jpeg_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev);
56static void jpeg_v2_5_set_irq_funcs(struct amdgpu_device *adev);
57static int jpeg_v2_5_set_powergating_state(struct amdgpu_ip_block *ip_block,
58 enum amd_powergating_state state);
59static void jpeg_v2_5_set_ras_funcs(struct amdgpu_device *adev);
60
61static int amdgpu_ih_clientid_jpeg[] = {
62 SOC15_IH_CLIENTID_VCN,
63 SOC15_IH_CLIENTID_VCN1
64};
65
66/**
67 * jpeg_v2_5_early_init - set function pointers
68 *
69 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
70 *
71 * Set ring and irq function pointers
72 */
73static int jpeg_v2_5_early_init(struct amdgpu_ip_block *ip_block)
74{
75 struct amdgpu_device *adev = ip_block->adev;
76 u32 harvest;
77 int i;
78
79 adev->jpeg.num_jpeg_rings = 1;
80 adev->jpeg.num_jpeg_inst = JPEG25_MAX_HW_INSTANCES_ARCTURUS;
81 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
82 harvest = RREG32_SOC15(JPEG, i, mmCC_UVD_HARVESTING);
83 if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK)
84 adev->jpeg.harvest_config |= 1 << i;
85 }
86 if (adev->jpeg.harvest_config == (AMDGPU_JPEG_HARVEST_JPEG0 |
87 AMDGPU_JPEG_HARVEST_JPEG1))
88 return -ENOENT;
89
90 jpeg_v2_5_set_dec_ring_funcs(adev);
91 jpeg_v2_5_set_irq_funcs(adev);
92 jpeg_v2_5_set_ras_funcs(adev);
93
94 return 0;
95}
96
97/**
98 * jpeg_v2_5_sw_init - sw init for JPEG block
99 *
100 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
101 *
102 * Load firmware and sw initialization
103 */
104static int jpeg_v2_5_sw_init(struct amdgpu_ip_block *ip_block)
105{
106 struct amdgpu_ring *ring;
107 int i, r;
108 struct amdgpu_device *adev = ip_block->adev;
109
110 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
111 if (adev->jpeg.harvest_config & (1 << i))
112 continue;
113
114 /* JPEG TRAP */
115 r = amdgpu_irq_add_id(adev, client_id: amdgpu_ih_clientid_jpeg[i],
116 VCN_2_0__SRCID__JPEG_DECODE, source: &adev->jpeg.inst[i].irq);
117 if (r)
118 return r;
119
120 /* JPEG DJPEG POISON EVENT */
121 r = amdgpu_irq_add_id(adev, client_id: amdgpu_ih_clientid_jpeg[i],
122 VCN_2_6__SRCID_DJPEG0_POISON, source: &adev->jpeg.inst[i].ras_poison_irq);
123 if (r)
124 return r;
125
126 /* JPEG EJPEG POISON EVENT */
127 r = amdgpu_irq_add_id(adev, client_id: amdgpu_ih_clientid_jpeg[i],
128 VCN_2_6__SRCID_EJPEG0_POISON, source: &adev->jpeg.inst[i].ras_poison_irq);
129 if (r)
130 return r;
131 }
132
133 r = amdgpu_jpeg_sw_init(adev);
134 if (r)
135 return r;
136
137 r = amdgpu_jpeg_resume(adev);
138 if (r)
139 return r;
140
141 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
142 if (adev->jpeg.harvest_config & (1 << i))
143 continue;
144
145 ring = adev->jpeg.inst[i].ring_dec;
146 ring->use_doorbell = true;
147 if (amdgpu_ip_version(adev, ip: UVD_HWIP, inst: 0) == IP_VERSION(2, 5, 0))
148 ring->vm_hub = AMDGPU_MMHUB1(0);
149 else
150 ring->vm_hub = AMDGPU_MMHUB0(0);
151 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1 + 8 * i;
152 sprintf(buf: ring->name, fmt: "jpeg_dec_%d", i);
153 r = amdgpu_ring_init(adev, ring, max_dw: 512, irq_src: &adev->jpeg.inst[i].irq,
154 irq_type: 0, hw_prio: AMDGPU_RING_PRIO_DEFAULT, NULL);
155 if (r)
156 return r;
157
158 adev->jpeg.internal.jpeg_pitch[0] = mmUVD_JPEG_PITCH_INTERNAL_OFFSET;
159 adev->jpeg.inst[i].external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_PITCH);
160 }
161
162 r = amdgpu_jpeg_ras_sw_init(adev);
163 if (r)
164 return r;
165
166 r = amdgpu_jpeg_reg_dump_init(adev, reg: jpeg_reg_list_2_5, ARRAY_SIZE(jpeg_reg_list_2_5));
167 if (r)
168 return r;
169
170 adev->jpeg.supported_reset =
171 amdgpu_get_soft_full_reset_mask(ring: adev->jpeg.inst[0].ring_dec);
172 if (!amdgpu_sriov_vf(adev))
173 adev->jpeg.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;
174 r = amdgpu_jpeg_sysfs_reset_mask_init(adev);
175
176 return r;
177}
178
179/**
180 * jpeg_v2_5_sw_fini - sw fini for JPEG block
181 *
182 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
183 *
184 * JPEG suspend and free up sw allocation
185 */
186static int jpeg_v2_5_sw_fini(struct amdgpu_ip_block *ip_block)
187{
188 int r;
189 struct amdgpu_device *adev = ip_block->adev;
190
191 r = amdgpu_jpeg_suspend(adev);
192 if (r)
193 return r;
194
195 amdgpu_jpeg_sysfs_reset_mask_fini(adev);
196
197 r = amdgpu_jpeg_sw_fini(adev);
198
199 return r;
200}
201
202/**
203 * jpeg_v2_5_hw_init - start and test JPEG block
204 *
205 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
206 *
207 */
208static int jpeg_v2_5_hw_init(struct amdgpu_ip_block *ip_block)
209{
210 struct amdgpu_device *adev = ip_block->adev;
211 struct amdgpu_ring *ring;
212 int i, r;
213
214 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
215 if (adev->jpeg.harvest_config & (1 << i))
216 continue;
217
218 ring = adev->jpeg.inst[i].ring_dec;
219 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
220 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i, i);
221
222 r = amdgpu_ring_test_helper(ring);
223 if (r)
224 return r;
225 }
226
227 return 0;
228}
229
230/**
231 * jpeg_v2_5_hw_fini - stop the hardware block
232 *
233 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
234 *
235 * Stop the JPEG block, mark ring as not ready any more
236 */
237static int jpeg_v2_5_hw_fini(struct amdgpu_ip_block *ip_block)
238{
239 struct amdgpu_device *adev = ip_block->adev;
240 int i;
241
242 cancel_delayed_work_sync(dwork: &adev->jpeg.idle_work);
243
244 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
245 if (adev->jpeg.harvest_config & (1 << i))
246 continue;
247
248 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
249 RREG32_SOC15(JPEG, i, mmUVD_JRBC_STATUS))
250 jpeg_v2_5_set_powergating_state(ip_block, state: AMD_PG_STATE_GATE);
251
252 if (amdgpu_ras_is_supported(adev, block: AMDGPU_RAS_BLOCK__JPEG))
253 amdgpu_irq_put(adev, src: &adev->jpeg.inst[i].ras_poison_irq, type: 0);
254 }
255
256 return 0;
257}
258
259/**
260 * jpeg_v2_5_suspend - suspend JPEG block
261 *
262 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
263 *
264 * HW fini and suspend JPEG block
265 */
266static int jpeg_v2_5_suspend(struct amdgpu_ip_block *ip_block)
267{
268 int r;
269
270 r = jpeg_v2_5_hw_fini(ip_block);
271 if (r)
272 return r;
273
274 r = amdgpu_jpeg_suspend(adev: ip_block->adev);
275
276 return r;
277}
278
279/**
280 * jpeg_v2_5_resume - resume JPEG block
281 *
282 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
283 *
284 * Resume firmware and hw init JPEG block
285 */
286static int jpeg_v2_5_resume(struct amdgpu_ip_block *ip_block)
287{
288 int r;
289
290 r = amdgpu_jpeg_resume(adev: ip_block->adev);
291 if (r)
292 return r;
293
294 r = jpeg_v2_5_hw_init(ip_block);
295
296 return r;
297}
298
299static void jpeg_v2_5_disable_clock_gating(struct amdgpu_device *adev, int inst)
300{
301 uint32_t data;
302
303 data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL);
304 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG)
305 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
306 else
307 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
308
309 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
310 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
311 WREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL, data);
312
313 data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE);
314 data &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK
315 | JPEG_CGC_GATE__JPEG2_DEC_MASK
316 | JPEG_CGC_GATE__JMCIF_MASK
317 | JPEG_CGC_GATE__JRBBM_MASK);
318 WREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE, data);
319
320 data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL);
321 data &= ~(JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK
322 | JPEG_CGC_CTRL__JPEG2_DEC_MODE_MASK
323 | JPEG_CGC_CTRL__JMCIF_MODE_MASK
324 | JPEG_CGC_CTRL__JRBBM_MODE_MASK);
325 WREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL, data);
326}
327
328static void jpeg_v2_5_enable_clock_gating(struct amdgpu_device *adev, int inst)
329{
330 uint32_t data;
331
332 data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE);
333 data |= (JPEG_CGC_GATE__JPEG_DEC_MASK
334 |JPEG_CGC_GATE__JPEG2_DEC_MASK
335 |JPEG_CGC_GATE__JPEG_ENC_MASK
336 |JPEG_CGC_GATE__JMCIF_MASK
337 |JPEG_CGC_GATE__JRBBM_MASK);
338 WREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE, data);
339}
340
341static void jpeg_v2_5_start_inst(struct amdgpu_device *adev, int i)
342{
343 struct amdgpu_ring *ring = adev->jpeg.inst[i].ring_dec;
344 /* disable anti hang mechanism */
345 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_POWER_STATUS), 0,
346 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
347
348 /* JPEG disable CGC */
349 jpeg_v2_5_disable_clock_gating(adev, inst: i);
350
351 /* MJPEG global tiling registers */
352 WREG32_SOC15(JPEG, i, mmJPEG_DEC_GFX8_ADDR_CONFIG,
353 adev->gfx.config.gb_addr_config);
354 WREG32_SOC15(JPEG, i, mmJPEG_DEC_GFX10_ADDR_CONFIG,
355 adev->gfx.config.gb_addr_config);
356
357 /* enable JMI channel */
358 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JMI_CNTL), 0,
359 ~UVD_JMI_CNTL__SOFT_RESET_MASK);
360
361 /* enable System Interrupt for JRBC */
362 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmJPEG_SYS_INT_EN),
363 JPEG_SYS_INT_EN__DJRBC_MASK,
364 ~JPEG_SYS_INT_EN__DJRBC_MASK);
365
366 WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_VMID, 0);
367 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));
368 WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
369 lower_32_bits(ring->gpu_addr));
370 WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
371 upper_32_bits(ring->gpu_addr));
372 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_RPTR, 0);
373 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_WPTR, 0);
374 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_CNTL, 0x00000002L);
375 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4);
376 ring->wptr = RREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_WPTR);
377}
378
379/**
380 * jpeg_v2_5_start - start JPEG block
381 *
382 * @adev: amdgpu_device pointer
383 *
384 * Setup and start the JPEG block
385 */
386static int jpeg_v2_5_start(struct amdgpu_device *adev)
387{
388 int i;
389
390 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
391 if (adev->jpeg.harvest_config & (1 << i))
392 continue;
393 jpeg_v2_5_start_inst(adev, i);
394
395 }
396
397 return 0;
398}
399
400static void jpeg_v2_5_stop_inst(struct amdgpu_device *adev, int i)
401{
402 /* reset JMI */
403 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JMI_CNTL),
404 UVD_JMI_CNTL__SOFT_RESET_MASK,
405 ~UVD_JMI_CNTL__SOFT_RESET_MASK);
406
407 jpeg_v2_5_enable_clock_gating(adev, inst: i);
408
409 /* enable anti hang mechanism */
410 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_POWER_STATUS),
411 UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK,
412 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
413}
414
415/**
416 * jpeg_v2_5_stop - stop JPEG block
417 *
418 * @adev: amdgpu_device pointer
419 *
420 * stop the JPEG block
421 */
422static int jpeg_v2_5_stop(struct amdgpu_device *adev)
423{
424 int i;
425
426 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
427 if (adev->jpeg.harvest_config & (1 << i))
428 continue;
429 jpeg_v2_5_stop_inst(adev, i);
430 }
431
432 return 0;
433}
434
435/**
436 * jpeg_v2_5_dec_ring_get_rptr - get read pointer
437 *
438 * @ring: amdgpu_ring pointer
439 *
440 * Returns the current hardware read pointer
441 */
442static uint64_t jpeg_v2_5_dec_ring_get_rptr(struct amdgpu_ring *ring)
443{
444 struct amdgpu_device *adev = ring->adev;
445
446 return RREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_RPTR);
447}
448
449/**
450 * jpeg_v2_5_dec_ring_get_wptr - get write pointer
451 *
452 * @ring: amdgpu_ring pointer
453 *
454 * Returns the current hardware write pointer
455 */
456static uint64_t jpeg_v2_5_dec_ring_get_wptr(struct amdgpu_ring *ring)
457{
458 struct amdgpu_device *adev = ring->adev;
459
460 if (ring->use_doorbell)
461 return *ring->wptr_cpu_addr;
462 else
463 return RREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_WPTR);
464}
465
466/**
467 * jpeg_v2_5_dec_ring_set_wptr - set write pointer
468 *
469 * @ring: amdgpu_ring pointer
470 *
471 * Commits the write pointer to the hardware
472 */
473static void jpeg_v2_5_dec_ring_set_wptr(struct amdgpu_ring *ring)
474{
475 struct amdgpu_device *adev = ring->adev;
476
477 if (ring->use_doorbell) {
478 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
479 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
480 } else {
481 WREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
482 }
483}
484
485/**
486 * jpeg_v2_6_dec_ring_insert_start - insert a start command
487 *
488 * @ring: amdgpu_ring pointer
489 *
490 * Write a start command to the ring.
491 */
492static void jpeg_v2_6_dec_ring_insert_start(struct amdgpu_ring *ring)
493{
494 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
495 0, 0, PACKETJ_TYPE0));
496 amdgpu_ring_write(ring, v: 0x6aa04); /* PCTL0_MMHUB_DEEPSLEEP_IB */
497
498 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
499 0, 0, PACKETJ_TYPE0));
500 amdgpu_ring_write(ring, v: 0x80000000 | (1 << (ring->me * 2 + 14)));
501}
502
503/**
504 * jpeg_v2_6_dec_ring_insert_end - insert a end command
505 *
506 * @ring: amdgpu_ring pointer
507 *
508 * Write a end command to the ring.
509 */
510static void jpeg_v2_6_dec_ring_insert_end(struct amdgpu_ring *ring)
511{
512 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
513 0, 0, PACKETJ_TYPE0));
514 amdgpu_ring_write(ring, v: 0x6aa04); /* PCTL0_MMHUB_DEEPSLEEP_IB */
515
516 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
517 0, 0, PACKETJ_TYPE0));
518 amdgpu_ring_write(ring, v: (1 << (ring->me * 2 + 14)));
519}
520
521static bool jpeg_v2_5_is_idle(struct amdgpu_ip_block *ip_block)
522{
523 struct amdgpu_device *adev = ip_block->adev;
524 int i, ret = 1;
525
526 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
527 if (adev->jpeg.harvest_config & (1 << i))
528 continue;
529
530 ret &= (((RREG32_SOC15(JPEG, i, mmUVD_JRBC_STATUS) &
531 UVD_JRBC_STATUS__RB_JOB_DONE_MASK) ==
532 UVD_JRBC_STATUS__RB_JOB_DONE_MASK));
533 }
534
535 return ret;
536}
537
538static int jpeg_v2_5_wait_for_idle(struct amdgpu_ip_block *ip_block)
539{
540 struct amdgpu_device *adev = ip_block->adev;
541 int i, ret;
542
543 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
544 if (adev->jpeg.harvest_config & (1 << i))
545 continue;
546
547 ret = SOC15_WAIT_ON_RREG(JPEG, i, mmUVD_JRBC_STATUS,
548 UVD_JRBC_STATUS__RB_JOB_DONE_MASK,
549 UVD_JRBC_STATUS__RB_JOB_DONE_MASK);
550 if (ret)
551 return ret;
552 }
553
554 return 0;
555}
556
557static int jpeg_v2_5_set_clockgating_state(struct amdgpu_ip_block *ip_block,
558 enum amd_clockgating_state state)
559{
560 struct amdgpu_device *adev = ip_block->adev;
561 bool enable = (state == AMD_CG_STATE_GATE);
562 int i;
563
564 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
565 if (adev->jpeg.harvest_config & (1 << i))
566 continue;
567
568 if (enable) {
569 if (!jpeg_v2_5_is_idle(ip_block))
570 return -EBUSY;
571 jpeg_v2_5_enable_clock_gating(adev, inst: i);
572 } else {
573 jpeg_v2_5_disable_clock_gating(adev, inst: i);
574 }
575 }
576
577 return 0;
578}
579
580static int jpeg_v2_5_set_powergating_state(struct amdgpu_ip_block *ip_block,
581 enum amd_powergating_state state)
582{
583 struct amdgpu_device *adev = ip_block->adev;
584 int ret;
585
586 if (state == adev->jpeg.cur_state)
587 return 0;
588
589 if (state == AMD_PG_STATE_GATE)
590 ret = jpeg_v2_5_stop(adev);
591 else
592 ret = jpeg_v2_5_start(adev);
593
594 if (!ret)
595 adev->jpeg.cur_state = state;
596
597 return ret;
598}
599
600static int jpeg_v2_5_set_interrupt_state(struct amdgpu_device *adev,
601 struct amdgpu_irq_src *source,
602 unsigned type,
603 enum amdgpu_interrupt_state state)
604{
605 return 0;
606}
607
608static int jpeg_v2_6_set_ras_interrupt_state(struct amdgpu_device *adev,
609 struct amdgpu_irq_src *source,
610 unsigned int type,
611 enum amdgpu_interrupt_state state)
612{
613 return 0;
614}
615
616static int jpeg_v2_5_process_interrupt(struct amdgpu_device *adev,
617 struct amdgpu_irq_src *source,
618 struct amdgpu_iv_entry *entry)
619{
620 uint32_t ip_instance;
621
622 switch (entry->client_id) {
623 case SOC15_IH_CLIENTID_VCN:
624 ip_instance = 0;
625 break;
626 case SOC15_IH_CLIENTID_VCN1:
627 ip_instance = 1;
628 break;
629 default:
630 DRM_ERROR("Unhandled client id: %d\n", entry->client_id);
631 return 0;
632 }
633
634 DRM_DEBUG("IH: JPEG TRAP\n");
635
636 switch (entry->src_id) {
637 case VCN_2_0__SRCID__JPEG_DECODE:
638 amdgpu_fence_process(ring: adev->jpeg.inst[ip_instance].ring_dec);
639 break;
640 default:
641 DRM_ERROR("Unhandled interrupt: %d %d\n",
642 entry->src_id, entry->src_data[0]);
643 break;
644 }
645
646 return 0;
647}
648
649static int jpeg_v2_5_ring_reset(struct amdgpu_ring *ring,
650 unsigned int vmid,
651 struct amdgpu_fence *timedout_fence)
652{
653 amdgpu_ring_reset_helper_begin(ring, guilty_fence: timedout_fence);
654 jpeg_v2_5_stop_inst(adev: ring->adev, i: ring->me);
655 jpeg_v2_5_start_inst(adev: ring->adev, i: ring->me);
656 return amdgpu_ring_reset_helper_end(ring, guilty_fence: timedout_fence);
657}
658
659static const struct amd_ip_funcs jpeg_v2_5_ip_funcs = {
660 .name = "jpeg_v2_5",
661 .early_init = jpeg_v2_5_early_init,
662 .sw_init = jpeg_v2_5_sw_init,
663 .sw_fini = jpeg_v2_5_sw_fini,
664 .hw_init = jpeg_v2_5_hw_init,
665 .hw_fini = jpeg_v2_5_hw_fini,
666 .suspend = jpeg_v2_5_suspend,
667 .resume = jpeg_v2_5_resume,
668 .is_idle = jpeg_v2_5_is_idle,
669 .wait_for_idle = jpeg_v2_5_wait_for_idle,
670 .set_clockgating_state = jpeg_v2_5_set_clockgating_state,
671 .set_powergating_state = jpeg_v2_5_set_powergating_state,
672 .dump_ip_state = amdgpu_jpeg_dump_ip_state,
673 .print_ip_state = amdgpu_jpeg_print_ip_state,
674};
675
676static const struct amd_ip_funcs jpeg_v2_6_ip_funcs = {
677 .name = "jpeg_v2_6",
678 .early_init = jpeg_v2_5_early_init,
679 .sw_init = jpeg_v2_5_sw_init,
680 .sw_fini = jpeg_v2_5_sw_fini,
681 .hw_init = jpeg_v2_5_hw_init,
682 .hw_fini = jpeg_v2_5_hw_fini,
683 .suspend = jpeg_v2_5_suspend,
684 .resume = jpeg_v2_5_resume,
685 .is_idle = jpeg_v2_5_is_idle,
686 .wait_for_idle = jpeg_v2_5_wait_for_idle,
687 .set_clockgating_state = jpeg_v2_5_set_clockgating_state,
688 .set_powergating_state = jpeg_v2_5_set_powergating_state,
689 .dump_ip_state = amdgpu_jpeg_dump_ip_state,
690 .print_ip_state = amdgpu_jpeg_print_ip_state,
691};
692
693static const struct amdgpu_ring_funcs jpeg_v2_5_dec_ring_vm_funcs = {
694 .type = AMDGPU_RING_TYPE_VCN_JPEG,
695 .align_mask = 0xf,
696 .get_rptr = jpeg_v2_5_dec_ring_get_rptr,
697 .get_wptr = jpeg_v2_5_dec_ring_get_wptr,
698 .set_wptr = jpeg_v2_5_dec_ring_set_wptr,
699 .parse_cs = amdgpu_jpeg_dec_parse_cs,
700 .emit_frame_size =
701 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
702 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
703 8 + /* jpeg_v2_5_dec_ring_emit_vm_flush */
704 18 + 18 + /* jpeg_v2_5_dec_ring_emit_fence x2 vm fence */
705 8 + 16,
706 .emit_ib_size = 22, /* jpeg_v2_5_dec_ring_emit_ib */
707 .emit_ib = jpeg_v2_0_dec_ring_emit_ib,
708 .emit_fence = jpeg_v2_0_dec_ring_emit_fence,
709 .emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush,
710 .test_ring = amdgpu_jpeg_dec_ring_test_ring,
711 .test_ib = amdgpu_jpeg_dec_ring_test_ib,
712 .insert_nop = jpeg_v2_0_dec_ring_nop,
713 .insert_start = jpeg_v2_0_dec_ring_insert_start,
714 .insert_end = jpeg_v2_0_dec_ring_insert_end,
715 .pad_ib = amdgpu_ring_generic_pad_ib,
716 .begin_use = amdgpu_jpeg_ring_begin_use,
717 .end_use = amdgpu_jpeg_ring_end_use,
718 .emit_wreg = jpeg_v2_0_dec_ring_emit_wreg,
719 .emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait,
720 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
721 .reset = jpeg_v2_5_ring_reset,
722};
723
724static const struct amdgpu_ring_funcs jpeg_v2_6_dec_ring_vm_funcs = {
725 .type = AMDGPU_RING_TYPE_VCN_JPEG,
726 .align_mask = 0xf,
727 .get_rptr = jpeg_v2_5_dec_ring_get_rptr,
728 .get_wptr = jpeg_v2_5_dec_ring_get_wptr,
729 .set_wptr = jpeg_v2_5_dec_ring_set_wptr,
730 .parse_cs = amdgpu_jpeg_dec_parse_cs,
731 .emit_frame_size =
732 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
733 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
734 8 + /* jpeg_v2_5_dec_ring_emit_vm_flush */
735 18 + 18 + /* jpeg_v2_5_dec_ring_emit_fence x2 vm fence */
736 8 + 16,
737 .emit_ib_size = 22, /* jpeg_v2_5_dec_ring_emit_ib */
738 .emit_ib = jpeg_v2_0_dec_ring_emit_ib,
739 .emit_fence = jpeg_v2_0_dec_ring_emit_fence,
740 .emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush,
741 .test_ring = amdgpu_jpeg_dec_ring_test_ring,
742 .test_ib = amdgpu_jpeg_dec_ring_test_ib,
743 .insert_nop = jpeg_v2_0_dec_ring_nop,
744 .insert_start = jpeg_v2_6_dec_ring_insert_start,
745 .insert_end = jpeg_v2_6_dec_ring_insert_end,
746 .pad_ib = amdgpu_ring_generic_pad_ib,
747 .begin_use = amdgpu_jpeg_ring_begin_use,
748 .end_use = amdgpu_jpeg_ring_end_use,
749 .emit_wreg = jpeg_v2_0_dec_ring_emit_wreg,
750 .emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait,
751 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
752 .reset = jpeg_v2_5_ring_reset,
753};
754
755static void jpeg_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev)
756{
757 int i;
758
759 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
760 if (adev->jpeg.harvest_config & (1 << i))
761 continue;
762 if (adev->asic_type == CHIP_ARCTURUS)
763 adev->jpeg.inst[i].ring_dec->funcs = &jpeg_v2_5_dec_ring_vm_funcs;
764 else /* CHIP_ALDEBARAN */
765 adev->jpeg.inst[i].ring_dec->funcs = &jpeg_v2_6_dec_ring_vm_funcs;
766 adev->jpeg.inst[i].ring_dec->me = i;
767 }
768}
769
770static const struct amdgpu_irq_src_funcs jpeg_v2_5_irq_funcs = {
771 .set = jpeg_v2_5_set_interrupt_state,
772 .process = jpeg_v2_5_process_interrupt,
773};
774
775static const struct amdgpu_irq_src_funcs jpeg_v2_6_ras_irq_funcs = {
776 .set = jpeg_v2_6_set_ras_interrupt_state,
777 .process = amdgpu_jpeg_process_poison_irq,
778};
779
780static void jpeg_v2_5_set_irq_funcs(struct amdgpu_device *adev)
781{
782 int i;
783
784 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
785 if (adev->jpeg.harvest_config & (1 << i))
786 continue;
787
788 adev->jpeg.inst[i].irq.num_types = 1;
789 adev->jpeg.inst[i].irq.funcs = &jpeg_v2_5_irq_funcs;
790
791 adev->jpeg.inst[i].ras_poison_irq.num_types = 1;
792 adev->jpeg.inst[i].ras_poison_irq.funcs = &jpeg_v2_6_ras_irq_funcs;
793 }
794}
795
796const struct amdgpu_ip_block_version jpeg_v2_5_ip_block = {
797 .type = AMD_IP_BLOCK_TYPE_JPEG,
798 .major = 2,
799 .minor = 5,
800 .rev = 0,
801 .funcs = &jpeg_v2_5_ip_funcs,
802};
803
804const struct amdgpu_ip_block_version jpeg_v2_6_ip_block = {
805 .type = AMD_IP_BLOCK_TYPE_JPEG,
806 .major = 2,
807 .minor = 6,
808 .rev = 0,
809 .funcs = &jpeg_v2_6_ip_funcs,
810};
811
812static uint32_t jpeg_v2_6_query_poison_by_instance(struct amdgpu_device *adev,
813 uint32_t instance, uint32_t sub_block)
814{
815 uint32_t poison_stat = 0, reg_value = 0;
816
817 switch (sub_block) {
818 case AMDGPU_JPEG_V2_6_JPEG0:
819 reg_value = RREG32_SOC15(JPEG, instance, mmUVD_RAS_JPEG0_STATUS);
820 poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_JPEG0_STATUS, POISONED_PF);
821 break;
822 case AMDGPU_JPEG_V2_6_JPEG1:
823 reg_value = RREG32_SOC15(JPEG, instance, mmUVD_RAS_JPEG1_STATUS);
824 poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_JPEG1_STATUS, POISONED_PF);
825 break;
826 default:
827 break;
828 }
829
830 if (poison_stat)
831 dev_info(adev->dev, "Poison detected in JPEG%d sub_block%d\n",
832 instance, sub_block);
833
834 return poison_stat;
835}
836
837static bool jpeg_v2_6_query_ras_poison_status(struct amdgpu_device *adev)
838{
839 uint32_t inst = 0, sub = 0, poison_stat = 0;
840
841 for (inst = 0; inst < adev->jpeg.num_jpeg_inst; inst++)
842 for (sub = 0; sub < AMDGPU_JPEG_V2_6_MAX_SUB_BLOCK; sub++)
843 poison_stat +=
844 jpeg_v2_6_query_poison_by_instance(adev, instance: inst, sub_block: sub);
845
846 return !!poison_stat;
847}
848
849const struct amdgpu_ras_block_hw_ops jpeg_v2_6_ras_hw_ops = {
850 .query_poison_status = jpeg_v2_6_query_ras_poison_status,
851};
852
853static struct amdgpu_jpeg_ras jpeg_v2_6_ras = {
854 .ras_block = {
855 .hw_ops = &jpeg_v2_6_ras_hw_ops,
856 .ras_late_init = amdgpu_jpeg_ras_late_init,
857 },
858};
859
860static void jpeg_v2_5_set_ras_funcs(struct amdgpu_device *adev)
861{
862 switch (amdgpu_ip_version(adev, ip: JPEG_HWIP, inst: 0)) {
863 case IP_VERSION(2, 6, 0):
864 adev->jpeg.ras = &jpeg_v2_6_ras;
865 break;
866 default:
867 break;
868 }
869}
870

source code of linux/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c