| 1 | /* SPDX-License-Identifier: MIT */ |
| 2 | /* |
| 3 | * Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved. |
| 4 | * All Rights Reserved. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the |
| 8 | * "Software"), to deal in the Software without restriction, including |
| 9 | * without limitation the rights to use, copy, modify, merge, publish, |
| 10 | * distribute, sub license, and/or sell copies of the Software, and to |
| 11 | * permit persons to whom the Software is furnished to do so, subject to |
| 12 | * the following conditions: |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, |
| 18 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR |
| 19 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE |
| 20 | * USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | * The above copyright notice and this permission notice (including the |
| 23 | * next paragraph) shall be included in all copies or substantial portions |
| 24 | * of the Software. |
| 25 | * |
| 26 | */ |
| 27 | |
| 28 | #include "amdgpu.h" |
| 29 | #include "isp_v4_1_0.h" |
| 30 | |
| 31 | static const unsigned int isp_4_1_0_int_srcid[MAX_ISP410_INT_SRC] = { |
| 32 | ISP_4_1__SRCID__ISP_RINGBUFFER_WPT9, |
| 33 | ISP_4_1__SRCID__ISP_RINGBUFFER_WPT10, |
| 34 | ISP_4_1__SRCID__ISP_RINGBUFFER_WPT11, |
| 35 | ISP_4_1__SRCID__ISP_RINGBUFFER_WPT12, |
| 36 | ISP_4_1__SRCID__ISP_RINGBUFFER_WPT13, |
| 37 | ISP_4_1__SRCID__ISP_RINGBUFFER_WPT14, |
| 38 | ISP_4_1__SRCID__ISP_RINGBUFFER_WPT15, |
| 39 | ISP_4_1__SRCID__ISP_RINGBUFFER_WPT16 |
| 40 | }; |
| 41 | |
| 42 | static int isp_v4_1_0_hw_init(struct amdgpu_isp *isp) |
| 43 | { |
| 44 | struct amdgpu_device *adev = isp->adev; |
| 45 | int idx, int_idx, num_res, r; |
| 46 | u64 isp_base; |
| 47 | |
| 48 | if (adev->rmmio_size == 0 || adev->rmmio_size < 0x5289) |
| 49 | return -EINVAL; |
| 50 | |
| 51 | isp_base = adev->rmmio_base; |
| 52 | |
| 53 | isp->isp_cell = kcalloc(3, sizeof(struct mfd_cell), GFP_KERNEL); |
| 54 | if (!isp->isp_cell) { |
| 55 | r = -ENOMEM; |
| 56 | drm_err(&adev->ddev, |
| 57 | "%s: isp mfd cell alloc failed\n" , __func__); |
| 58 | goto failure; |
| 59 | } |
| 60 | |
| 61 | num_res = MAX_ISP410_MEM_RES + MAX_ISP410_INT_SRC; |
| 62 | isp->isp_res = kcalloc(num_res, sizeof(struct resource), |
| 63 | GFP_KERNEL); |
| 64 | if (!isp->isp_res) { |
| 65 | r = -ENOMEM; |
| 66 | drm_err(&adev->ddev, |
| 67 | "%s: isp mfd res alloc failed\n" , __func__); |
| 68 | goto failure; |
| 69 | } |
| 70 | |
| 71 | isp->isp_pdata = kzalloc(sizeof(*isp->isp_pdata), GFP_KERNEL); |
| 72 | if (!isp->isp_pdata) { |
| 73 | r = -ENOMEM; |
| 74 | drm_err(&adev->ddev, |
| 75 | "%s: isp platform data alloc failed\n" , __func__); |
| 76 | goto failure; |
| 77 | } |
| 78 | |
| 79 | /* initialize isp platform data */ |
| 80 | isp->isp_pdata->adev = (void *)adev; |
| 81 | isp->isp_pdata->asic_type = adev->asic_type; |
| 82 | isp->isp_pdata->base_rmmio_size = adev->rmmio_size; |
| 83 | |
| 84 | isp->isp_res[0].name = "isp_4_1_0_reg" ; |
| 85 | isp->isp_res[0].flags = IORESOURCE_MEM; |
| 86 | isp->isp_res[0].start = isp_base; |
| 87 | isp->isp_res[0].end = isp_base + ISP_REGS_OFFSET_END; |
| 88 | |
| 89 | isp->isp_res[1].name = "isp_4_1_phy0_reg" ; |
| 90 | isp->isp_res[1].flags = IORESOURCE_MEM; |
| 91 | isp->isp_res[1].start = isp_base + ISP410_PHY0_OFFSET; |
| 92 | isp->isp_res[1].end = isp_base + ISP410_PHY0_OFFSET + ISP410_PHY0_SIZE; |
| 93 | |
| 94 | for (idx = MAX_ISP410_MEM_RES, int_idx = 0; idx < num_res; idx++, int_idx++) { |
| 95 | isp->isp_res[idx].name = "isp_4_1_0_irq" ; |
| 96 | isp->isp_res[idx].flags = IORESOURCE_IRQ; |
| 97 | isp->isp_res[idx].start = |
| 98 | amdgpu_irq_create_mapping(adev, src_id: isp_4_1_0_int_srcid[int_idx]); |
| 99 | isp->isp_res[idx].end = |
| 100 | isp->isp_res[idx].start; |
| 101 | } |
| 102 | |
| 103 | isp->isp_cell[0].name = "amd_isp_capture" ; |
| 104 | isp->isp_cell[0].num_resources = num_res; |
| 105 | isp->isp_cell[0].resources = &isp->isp_res[0]; |
| 106 | isp->isp_cell[0].platform_data = isp->isp_pdata; |
| 107 | isp->isp_cell[0].pdata_size = sizeof(struct isp_platform_data); |
| 108 | |
| 109 | /* initialize isp i2c platform data */ |
| 110 | isp->isp_i2c_res = kcalloc(1, sizeof(struct resource), GFP_KERNEL); |
| 111 | if (!isp->isp_i2c_res) { |
| 112 | r = -ENOMEM; |
| 113 | drm_err(&adev->ddev, |
| 114 | "%s: isp mfd res alloc failed\n" , __func__); |
| 115 | goto failure; |
| 116 | } |
| 117 | |
| 118 | isp->isp_i2c_res[0].name = "isp_i2c0_reg" ; |
| 119 | isp->isp_i2c_res[0].flags = IORESOURCE_MEM; |
| 120 | isp->isp_i2c_res[0].start = isp_base + ISP410_I2C0_OFFSET; |
| 121 | isp->isp_i2c_res[0].end = isp_base + ISP410_I2C0_OFFSET + ISP410_I2C0_SIZE; |
| 122 | |
| 123 | isp->isp_cell[1].name = "amd_isp_i2c_designware" ; |
| 124 | isp->isp_cell[1].num_resources = 1; |
| 125 | isp->isp_cell[1].resources = &isp->isp_i2c_res[0]; |
| 126 | isp->isp_cell[1].platform_data = isp->isp_pdata; |
| 127 | isp->isp_cell[1].pdata_size = sizeof(struct isp_platform_data); |
| 128 | |
| 129 | /* initialize isp gpiochip platform data */ |
| 130 | isp->isp_gpio_res = kcalloc(1, sizeof(struct resource), GFP_KERNEL); |
| 131 | if (!isp->isp_gpio_res) { |
| 132 | r = -ENOMEM; |
| 133 | drm_err(&adev->ddev, |
| 134 | "%s: isp gpio res alloc failed\n" , __func__); |
| 135 | goto failure; |
| 136 | } |
| 137 | |
| 138 | isp->isp_gpio_res[0].name = "isp_gpio_reg" ; |
| 139 | isp->isp_gpio_res[0].flags = IORESOURCE_MEM; |
| 140 | isp->isp_gpio_res[0].start = isp_base + ISP410_GPIO_SENSOR_OFFSET; |
| 141 | isp->isp_gpio_res[0].end = isp_base + ISP410_GPIO_SENSOR_OFFSET + |
| 142 | ISP410_GPIO_SENSOR_SIZE; |
| 143 | |
| 144 | isp->isp_cell[2].name = "amdisp-pinctrl" ; |
| 145 | isp->isp_cell[2].num_resources = 1; |
| 146 | isp->isp_cell[2].resources = &isp->isp_gpio_res[0]; |
| 147 | isp->isp_cell[2].platform_data = isp->isp_pdata; |
| 148 | isp->isp_cell[2].pdata_size = sizeof(struct isp_platform_data); |
| 149 | |
| 150 | r = mfd_add_hotplug_devices(parent: isp->parent, cells: isp->isp_cell, n_devs: 3); |
| 151 | if (r) { |
| 152 | drm_err(&adev->ddev, |
| 153 | "%s: add mfd hotplug device failed\n" , __func__); |
| 154 | goto failure; |
| 155 | } |
| 156 | |
| 157 | return 0; |
| 158 | |
| 159 | failure: |
| 160 | |
| 161 | kfree(objp: isp->isp_pdata); |
| 162 | kfree(objp: isp->isp_res); |
| 163 | kfree(objp: isp->isp_cell); |
| 164 | kfree(objp: isp->isp_i2c_res); |
| 165 | kfree(objp: isp->isp_gpio_res); |
| 166 | |
| 167 | return r; |
| 168 | } |
| 169 | |
| 170 | static int isp_v4_1_0_hw_fini(struct amdgpu_isp *isp) |
| 171 | { |
| 172 | mfd_remove_devices(parent: isp->parent); |
| 173 | |
| 174 | kfree(objp: isp->isp_res); |
| 175 | kfree(objp: isp->isp_cell); |
| 176 | kfree(objp: isp->isp_pdata); |
| 177 | kfree(objp: isp->isp_i2c_res); |
| 178 | kfree(objp: isp->isp_gpio_res); |
| 179 | |
| 180 | return 0; |
| 181 | } |
| 182 | |
| 183 | static const struct isp_funcs isp_v4_1_0_funcs = { |
| 184 | .hw_init = isp_v4_1_0_hw_init, |
| 185 | .hw_fini = isp_v4_1_0_hw_fini, |
| 186 | }; |
| 187 | |
| 188 | void isp_v4_1_0_set_isp_funcs(struct amdgpu_isp *isp) |
| 189 | { |
| 190 | isp->funcs = &isp_v4_1_0_funcs; |
| 191 | } |
| 192 | |