1/*
2 * Copyright 2023 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/firmware.h>
25#include "amdgpu.h"
26#include "amdgpu_imu.h"
27#include "amdgpu_dpm.h"
28
29#include "imu_v12_0.h"
30
31#include "gc/gc_12_0_0_offset.h"
32#include "gc/gc_12_0_0_sh_mask.h"
33#include "mmhub/mmhub_4_1_0_offset.h"
34
35MODULE_FIRMWARE("amdgpu/gc_12_0_0_imu.bin");
36MODULE_FIRMWARE("amdgpu/gc_12_0_1_imu.bin");
37MODULE_FIRMWARE("amdgpu/gc_12_0_1_imu_kicker.bin");
38
39#define TRANSFER_RAM_MASK 0x001c0000
40
41static int imu_v12_0_init_microcode(struct amdgpu_device *adev)
42{
43 char ucode_prefix[30];
44 int err;
45 const struct imu_firmware_header_v1_0 *imu_hdr;
46 struct amdgpu_firmware_info *info = NULL;
47
48 DRM_DEBUG("\n");
49
50 amdgpu_ucode_ip_version_decode(adev, block_type: GC_HWIP, ucode_prefix, len: sizeof(ucode_prefix));
51 if (amdgpu_is_kicker_fw(adev))
52 err = amdgpu_ucode_request(adev, fw: &adev->gfx.imu_fw, required: AMDGPU_UCODE_REQUIRED,
53 fmt: "amdgpu/%s_imu_kicker.bin", ucode_prefix);
54 else
55 err = amdgpu_ucode_request(adev, fw: &adev->gfx.imu_fw, required: AMDGPU_UCODE_REQUIRED,
56 fmt: "amdgpu/%s_imu.bin", ucode_prefix);
57 if (err)
58 goto out;
59
60 imu_hdr = (const struct imu_firmware_header_v1_0 *)adev->gfx.imu_fw->data;
61 adev->gfx.imu_fw_version = le32_to_cpu(imu_hdr->header.ucode_version);
62
63 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
64 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_IMU_I];
65 info->ucode_id = AMDGPU_UCODE_ID_IMU_I;
66 info->fw = adev->gfx.imu_fw;
67 adev->firmware.fw_size +=
68 ALIGN(le32_to_cpu(imu_hdr->imu_iram_ucode_size_bytes), PAGE_SIZE);
69 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_IMU_D];
70 info->ucode_id = AMDGPU_UCODE_ID_IMU_D;
71 info->fw = adev->gfx.imu_fw;
72 adev->firmware.fw_size +=
73 ALIGN(le32_to_cpu(imu_hdr->imu_dram_ucode_size_bytes), PAGE_SIZE);
74 }
75
76out:
77 if (err) {
78 dev_err(adev->dev,
79 "gfx12: Failed to load firmware \"%s_imu.bin\"\n",
80 ucode_prefix);
81 amdgpu_ucode_release(fw: &adev->gfx.imu_fw);
82 }
83
84 return err;
85}
86
87static int imu_v12_0_load_microcode(struct amdgpu_device *adev)
88{
89 const struct imu_firmware_header_v1_0 *hdr;
90 const __le32 *fw_data;
91 unsigned i, fw_size;
92
93 if (!adev->gfx.imu_fw)
94 return -EINVAL;
95
96 hdr = (const struct imu_firmware_header_v1_0 *)adev->gfx.imu_fw->data;
97
98 fw_data = (const __le32 *)(adev->gfx.imu_fw->data +
99 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
100 fw_size = le32_to_cpu(hdr->imu_iram_ucode_size_bytes) / 4;
101
102 WREG32_SOC15(GC, 0, regGFX_IMU_I_RAM_ADDR, 0);
103
104 for (i = 0; i < fw_size; i++)
105 WREG32_SOC15(GC, 0, regGFX_IMU_I_RAM_DATA, le32_to_cpup(fw_data++));
106
107 WREG32_SOC15(GC, 0, regGFX_IMU_I_RAM_ADDR, adev->gfx.imu_fw_version);
108
109 fw_data = (const __le32 *)(adev->gfx.imu_fw->data +
110 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
111 le32_to_cpu(hdr->imu_iram_ucode_size_bytes));
112 fw_size = le32_to_cpu(hdr->imu_dram_ucode_size_bytes) / 4;
113
114 WREG32_SOC15(GC, 0, regGFX_IMU_D_RAM_ADDR, 0);
115
116 for (i = 0; i < fw_size; i++)
117 WREG32_SOC15(GC, 0, regGFX_IMU_D_RAM_DATA, le32_to_cpup(fw_data++));
118
119 WREG32_SOC15(GC, 0, regGFX_IMU_D_RAM_ADDR, adev->gfx.imu_fw_version);
120
121 return 0;
122}
123
124static int imu_v12_0_wait_for_reset_status(struct amdgpu_device *adev)
125{
126 u32 imu_reg_val = 0;
127 int i;
128
129 for (i = 0; i < adev->usec_timeout; i++) {
130 imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_GFX_RESET_CTRL);
131 if ((imu_reg_val & 0x1f) == 0x1f)
132 break;
133 udelay(usec: 1);
134 }
135
136 if (i >= adev->usec_timeout) {
137 dev_err(adev->dev, "init imu: IMU start timeout\n");
138 return -ETIMEDOUT;
139 }
140
141 return 0;
142}
143
144static void imu_v12_0_setup(struct amdgpu_device *adev)
145{
146 u32 imu_reg_val;
147
148 WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_ACCESS_CTRL0, 0xffffff);
149 WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_ACCESS_CTRL1, 0xffff);
150
151 if (adev->gfx.imu.mode == DEBUG_MODE) {
152 imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16);
153 imu_reg_val |= 0x1;
154 WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16, imu_reg_val);
155
156 imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_10);
157 imu_reg_val |= 0x20010007;
158 WREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_10, imu_reg_val);
159
160 }
161}
162
163static int imu_v12_0_start(struct amdgpu_device *adev)
164{
165 u32 imu_reg_val;
166
167 imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_CORE_CTRL);
168 imu_reg_val &= 0xfffffffe;
169 WREG32_SOC15(GC, 0, regGFX_IMU_CORE_CTRL, imu_reg_val);
170
171 if (adev->flags & AMD_IS_APU)
172 amdgpu_dpm_set_gfx_power_up_by_imu(adev);
173
174 return imu_v12_0_wait_for_reset_status(adev);
175}
176
177static const struct imu_rlc_ram_golden imu_rlc_ram_golden_12_0_1[] = {
178 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCH_PIPE_STEER, 0x1e4, 0x1c0000),
179 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGL1X_PIPE_STEER, 0x1e4, 0x1c0000),
180 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGL1_PIPE_STEER, 0x1e4, 0x1c0000),
181 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGL2_PIPE_STEER_0, 0x13571357, 0x1c0000),
182 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGL2_PIPE_STEER_1, 0x64206420, 0x1c0000),
183 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGL2_PIPE_STEER_2, 0x2460246, 0x1c0000),
184 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGL2_PIPE_STEER_3, 0x75317531, 0x1c0000),
185 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGL2C_CTRL3, 0xc0d41183, 0x1c0000),
186 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regSDMA0_CHICKEN_BITS, 0x507d1c0, 0x1c0000),
187 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regSDMA1_CHICKEN_BITS, 0x507d1c0, 0x1c0000),
188 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCP_RB_WPTR_POLL_CNTL, 0x600100, 0x1c0000),
189 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_CPWD_SDP_CREDITS, 0x3f7fff, 0x1c0000),
190 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_SE_SDP_CREDITS, 0x3f7ebf, 0x1c0000),
191 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_CPWD_SDP_TAG_RESERVE0, 0x2e00000, 0x1c0000),
192 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_CPWD_SDP_TAG_RESERVE1, 0x1a078, 0x1c0000),
193 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_CPWD_SDP_TAG_RESERVE2, 0x0, 0x1c0000),
194 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_SE_SDP_TAG_RESERVE0, 0x0, 0x1c0000),
195 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_SE_SDP_TAG_RESERVE1, 0x12030, 0x1c0000),
196 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_SE_SDP_TAG_RESERVE2, 0x0, 0x1c0000),
197 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_CPWD_SDP_VCC_RESERVE0, 0x19041000, 0x1c0000),
198 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_CPWD_SDP_VCC_RESERVE1, 0x80000000, 0x1c0000),
199 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_SE_SDP_VCC_RESERVE0, 0x1e080000, 0x1c0000),
200 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_SE_SDP_VCC_RESERVE1, 0x80000000, 0x1c0000),
201 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_CPWD_SDP_PRIORITY, 0x880, 0x1c0000),
202 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_SE_SDP_PRIORITY, 0x8880, 0x1c0000),
203 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_CPWD_SDP_ARB_FINAL, 0x17, 0x1c0000),
204 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_SE_SDP_ARB_FINAL, 0x77, 0x1c0000),
205 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_CPWD_SDP_ENABLE, 0x00000001, 0x1c0000),
206 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_SE_SDP_ENABLE, 0x00000001, 0x1c0000),
207 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL2, 0x20000, 0x1c0000),
208 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_APT_CNTL, 0x0c, 0x1c0000),
209 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_CACHEABLE_DRAM_ADDRESS_END, 0xfffff, 0x1c0000),
210 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_CPWD_MISC, 0x0091, 0x1c0000),
211 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_SE_MISC, 0x0091, 0x1c0000),
212 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGRBM_GFX_INDEX, 0xe0000000, 0x1c0000),
213 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCR_GENERAL_CNTL, 0x00008500, 0x1c0000),
214 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regPA_CL_ENHANCE, 0x00880007, 0x1c0000),
215 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regTD_CNTL, 0x00000001, 0x1c0000),
216 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGRBM_GFX_INDEX, 0x00000000, 0x1c0000),
217 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regRMI_GENERAL_CNTL, 0x01e00000, 0x1c0000),
218 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGRBM_GFX_INDEX, 0x00000001, 0x1c0000),
219 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regRMI_GENERAL_CNTL, 0x01e00000, 0x1c0000),
220 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGRBM_GFX_INDEX, 0x00000100, 0x1c0000),
221 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regRMI_GENERAL_CNTL, 0x01e00000, 0x1c0000),
222 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGRBM_GFX_INDEX, 0x00000101, 0x1c0000),
223 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regRMI_GENERAL_CNTL, 0x01e00000, 0x1c0000),
224 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGRBM_GFX_INDEX, 0xe0000000, 0x1c0000),
225 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGB_ADDR_CONFIG, 0x08200545, 0x1c0000),
226 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGRBMH_CP_PERFMON_CNTL, 0x00000000, 0x1c0000),
227 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCB_PERFCOUNTER0_SELECT1, 0x000fffff, 0x1c0000),
228 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCP_DEBUG_2, 0x00020000, 0x1c0000),
229 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCP_CPC_DEBUG, 0x00500010, 0x1c0000),
230 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, 0x00000500, 0x1c0000),
231 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR, 0x00000001, 0x1c0000),
232 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 0x00000000, 0x1c0000),
233 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_LOCAL_FB_ADDRESS_START, 0x00000000, 0x1c0000),
234 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_LOCAL_FB_ADDRESS_END, 0x0000000f, 0x1c0000),
235 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_FB_LOCATION_BASE, 0x00006000, 0x1c0000),
236 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_FB_LOCATION_TOP, 0x0000600f, 0x1c0000),
237 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_CONTEXT0_CNTL, 0x00000000, 0x1c0000),
238 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_CONTEXT1_CNTL, 0x00000000, 0x1c0000),
239 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_NB_TOP_OF_DRAM_SLOT1, 0xff800000, 0xe0000000),
240 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_NB_LOWER_TOP_OF_DRAM2, 0x00000001, 0x1c0000),
241 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_NB_UPPER_TOP_OF_DRAM2, 0x0000ffff, 0x1c0000),
242 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_AGP_BASE, 0x00000000, 0x1c0000),
243 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_AGP_BOT, 0x00000002, 0x1c0000),
244 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_AGP_TOP, 0x00000000, 0x1c0000),
245 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL, 0x00001ffc, 0x1c0000),
246 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, 0x00000551, 0x1c0000),
247 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL, 0x00080603, 0x1c0000),
248 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL2, 0x00000003, 0x1c0000),
249 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL3, 0x00100003, 0x1c0000),
250 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL5, 0x00003fe0, 0x1c0000),
251 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR, 0x0003d000, 0x1c0000),
252 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 0x0003d7ff, 0x1c0000),
253 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 0, 0x1c0000),
254 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 0, 0x1c0000)
255};
256
257static void program_imu_rlc_ram_old(struct amdgpu_device *adev,
258 const struct imu_rlc_ram_golden *regs,
259 const u32 array_size)
260{
261 const struct imu_rlc_ram_golden *entry;
262 u32 reg, data;
263 int i;
264
265 for (i = 0; i < array_size; ++i) {
266 entry = &regs[i];
267 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
268 reg |= entry->addr_mask;
269 data = entry->data;
270 if (entry->reg == regGCMC_VM_AGP_BASE)
271 data = 0x00ffffff;
272 else if (entry->reg == regGCMC_VM_AGP_TOP)
273 data = 0x0;
274 else if (entry->reg == regGCMC_VM_FB_LOCATION_BASE)
275 data = adev->gmc.vram_start >> 24;
276 else if (entry->reg == regGCMC_VM_FB_LOCATION_TOP)
277 data = adev->gmc.vram_end >> 24;
278
279 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_HIGH, 0);
280 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_LOW, reg);
281 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_DATA, data);
282 }
283}
284
285static u32 imu_v12_0_grbm_gfx_index_remap(struct amdgpu_device *adev,
286 u32 data, bool high)
287{
288 u32 val, inst_index;
289
290 inst_index = REG_GET_FIELD(data, GRBM_GFX_INDEX, INSTANCE_INDEX);
291
292 if (high)
293 val = inst_index >> 5;
294 else
295 val = REG_GET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES) << 18 |
296 REG_GET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES) << 19 |
297 REG_GET_FIELD(data, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES) << 20 |
298 REG_GET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX) << 21 |
299 REG_GET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX) << 25 |
300 (inst_index & 0x1f);
301
302 return val;
303}
304
305static u32 imu_v12_init_gfxhub_settings(struct amdgpu_device *adev,
306 u32 reg, u32 data)
307{
308 if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_FB_LOCATION_BASE))
309 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_BASE);
310 else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_FB_LOCATION_TOP))
311 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_TOP);
312 else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_FB_OFFSET))
313 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET);
314 else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_AGP_BASE))
315 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE);
316 else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_AGP_BOT))
317 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT);
318 else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_AGP_TOP))
319 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP);
320 else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL))
321 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);
322 else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR))
323 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR);
324 else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR))
325 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR);
326 else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_LOCAL_FB_ADDRESS_START))
327 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_LOCAL_FB_ADDRESS_START);
328 else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_LOCAL_FB_ADDRESS_END))
329 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_LOCAL_FB_ADDRESS_END);
330 else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_LOCAL_SYSMEM_ADDRESS_START))
331 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_LOCAL_SYSMEM_ADDRESS_START);
332 else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_LOCAL_SYSMEM_ADDRESS_END))
333 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_LOCAL_SYSMEM_ADDRESS_END);
334 else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB))
335 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB);
336 else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB))
337 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB);
338 else
339 return data;
340}
341
342static void program_imu_rlc_ram(struct amdgpu_device *adev,
343 const u32 *regs,
344 const u32 array_size)
345{
346 u32 reg, data, val_h = 0, val_l = TRANSFER_RAM_MASK;
347 int i;
348
349 if (array_size % 3)
350 return;
351
352 for (i = 0; i < array_size; i += 3) {
353 reg = regs[i + 0];
354 data = regs[i + 2];
355 data = imu_v12_init_gfxhub_settings(adev, reg, data);
356 if (reg == SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX)) {
357 val_l = imu_v12_0_grbm_gfx_index_remap(adev, data, high: false);
358 val_h = imu_v12_0_grbm_gfx_index_remap(adev, data, high: true);
359 } else {
360 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_HIGH, val_h);
361 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_LOW, reg | val_l);
362 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_DATA, data);
363 }
364 }
365}
366
367static void imu_v12_0_program_rlc_ram(struct amdgpu_device *adev)
368{
369 u32 reg_data, size = 0;
370 const u32 *data = NULL;
371 int r = -EINVAL;
372
373 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_INDEX, 0x2);
374
375 switch (amdgpu_ip_version(adev, ip: GC_HWIP, inst: 0)) {
376 case IP_VERSION(12, 0, 0):
377 case IP_VERSION(12, 0, 1):
378 if (!r)
379 program_imu_rlc_ram(adev, regs: data, array_size: (const u32)size);
380 else
381 program_imu_rlc_ram_old(adev, regs: imu_rlc_ram_golden_12_0_1,
382 array_size: (const u32)ARRAY_SIZE(imu_rlc_ram_golden_12_0_1));
383 break;
384 default:
385 BUG();
386 break;
387 }
388
389 //Indicate the latest entry
390 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_HIGH, 0);
391 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_LOW, 0);
392 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_DATA, 0);
393
394 reg_data = RREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_INDEX);
395 reg_data |= GFX_IMU_RLC_RAM_INDEX__RAM_VALID_MASK;
396 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_INDEX, reg_data);
397}
398
399const struct amdgpu_imu_funcs gfx_v12_0_imu_funcs = {
400 .init_microcode = imu_v12_0_init_microcode,
401 .load_microcode = imu_v12_0_load_microcode,
402 .setup_imu = imu_v12_0_setup,
403 .start_imu = imu_v12_0_start,
404 .program_rlc_ram = imu_v12_0_program_rlc_ram,
405 .wait_for_reset_status = imu_v12_0_wait_for_reset_status,
406};
407

source code of linux/drivers/gpu/drm/amd/amdgpu/imu_v12_0.c