1/*
2 * Copyright 2023 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#ifndef __CLEARSTATE_GFX12_H_
24#define __CLEARSTATE_GFX12_H_
25
26static const unsigned int gfx12_SECT_CONTEXT_def_1[] = {
270x00000000, //mmSC_MEM_TEMPORAL
280x00000000, //mmSC_MEM_SPEC_READ
290x00000000, //mmPA_SC_VPORT_0_TL
300x00000000, //mmPA_SC_VPORT_0_BR
310x00000000, //mmPA_SC_VPORT_1_TL
320x00000000, //mmPA_SC_VPORT_1_BR
330x00000000, //mmPA_SC_VPORT_2_TL
340x00000000, //mmPA_SC_VPORT_2_BR
350x00000000, //mmPA_SC_VPORT_3_TL
360x00000000, //mmPA_SC_VPORT_3_BR
370x00000000, //mmPA_SC_VPORT_4_TL
380x00000000, //mmPA_SC_VPORT_4_BR
390x00000000, //mmPA_SC_VPORT_5_TL
400x00000000, //mmPA_SC_VPORT_5_BR
410x00000000, //mmPA_SC_VPORT_6_TL
420x00000000, //mmPA_SC_VPORT_6_BR
430x00000000, //mmPA_SC_VPORT_7_TL
440x00000000, //mmPA_SC_VPORT_7_BR
450x00000000, //mmPA_SC_VPORT_8_TL
460x00000000, //mmPA_SC_VPORT_8_BR
470x00000000, //mmPA_SC_VPORT_9_TL
480x00000000, //mmPA_SC_VPORT_9_BR
490x00000000, //mmPA_SC_VPORT_10_TL
500x00000000, //mmPA_SC_VPORT_10_BR
510x00000000, //mmPA_SC_VPORT_11_TL
520x00000000, //mmPA_SC_VPORT_11_BR
530x00000000, //mmPA_SC_VPORT_12_TL
540x00000000, //mmPA_SC_VPORT_12_BR
550x00000000, //mmPA_SC_VPORT_13_TL
560x00000000, //mmPA_SC_VPORT_13_BR
570x00000000, //mmPA_SC_VPORT_14_TL
580x00000000, //mmPA_SC_VPORT_14_BR
590x00000000, //mmPA_SC_VPORT_15_TL
600x00000000, //mmPA_SC_VPORT_15_BR
61};
62
63static const unsigned int gfx12_SECT_CONTEXT_def_2[] = {
640x00000000, //mmPA_CL_PROG_NEAR_CLIP_Z
650x00000000, //mmPA_RATE_CNTL
66};
67
68static const unsigned int gfx12_SECT_CONTEXT_def_3[] = {
690x00000000, //mmCP_PERFMON_CNTX_CNTL
70};
71
72static const unsigned int gfx12_SECT_CONTEXT_def_4[] = {
730x00000000, //mmCONTEXT_RESERVED_REG0
740x00000000, //mmCONTEXT_RESERVED_REG1
750x00000000, //mmPA_SC_CLIPRECT_0_EXT
760x00000000, //mmPA_SC_CLIPRECT_1_EXT
770x00000000, //mmPA_SC_CLIPRECT_2_EXT
780x00000000, //mmPA_SC_CLIPRECT_3_EXT
79};
80
81static const unsigned int gfx12_SECT_CONTEXT_def_5[] = {
820x00000000, //mmPA_SC_HIZ_INFO
830x00000000, //mmPA_SC_HIS_INFO
840x00000000, //mmPA_SC_HIZ_BASE
850x00000000, //mmPA_SC_HIZ_BASE_EXT
860x00000000, //mmPA_SC_HIZ_SIZE_XY
870x00000000, //mmPA_SC_HIS_BASE
880x00000000, //mmPA_SC_HIS_BASE_EXT
890x00000000, //mmPA_SC_HIS_SIZE_XY
900x00000000, //mmPA_SC_BINNER_OUTPUT_TIMEOUT_CNTL
910x00000000, //mmPA_SC_BINNER_DYNAMIC_BATCH_LIMIT
920x00000000, //mmPA_SC_HISZ_CONTROL
93};
94
95static const unsigned int gfx12_SECT_CONTEXT_def_6[] = {
960x00000000, //mmCB_MEM0_INFO
970x00000000, //mmCB_MEM1_INFO
980x00000000, //mmCB_MEM2_INFO
990x00000000, //mmCB_MEM3_INFO
1000x00000000, //mmCB_MEM4_INFO
1010x00000000, //mmCB_MEM5_INFO
1020x00000000, //mmCB_MEM6_INFO
1030x00000000, //mmCB_MEM7_INFO
104};
105
106static const struct cs_extent_def gfx12_SECT_CONTEXT_defs[] = {
107 {gfx12_SECT_CONTEXT_def_1, 0x0000a03e, 34 },
108 {gfx12_SECT_CONTEXT_def_2, 0x0000a0cc, 2 },
109 {gfx12_SECT_CONTEXT_def_3, 0x0000a0d8, 1 },
110 {gfx12_SECT_CONTEXT_def_4, 0x0000a0db, 6 },
111 {gfx12_SECT_CONTEXT_def_5, 0x0000a2e5, 11 },
112 {gfx12_SECT_CONTEXT_def_6, 0x0000a3c0, 8 },
113 { 0, 0, 0 }
114};
115
116static const struct cs_section_def gfx12_cs_data[] = {
117 { gfx12_SECT_CONTEXT_defs, SECT_CONTEXT },
118 { 0, SECT_NONE }
119};
120
121#endif /* __CLEARSTATE_GFX12_H_ */
122

source code of linux/drivers/gpu/drm/amd/amdgpu/clearstate_gfx12.h