1/*
2 * Copyright (C) 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21#ifndef __AMDGPU_UMC_H__
22#define __AMDGPU_UMC_H__
23#include "amdgpu_ras.h"
24#include "amdgpu_mca.h"
25/*
26 * (addr / 256) * 4096, the higher 26 bits in ErrorAddr
27 * is the index of 4KB block
28 */
29#define ADDR_OF_4KB_BLOCK(addr) (((addr) & ~0xffULL) << 4)
30/*
31 * (addr / 256) * 8192, the higher 26 bits in ErrorAddr
32 * is the index of 8KB block
33 */
34#define ADDR_OF_8KB_BLOCK(addr) (((addr) & ~0xffULL) << 5)
35/*
36 * (addr / 256) * 32768, the higher 26 bits in ErrorAddr
37 * is the index of 8KB block
38 */
39#define ADDR_OF_32KB_BLOCK(addr) (((addr) & ~0xffULL) << 7)
40/* channel index is the index of 256B block */
41#define ADDR_OF_256B_BLOCK(channel_index) ((channel_index) << 8)
42/* offset in 256B block */
43#define OFFSET_IN_256B_BLOCK(addr) ((addr) & 0xffULL)
44
45#define LOOP_UMC_INST(umc_inst) for ((umc_inst) = 0; (umc_inst) < adev->umc.umc_inst_num; (umc_inst)++)
46#define LOOP_UMC_CH_INST(ch_inst) for ((ch_inst) = 0; (ch_inst) < adev->umc.channel_inst_num; (ch_inst)++)
47#define LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) LOOP_UMC_INST((umc_inst)) LOOP_UMC_CH_INST((ch_inst))
48
49#define LOOP_UMC_NODE_INST(node_inst) \
50 for_each_set_bit((node_inst), &(adev->umc.active_mask), adev->umc.node_inst_num)
51
52#define LOOP_UMC_EACH_NODE_INST_AND_CH(node_inst, umc_inst, ch_inst) \
53 LOOP_UMC_NODE_INST((node_inst)) LOOP_UMC_INST_AND_CH((umc_inst), (ch_inst))
54
55/* Page retirement tag */
56#define UMC_ECC_NEW_DETECTED_TAG 0x1
57/*
58 * a flag to indicate v2 of channel index stored in eeprom
59 *
60 * v1 (legacy way): store channel index within a umc instance in eeprom
61 * range in UMC v12: 0 ~ 7
62 * v2: store global channel index in eeprom
63 * range in UMC v12: 0 ~ 127
64 *
65 * NOTE: it's better to store it in eeprom_table_record.mem_channel,
66 * but there is only 8 bits in mem_channel, and the channel number may
67 * increase in the future, we decide to save it in
68 * eeprom_table_record.retired_page. retired_page is useless in v2,
69 * we depend on eeprom_table_record.address instead of retired_page in v2.
70 * Only 48 bits are saved on eeprom, use bit 47 here.
71 */
72#define UMC_CHANNEL_IDX_V2 BIT_ULL(47)
73
74/*
75 * save nps value to eeprom_table_record.retired_page[47:40],
76 * the channel index flag above will be retired.
77 */
78#define UMC_NPS_SHIFT 40
79#define UMC_NPS_MASK 0xffULL
80
81/* three column bits and one row bit in MCA address flip
82 * in bad page retirement
83 */
84#define RETIRE_FLIP_BITS_NUM 4
85
86struct amdgpu_umc_flip_bits {
87 uint32_t flip_bits_in_pa[RETIRE_FLIP_BITS_NUM];
88 uint32_t flip_row_bit;
89 uint32_t r13_in_pa;
90 uint32_t bit_num;
91};
92
93typedef int (*umc_func)(struct amdgpu_device *adev, uint32_t node_inst,
94 uint32_t umc_inst, uint32_t ch_inst, void *data);
95
96struct amdgpu_umc_ras {
97 struct amdgpu_ras_block_object ras_block;
98 void (*err_cnt_init)(struct amdgpu_device *adev);
99 bool (*query_ras_poison_mode)(struct amdgpu_device *adev);
100 void (*ecc_info_query_ras_error_count)(struct amdgpu_device *adev,
101 void *ras_error_status);
102 void (*ecc_info_query_ras_error_address)(struct amdgpu_device *adev,
103 void *ras_error_status);
104 bool (*check_ecc_err_status)(struct amdgpu_device *adev,
105 enum amdgpu_mca_error_type type, void *ras_error_status);
106 int (*update_ecc_status)(struct amdgpu_device *adev,
107 uint64_t status, uint64_t ipid, uint64_t addr);
108 int (*convert_ras_err_addr)(struct amdgpu_device *adev,
109 struct ras_err_data *err_data,
110 struct ta_ras_query_address_input *addr_in,
111 struct ta_ras_query_address_output *addr_out,
112 bool dump_addr);
113 uint32_t (*get_die_id_from_pa)(struct amdgpu_device *adev,
114 uint64_t mca_addr, uint64_t retired_page);
115 void (*get_retire_flip_bits)(struct amdgpu_device *adev);
116 void (*mca_ipid_parse)(struct amdgpu_device *adev, uint64_t ipid,
117 uint32_t *did, uint32_t *ch, uint32_t *umc_inst, uint32_t *sid);
118};
119
120struct amdgpu_umc_funcs {
121 void (*init_registers)(struct amdgpu_device *adev);
122};
123
124struct amdgpu_umc {
125 /* max error count in one ras query call */
126 uint32_t max_ras_err_cnt_per_query;
127 /* number of umc channel instance with memory map register access */
128 uint32_t channel_inst_num;
129 /* number of umc instance with memory map register access */
130 uint32_t umc_inst_num;
131
132 /* Total number of umc node instance including harvest one */
133 uint32_t node_inst_num;
134
135 /* UMC regiser per channel offset */
136 uint32_t channel_offs;
137 /* how many pages are retired in one UE */
138 uint32_t retire_unit;
139 /* channel index table of interleaved memory */
140 const uint32_t *channel_idx_tbl;
141 struct ras_common_if *ras_if;
142
143 const struct amdgpu_umc_funcs *funcs;
144 struct amdgpu_umc_ras *ras;
145
146 /* active mask for umc node instance */
147 unsigned long active_mask;
148
149 struct amdgpu_umc_flip_bits flip_bits;
150
151 unsigned long err_addr_cnt;
152};
153
154int amdgpu_umc_ras_sw_init(struct amdgpu_device *adev);
155int amdgpu_umc_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block);
156int amdgpu_umc_poison_handler(struct amdgpu_device *adev,
157 enum amdgpu_ras_block block, uint32_t reset);
158int amdgpu_umc_pasid_poison_handler(struct amdgpu_device *adev,
159 enum amdgpu_ras_block block, uint16_t pasid,
160 pasid_notify pasid_fn, void *data, uint32_t reset);
161int amdgpu_umc_process_ecc_irq(struct amdgpu_device *adev,
162 struct amdgpu_irq_src *source,
163 struct amdgpu_iv_entry *entry);
164int amdgpu_umc_fill_error_record(struct ras_err_data *err_data,
165 uint64_t err_addr,
166 uint64_t retired_page,
167 uint32_t channel_index,
168 uint32_t umc_inst);
169
170int amdgpu_umc_process_ras_data_cb(struct amdgpu_device *adev,
171 void *ras_error_status,
172 struct amdgpu_iv_entry *entry);
173int amdgpu_umc_page_retirement_mca(struct amdgpu_device *adev,
174 uint64_t err_addr, uint32_t ch_inst, uint32_t umc_inst);
175
176int amdgpu_umc_loop_channels(struct amdgpu_device *adev,
177 umc_func func, void *data);
178
179int amdgpu_umc_update_ecc_status(struct amdgpu_device *adev,
180 uint64_t status, uint64_t ipid, uint64_t addr);
181int amdgpu_umc_logs_ecc_err(struct amdgpu_device *adev,
182 struct radix_tree_root *ecc_tree, struct ras_ecc_err *ecc_err);
183
184void amdgpu_umc_handle_bad_pages(struct amdgpu_device *adev,
185 void *ras_error_status);
186int amdgpu_umc_pages_in_a_row(struct amdgpu_device *adev,
187 struct ras_err_data *err_data, uint64_t pa_addr);
188int amdgpu_umc_lookup_bad_pages_in_a_row(struct amdgpu_device *adev,
189 uint64_t pa_addr, uint64_t *pfns, int len);
190int amdgpu_umc_mca_to_addr(struct amdgpu_device *adev,
191 uint64_t err_addr, uint32_t ch, uint32_t umc,
192 uint32_t node, uint32_t socket,
193 struct ta_ras_query_address_output *addr_out, bool dump_addr);
194int amdgpu_umc_pa2mca(struct amdgpu_device *adev,
195 uint64_t pa, uint64_t *mca, enum amdgpu_memory_partition nps);
196#endif
197

source code of linux/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h