1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26
27#include "amdgpu.h"
28#include "amdgpu_jpeg.h"
29#include "amdgpu_pm.h"
30#include "soc15d.h"
31#include "soc15_common.h"
32
33#define JPEG_IDLE_TIMEOUT msecs_to_jiffies(1000)
34
35static void amdgpu_jpeg_idle_work_handler(struct work_struct *work);
36static void amdgpu_jpeg_reg_dump_fini(struct amdgpu_device *adev);
37
38int amdgpu_jpeg_sw_init(struct amdgpu_device *adev)
39{
40 int i, r;
41
42 INIT_DELAYED_WORK(&adev->jpeg.idle_work, amdgpu_jpeg_idle_work_handler);
43 mutex_init(&adev->jpeg.jpeg_pg_lock);
44 atomic_set(v: &adev->jpeg.total_submission_cnt, i: 0);
45
46 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
47 (adev->pg_flags & AMD_PG_SUPPORT_JPEG_DPG))
48 adev->jpeg.indirect_sram = true;
49
50 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
51 if (adev->jpeg.harvest_config & (1U << i))
52 continue;
53
54 if (adev->jpeg.indirect_sram) {
55 r = amdgpu_bo_create_kernel(adev, size: 64 * 2 * 4, PAGE_SIZE,
56 AMDGPU_GEM_DOMAIN_VRAM |
57 AMDGPU_GEM_DOMAIN_GTT,
58 bo_ptr: &adev->jpeg.inst[i].dpg_sram_bo,
59 gpu_addr: &adev->jpeg.inst[i].dpg_sram_gpu_addr,
60 cpu_addr: &adev->jpeg.inst[i].dpg_sram_cpu_addr);
61 if (r) {
62 dev_err(adev->dev,
63 "JPEG %d (%d) failed to allocate DPG bo\n", i, r);
64 return r;
65 }
66 }
67 }
68
69 return 0;
70}
71
72int amdgpu_jpeg_sw_fini(struct amdgpu_device *adev)
73{
74 int i, j;
75
76 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
77 if (adev->jpeg.harvest_config & (1U << i))
78 continue;
79
80 amdgpu_bo_free_kernel(
81 bo: &adev->jpeg.inst[i].dpg_sram_bo,
82 gpu_addr: &adev->jpeg.inst[i].dpg_sram_gpu_addr,
83 cpu_addr: (void **)&adev->jpeg.inst[i].dpg_sram_cpu_addr);
84
85 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j)
86 amdgpu_ring_fini(ring: &adev->jpeg.inst[i].ring_dec[j]);
87 }
88
89 if (adev->jpeg.reg_list)
90 amdgpu_jpeg_reg_dump_fini(adev);
91
92 mutex_destroy(lock: &adev->jpeg.jpeg_pg_lock);
93
94 return 0;
95}
96
97int amdgpu_jpeg_suspend(struct amdgpu_device *adev)
98{
99 cancel_delayed_work_sync(dwork: &adev->jpeg.idle_work);
100
101 return 0;
102}
103
104int amdgpu_jpeg_resume(struct amdgpu_device *adev)
105{
106 return 0;
107}
108
109static void amdgpu_jpeg_idle_work_handler(struct work_struct *work)
110{
111 struct amdgpu_device *adev =
112 container_of(work, struct amdgpu_device, jpeg.idle_work.work);
113 unsigned int fences = 0;
114 unsigned int i, j;
115
116 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
117 if (adev->jpeg.harvest_config & (1U << i))
118 continue;
119
120 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j)
121 fences += amdgpu_fence_count_emitted(ring: &adev->jpeg.inst[i].ring_dec[j]);
122 }
123
124 if (!fences && !atomic_read(v: &adev->jpeg.total_submission_cnt)) {
125 mutex_lock(&adev->jpeg.jpeg_pg_lock);
126 amdgpu_device_ip_set_powergating_state(dev: adev, block_type: AMD_IP_BLOCK_TYPE_JPEG,
127 state: AMD_PG_STATE_GATE);
128 mutex_unlock(lock: &adev->jpeg.jpeg_pg_lock);
129 } else
130 schedule_delayed_work(dwork: &adev->jpeg.idle_work, JPEG_IDLE_TIMEOUT);
131}
132
133void amdgpu_jpeg_ring_begin_use(struct amdgpu_ring *ring)
134{
135 struct amdgpu_device *adev = ring->adev;
136
137 atomic_inc(v: &adev->jpeg.total_submission_cnt);
138 cancel_delayed_work_sync(dwork: &adev->jpeg.idle_work);
139
140 mutex_lock(&adev->jpeg.jpeg_pg_lock);
141 amdgpu_device_ip_set_powergating_state(dev: adev, block_type: AMD_IP_BLOCK_TYPE_JPEG,
142 state: AMD_PG_STATE_UNGATE);
143 mutex_unlock(lock: &adev->jpeg.jpeg_pg_lock);
144}
145
146void amdgpu_jpeg_ring_end_use(struct amdgpu_ring *ring)
147{
148 atomic_dec(v: &ring->adev->jpeg.total_submission_cnt);
149 schedule_delayed_work(dwork: &ring->adev->jpeg.idle_work, JPEG_IDLE_TIMEOUT);
150}
151
152int amdgpu_jpeg_dec_ring_test_ring(struct amdgpu_ring *ring)
153{
154 struct amdgpu_device *adev = ring->adev;
155 uint32_t tmp = 0;
156 unsigned i;
157 int r;
158
159 /* JPEG in SRIOV does not support direct register read/write */
160 if (amdgpu_sriov_vf(adev))
161 return 0;
162
163 r = amdgpu_ring_alloc(ring, ndw: 3);
164 if (r)
165 return r;
166
167 WREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch[ring->pipe], 0xCAFEDEAD);
168 /* Add a read register to make sure the write register is executed. */
169 RREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch[ring->pipe]);
170
171 amdgpu_ring_write(ring, PACKET0(adev->jpeg.internal.jpeg_pitch[ring->pipe], 0));
172 amdgpu_ring_write(ring, v: 0xABADCAFE);
173 amdgpu_ring_commit(ring);
174
175 for (i = 0; i < adev->usec_timeout; i++) {
176 tmp = RREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch[ring->pipe]);
177 if (tmp == 0xABADCAFE)
178 break;
179 udelay(usec: 1);
180 }
181
182 if (i >= adev->usec_timeout)
183 r = -ETIMEDOUT;
184
185 return r;
186}
187
188static int amdgpu_jpeg_dec_set_reg(struct amdgpu_ring *ring, uint32_t handle,
189 struct dma_fence **fence)
190{
191 struct amdgpu_device *adev = ring->adev;
192 struct amdgpu_job *job;
193 struct amdgpu_ib *ib;
194 struct dma_fence *f = NULL;
195 const unsigned ib_size_dw = 16;
196 int i, r;
197
198 r = amdgpu_job_alloc_with_ib(adev: ring->adev, NULL, NULL, size: ib_size_dw * 4,
199 pool_type: AMDGPU_IB_POOL_DIRECT, job: &job,
200 AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST);
201 if (r)
202 return r;
203
204 ib = &job->ibs[0];
205
206 ib->ptr[0] = PACKETJ(adev->jpeg.internal.jpeg_pitch[ring->pipe], 0, 0, PACKETJ_TYPE0);
207 ib->ptr[1] = 0xDEADBEEF;
208 for (i = 2; i < 16; i += 2) {
209 ib->ptr[i] = PACKETJ(0, 0, 0, PACKETJ_TYPE6);
210 ib->ptr[i+1] = 0;
211 }
212 ib->length_dw = 16;
213
214 r = amdgpu_job_submit_direct(job, ring, fence: &f);
215 if (r)
216 goto err;
217
218 if (fence)
219 *fence = dma_fence_get(fence: f);
220 dma_fence_put(fence: f);
221
222 return 0;
223
224err:
225 amdgpu_job_free(job);
226 return r;
227}
228
229int amdgpu_jpeg_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout)
230{
231 struct amdgpu_device *adev = ring->adev;
232 uint32_t tmp = 0;
233 unsigned i;
234 struct dma_fence *fence = NULL;
235 long r = 0;
236
237 r = amdgpu_jpeg_dec_set_reg(ring, handle: 1, fence: &fence);
238 if (r)
239 goto error;
240
241 r = dma_fence_wait_timeout(fence, intr: false, timeout);
242 if (r == 0) {
243 r = -ETIMEDOUT;
244 goto error;
245 } else if (r < 0) {
246 goto error;
247 } else {
248 r = 0;
249 }
250
251 if (!amdgpu_sriov_vf(adev)) {
252 for (i = 0; i < adev->usec_timeout; i++) {
253 tmp = RREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch[ring->pipe]);
254 if (tmp == 0xDEADBEEF)
255 break;
256 udelay(usec: 1);
257 if (amdgpu_emu_mode == 1)
258 udelay(usec: 10);
259 }
260
261 if (i >= adev->usec_timeout)
262 r = -ETIMEDOUT;
263 }
264
265 dma_fence_put(fence);
266error:
267 return r;
268}
269
270int amdgpu_jpeg_process_poison_irq(struct amdgpu_device *adev,
271 struct amdgpu_irq_src *source,
272 struct amdgpu_iv_entry *entry)
273{
274 struct ras_common_if *ras_if = adev->jpeg.ras_if;
275 struct ras_dispatch_if ih_data = {
276 .entry = entry,
277 };
278
279 if (!ras_if)
280 return 0;
281
282 ih_data.head = *ras_if;
283 amdgpu_ras_interrupt_dispatch(adev, info: &ih_data);
284
285 return 0;
286}
287
288int amdgpu_jpeg_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)
289{
290 int r, i;
291
292 r = amdgpu_ras_block_late_init(adev, ras_block);
293 if (r)
294 return r;
295
296 if (amdgpu_ras_is_supported(adev, block: ras_block->block)) {
297 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
298 if (adev->jpeg.harvest_config & (1 << i) ||
299 !adev->jpeg.inst[i].ras_poison_irq.funcs)
300 continue;
301
302 r = amdgpu_irq_get(adev, src: &adev->jpeg.inst[i].ras_poison_irq, type: 0);
303 if (r)
304 goto late_fini;
305 }
306 }
307 return 0;
308
309late_fini:
310 amdgpu_ras_block_late_fini(adev, ras_block);
311 return r;
312}
313
314int amdgpu_jpeg_ras_sw_init(struct amdgpu_device *adev)
315{
316 int err;
317 struct amdgpu_jpeg_ras *ras;
318
319 if (!adev->jpeg.ras)
320 return 0;
321
322 ras = adev->jpeg.ras;
323 err = amdgpu_ras_register_ras_block(adev, ras_block_obj: &ras->ras_block);
324 if (err) {
325 dev_err(adev->dev, "Failed to register jpeg ras block!\n");
326 return err;
327 }
328
329 strcpy(p: ras->ras_block.ras_comm.name, q: "jpeg");
330 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__JPEG;
331 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__POISON;
332 adev->jpeg.ras_if = &ras->ras_block.ras_comm;
333
334 if (!ras->ras_block.ras_late_init)
335 ras->ras_block.ras_late_init = amdgpu_jpeg_ras_late_init;
336
337 return 0;
338}
339
340int amdgpu_jpeg_psp_update_sram(struct amdgpu_device *adev, int inst_idx,
341 enum AMDGPU_UCODE_ID ucode_id)
342{
343 struct amdgpu_firmware_info ucode = {
344 .ucode_id = AMDGPU_UCODE_ID_JPEG_RAM,
345 .mc_addr = adev->jpeg.inst[inst_idx].dpg_sram_gpu_addr,
346 .ucode_size = ((uintptr_t)adev->jpeg.inst[inst_idx].dpg_sram_curr_addr -
347 (uintptr_t)adev->jpeg.inst[inst_idx].dpg_sram_cpu_addr),
348 };
349
350 return psp_execute_ip_fw_load(psp: &adev->psp, ucode: &ucode);
351}
352
353/*
354 * debugfs for to enable/disable jpeg job submission to specific core.
355 */
356#if defined(CONFIG_DEBUG_FS)
357static int amdgpu_debugfs_jpeg_sched_mask_set(void *data, u64 val)
358{
359 struct amdgpu_device *adev = (struct amdgpu_device *)data;
360 u32 i, j;
361 u64 mask = 0;
362 struct amdgpu_ring *ring;
363
364 if (!adev)
365 return -ENODEV;
366
367 mask = (1ULL << (adev->jpeg.num_jpeg_inst * adev->jpeg.num_jpeg_rings)) - 1;
368 if ((val & mask) == 0)
369 return -EINVAL;
370
371 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
372 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {
373 ring = &adev->jpeg.inst[i].ring_dec[j];
374 if (val & (BIT_ULL((i * adev->jpeg.num_jpeg_rings) + j)))
375 ring->sched.ready = true;
376 else
377 ring->sched.ready = false;
378 }
379 }
380 /* publish sched.ready flag update effective immediately across smp */
381 smp_rmb();
382 return 0;
383}
384
385static int amdgpu_debugfs_jpeg_sched_mask_get(void *data, u64 *val)
386{
387 struct amdgpu_device *adev = (struct amdgpu_device *)data;
388 u32 i, j;
389 u64 mask = 0;
390 struct amdgpu_ring *ring;
391
392 if (!adev)
393 return -ENODEV;
394 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
395 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {
396 ring = &adev->jpeg.inst[i].ring_dec[j];
397 if (ring->sched.ready)
398 mask |= 1ULL << ((i * adev->jpeg.num_jpeg_rings) + j);
399 }
400 }
401 *val = mask;
402 return 0;
403}
404
405DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_debugfs_jpeg_sched_mask_fops,
406 amdgpu_debugfs_jpeg_sched_mask_get,
407 amdgpu_debugfs_jpeg_sched_mask_set, "%llx\n");
408
409#endif
410
411void amdgpu_debugfs_jpeg_sched_mask_init(struct amdgpu_device *adev)
412{
413#if defined(CONFIG_DEBUG_FS)
414 struct drm_minor *minor = adev_to_drm(adev)->primary;
415 struct dentry *root = minor->debugfs_root;
416 char name[32];
417
418 if (!(adev->jpeg.num_jpeg_inst > 1) && !(adev->jpeg.num_jpeg_rings > 1))
419 return;
420 sprintf(buf: name, fmt: "amdgpu_jpeg_sched_mask");
421 debugfs_create_file(name, 0600, root, adev,
422 &amdgpu_debugfs_jpeg_sched_mask_fops);
423#endif
424}
425
426static ssize_t amdgpu_get_jpeg_reset_mask(struct device *dev,
427 struct device_attribute *attr,
428 char *buf)
429{
430 struct drm_device *ddev = dev_get_drvdata(dev);
431 struct amdgpu_device *adev = drm_to_adev(ddev);
432
433 if (!adev)
434 return -ENODEV;
435
436 return amdgpu_show_reset_mask(buf, supported_reset: adev->jpeg.supported_reset);
437}
438
439static DEVICE_ATTR(jpeg_reset_mask, 0444,
440 amdgpu_get_jpeg_reset_mask, NULL);
441
442int amdgpu_jpeg_sysfs_reset_mask_init(struct amdgpu_device *adev)
443{
444 int r = 0;
445
446 if (adev->jpeg.num_jpeg_inst) {
447 r = device_create_file(device: adev->dev, entry: &dev_attr_jpeg_reset_mask);
448 if (r)
449 return r;
450 }
451
452 return r;
453}
454
455void amdgpu_jpeg_sysfs_reset_mask_fini(struct amdgpu_device *adev)
456{
457 if (adev->dev->kobj.sd) {
458 if (adev->jpeg.num_jpeg_inst)
459 device_remove_file(dev: adev->dev, attr: &dev_attr_jpeg_reset_mask);
460 }
461}
462
463int amdgpu_jpeg_reg_dump_init(struct amdgpu_device *adev,
464 const struct amdgpu_hwip_reg_entry *reg, u32 count)
465{
466 adev->jpeg.ip_dump = kcalloc(adev->jpeg.num_jpeg_inst * count,
467 sizeof(uint32_t), GFP_KERNEL);
468 if (!adev->jpeg.ip_dump) {
469 dev_err(adev->dev,
470 "Failed to allocate memory for JPEG IP Dump\n");
471 return -ENOMEM;
472 }
473 adev->jpeg.reg_list = reg;
474 adev->jpeg.reg_count = count;
475
476 return 0;
477}
478
479static void amdgpu_jpeg_reg_dump_fini(struct amdgpu_device *adev)
480{
481 kfree(objp: adev->jpeg.ip_dump);
482 adev->jpeg.reg_list = NULL;
483 adev->jpeg.reg_count = 0;
484}
485
486void amdgpu_jpeg_dump_ip_state(struct amdgpu_ip_block *ip_block)
487{
488 struct amdgpu_device *adev = ip_block->adev;
489 u32 inst_off, inst_id, is_powered;
490 int i, j;
491
492 if (!adev->jpeg.ip_dump)
493 return;
494
495 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
496 if (adev->jpeg.harvest_config & (1 << i))
497 continue;
498
499 inst_id = GET_INST(JPEG, i);
500 inst_off = i * adev->jpeg.reg_count;
501 /* check power status from UVD_JPEG_POWER_STATUS */
502 adev->jpeg.ip_dump[inst_off] =
503 RREG32(SOC15_REG_ENTRY_OFFSET_INST(adev->jpeg.reg_list[0],
504 inst_id));
505 is_powered = ((adev->jpeg.ip_dump[inst_off] & 0x1) != 1);
506
507 if (is_powered)
508 for (j = 1; j < adev->jpeg.reg_count; j++)
509 adev->jpeg.ip_dump[inst_off + j] =
510 RREG32(SOC15_REG_ENTRY_OFFSET_INST(adev->jpeg.reg_list[j],
511 inst_id));
512 }
513}
514
515void amdgpu_jpeg_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p)
516{
517 struct amdgpu_device *adev = ip_block->adev;
518 u32 inst_off, is_powered;
519 int i, j;
520
521 if (!adev->jpeg.ip_dump)
522 return;
523
524 drm_printf(p, f: "num_instances:%d\n", adev->jpeg.num_jpeg_inst);
525 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
526 if (adev->jpeg.harvest_config & (1 << i)) {
527 drm_printf(p, f: "\nHarvested Instance:JPEG%d Skipping dump\n", i);
528 continue;
529 }
530
531 inst_off = i * adev->jpeg.reg_count;
532 is_powered = ((adev->jpeg.ip_dump[inst_off] & 0x1) != 1);
533
534 if (is_powered) {
535 drm_printf(p, f: "Active Instance:JPEG%d\n", i);
536 for (j = 0; j < adev->jpeg.reg_count; j++)
537 drm_printf(p, f: "%-50s \t 0x%08x\n", adev->jpeg.reg_list[j].reg_name,
538 adev->jpeg.ip_dump[inst_off + j]);
539 } else
540 drm_printf(p, f: "\nInactive Instance:JPEG%d\n", i);
541 }
542}
543
544static inline bool amdgpu_jpeg_reg_valid(u32 reg)
545{
546 if (reg < JPEG_REG_RANGE_START || reg > JPEG_REG_RANGE_END ||
547 (reg >= JPEG_ATOMIC_RANGE_START && reg <= JPEG_ATOMIC_RANGE_END))
548 return false;
549 else
550 return true;
551}
552
553/**
554 * amdgpu_jpeg_dec_parse_cs - command submission parser
555 *
556 * @parser: Command submission parser context
557 * @job: the job to parse
558 * @ib: the IB to parse
559 *
560 * Parse the command stream, return -EINVAL for invalid packet,
561 * 0 otherwise
562 */
563
564int amdgpu_jpeg_dec_parse_cs(struct amdgpu_cs_parser *parser,
565 struct amdgpu_job *job,
566 struct amdgpu_ib *ib)
567{
568 u32 i, reg, res, cond, type;
569 struct amdgpu_device *adev = parser->adev;
570
571 for (i = 0; i < ib->length_dw ; i += 2) {
572 reg = CP_PACKETJ_GET_REG(ib->ptr[i]);
573 res = CP_PACKETJ_GET_RES(ib->ptr[i]);
574 cond = CP_PACKETJ_GET_COND(ib->ptr[i]);
575 type = CP_PACKETJ_GET_TYPE(ib->ptr[i]);
576
577 if (res) /* only support 0 at the moment */
578 return -EINVAL;
579
580 switch (type) {
581 case PACKETJ_TYPE0:
582 if (cond != PACKETJ_CONDITION_CHECK0 ||
583 !amdgpu_jpeg_reg_valid(reg)) {
584 dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]);
585 return -EINVAL;
586 }
587 break;
588 case PACKETJ_TYPE3:
589 if (cond != PACKETJ_CONDITION_CHECK3 ||
590 !amdgpu_jpeg_reg_valid(reg)) {
591 dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]);
592 return -EINVAL;
593 }
594 break;
595 case PACKETJ_TYPE6:
596 if (ib->ptr[i] == CP_PACKETJ_NOP)
597 continue;
598 dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]);
599 return -EINVAL;
600 default:
601 dev_err(adev->dev, "Unknown packet type %d !\n", type);
602 return -EINVAL;
603 }
604 }
605
606 return 0;
607}
608

source code of linux/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c