1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/ktime.h>
29#include <linux/module.h>
30#include <linux/pagemap.h>
31#include <linux/pci.h>
32#include <linux/dma-buf.h>
33
34#include <drm/amdgpu_drm.h>
35#include <drm/drm_drv.h>
36#include <drm/drm_exec.h>
37#include <drm/drm_gem_ttm_helper.h>
38#include <drm/ttm/ttm_tt.h>
39#include <drm/drm_syncobj.h>
40
41#include "amdgpu.h"
42#include "amdgpu_display.h"
43#include "amdgpu_dma_buf.h"
44#include "amdgpu_hmm.h"
45#include "amdgpu_xgmi.h"
46#include "amdgpu_vm.h"
47
48static int
49amdgpu_gem_add_input_fence(struct drm_file *filp,
50 uint64_t syncobj_handles_array,
51 uint32_t num_syncobj_handles)
52{
53 struct dma_fence *fence;
54 uint32_t *syncobj_handles;
55 int ret, i;
56
57 if (!num_syncobj_handles)
58 return 0;
59
60 syncobj_handles = memdup_user(u64_to_user_ptr(syncobj_handles_array),
61 size_mul(factor1: sizeof(uint32_t), factor2: num_syncobj_handles));
62 if (IS_ERR(ptr: syncobj_handles))
63 return PTR_ERR(ptr: syncobj_handles);
64
65 for (i = 0; i < num_syncobj_handles; i++) {
66
67 if (!syncobj_handles[i]) {
68 ret = -EINVAL;
69 goto free_memdup;
70 }
71
72 ret = drm_syncobj_find_fence(file_private: filp, handle: syncobj_handles[i], point: 0, flags: 0, fence: &fence);
73 if (ret)
74 goto free_memdup;
75
76 dma_fence_wait(fence, intr: false);
77
78 /* TODO: optimize async handling */
79 dma_fence_put(fence);
80 }
81
82free_memdup:
83 kfree(objp: syncobj_handles);
84 return ret;
85}
86
87static int
88amdgpu_gem_update_timeline_node(struct drm_file *filp,
89 uint32_t syncobj_handle,
90 uint64_t point,
91 struct drm_syncobj **syncobj,
92 struct dma_fence_chain **chain)
93{
94 if (!syncobj_handle)
95 return 0;
96
97 /* Find the sync object */
98 *syncobj = drm_syncobj_find(file_private: filp, handle: syncobj_handle);
99 if (!*syncobj)
100 return -ENOENT;
101
102 if (!point)
103 return 0;
104
105 /* Allocate the chain node */
106 *chain = dma_fence_chain_alloc();
107 if (!*chain) {
108 drm_syncobj_put(obj: *syncobj);
109 return -ENOMEM;
110 }
111
112 return 0;
113}
114
115static void
116amdgpu_gem_update_bo_mapping(struct drm_file *filp,
117 struct amdgpu_bo_va *bo_va,
118 uint32_t operation,
119 uint64_t point,
120 struct dma_fence *fence,
121 struct drm_syncobj *syncobj,
122 struct dma_fence_chain *chain)
123{
124 struct amdgpu_bo *bo = bo_va ? bo_va->base.bo : NULL;
125 struct amdgpu_fpriv *fpriv = filp->driver_priv;
126 struct amdgpu_vm *vm = &fpriv->vm;
127 struct dma_fence *last_update;
128
129 if (!syncobj)
130 return;
131
132 /* Find the last update fence */
133 switch (operation) {
134 case AMDGPU_VA_OP_MAP:
135 case AMDGPU_VA_OP_REPLACE:
136 if (bo && (bo->tbo.base.resv == vm->root.bo->tbo.base.resv))
137 last_update = vm->last_update;
138 else
139 last_update = bo_va->last_pt_update;
140 break;
141 case AMDGPU_VA_OP_UNMAP:
142 case AMDGPU_VA_OP_CLEAR:
143 last_update = fence;
144 break;
145 default:
146 return;
147 }
148
149 /* Add fence to timeline */
150 if (!point)
151 drm_syncobj_replace_fence(syncobj, fence: last_update);
152 else
153 drm_syncobj_add_point(syncobj, chain, fence: last_update, point);
154}
155
156static vm_fault_t amdgpu_gem_fault(struct vm_fault *vmf)
157{
158 struct ttm_buffer_object *bo = vmf->vma->vm_private_data;
159 struct drm_device *ddev = bo->base.dev;
160 vm_fault_t ret;
161 int idx;
162
163 ret = ttm_bo_vm_reserve(bo, vmf);
164 if (ret)
165 return ret;
166
167 if (drm_dev_enter(dev: ddev, idx: &idx)) {
168 ret = amdgpu_bo_fault_reserve_notify(bo);
169 if (ret) {
170 drm_dev_exit(idx);
171 goto unlock;
172 }
173
174 ret = ttm_bo_vm_fault_reserved(vmf, prot: vmf->vma->vm_page_prot,
175 TTM_BO_VM_NUM_PREFAULT);
176
177 drm_dev_exit(idx);
178 } else {
179 ret = ttm_bo_vm_dummy_page(vmf, prot: vmf->vma->vm_page_prot);
180 }
181 if (ret == VM_FAULT_RETRY && !(vmf->flags & FAULT_FLAG_RETRY_NOWAIT))
182 return ret;
183
184unlock:
185 dma_resv_unlock(obj: bo->base.resv);
186 return ret;
187}
188
189static const struct vm_operations_struct amdgpu_gem_vm_ops = {
190 .fault = amdgpu_gem_fault,
191 .open = ttm_bo_vm_open,
192 .close = ttm_bo_vm_close,
193 .access = ttm_bo_vm_access
194};
195
196static void amdgpu_gem_object_free(struct drm_gem_object *gobj)
197{
198 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(gobj);
199
200 amdgpu_hmm_unregister(bo: aobj);
201 ttm_bo_fini(bo: &aobj->tbo);
202}
203
204int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
205 int alignment, u32 initial_domain,
206 u64 flags, enum ttm_bo_type type,
207 struct dma_resv *resv,
208 struct drm_gem_object **obj, int8_t xcp_id_plus1)
209{
210 struct amdgpu_bo *bo;
211 struct amdgpu_bo_user *ubo;
212 struct amdgpu_bo_param bp;
213 int r;
214
215 memset(&bp, 0, sizeof(bp));
216 *obj = NULL;
217 flags |= AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE;
218
219 bp.size = size;
220 bp.byte_align = alignment;
221 bp.type = type;
222 bp.resv = resv;
223 bp.preferred_domain = initial_domain;
224 bp.flags = flags;
225 bp.domain = initial_domain;
226 bp.bo_ptr_size = sizeof(struct amdgpu_bo);
227 bp.xcp_id_plus1 = xcp_id_plus1;
228
229 r = amdgpu_bo_create_user(adev, bp: &bp, ubo_ptr: &ubo);
230 if (r)
231 return r;
232
233 bo = &ubo->bo;
234 *obj = &bo->tbo.base;
235
236 return 0;
237}
238
239void amdgpu_gem_force_release(struct amdgpu_device *adev)
240{
241 struct drm_device *ddev = adev_to_drm(adev);
242 struct drm_file *file;
243
244 mutex_lock(&ddev->filelist_mutex);
245
246 list_for_each_entry(file, &ddev->filelist, lhead) {
247 struct drm_gem_object *gobj;
248 int handle;
249
250 WARN_ONCE(1, "Still active user space clients!\n");
251 spin_lock(lock: &file->table_lock);
252 idr_for_each_entry(&file->object_idr, gobj, handle) {
253 WARN_ONCE(1, "And also active allocations!\n");
254 drm_gem_object_put(obj: gobj);
255 }
256 idr_destroy(&file->object_idr);
257 spin_unlock(lock: &file->table_lock);
258 }
259
260 mutex_unlock(lock: &ddev->filelist_mutex);
261}
262
263/*
264 * Call from drm_gem_handle_create which appear in both new and open ioctl
265 * case.
266 */
267static int amdgpu_gem_object_open(struct drm_gem_object *obj,
268 struct drm_file *file_priv)
269{
270 struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj);
271 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev: abo->tbo.bdev);
272 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
273 struct amdgpu_vm *vm = &fpriv->vm;
274 struct amdgpu_bo_va *bo_va;
275 struct mm_struct *mm;
276 int r;
277
278 mm = amdgpu_ttm_tt_get_usermm(ttm: abo->tbo.ttm);
279 if (mm && mm != current->mm)
280 return -EPERM;
281
282 if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID &&
283 !amdgpu_vm_is_bo_always_valid(vm, bo: abo))
284 return -EPERM;
285
286 r = amdgpu_bo_reserve(bo: abo, no_intr: false);
287 if (r)
288 return r;
289
290 amdgpu_vm_bo_update_shared(bo: abo);
291 bo_va = amdgpu_vm_bo_find(vm, bo: abo);
292 if (!bo_va)
293 bo_va = amdgpu_vm_bo_add(adev, vm, bo: abo);
294 else
295 ++bo_va->ref_count;
296
297 /* attach gfx eviction fence */
298 r = amdgpu_eviction_fence_attach(evf_mgr: &fpriv->evf_mgr, bo: abo);
299 if (r) {
300 DRM_DEBUG_DRIVER("Failed to attach eviction fence to BO\n");
301 amdgpu_bo_unreserve(bo: abo);
302 return r;
303 }
304
305 amdgpu_bo_unreserve(bo: abo);
306
307 /* Validate and add eviction fence to DMABuf imports with dynamic
308 * attachment in compute VMs. Re-validation will be done by
309 * amdgpu_vm_validate. Fences are on the reservation shared with the
310 * export, which is currently required to be validated and fenced
311 * already by amdgpu_amdkfd_gpuvm_restore_process_bos.
312 *
313 * Nested locking below for the case that a GEM object is opened in
314 * kfd_mem_export_dmabuf. Since the lock below is only taken for imports,
315 * but not for export, this is a different lock class that cannot lead to
316 * circular lock dependencies.
317 */
318 if (!vm->is_compute_context || !vm->process_info)
319 return 0;
320 if (!drm_gem_is_imported(obj) ||
321 !dma_buf_is_dynamic(dmabuf: obj->import_attach->dmabuf))
322 return 0;
323 mutex_lock_nested(lock: &vm->process_info->lock, subclass: 1);
324 if (!WARN_ON(!vm->process_info->eviction_fence)) {
325 r = amdgpu_amdkfd_bo_validate_and_fence(bo: abo, AMDGPU_GEM_DOMAIN_GTT,
326 fence: &vm->process_info->eviction_fence->base);
327 if (r) {
328 struct amdgpu_task_info *ti = amdgpu_vm_get_task_info_vm(vm);
329
330 dev_warn(adev->dev, "validate_and_fence failed: %d\n", r);
331 if (ti) {
332 dev_warn(adev->dev, "pid %d\n", ti->task.pid);
333 amdgpu_vm_put_task_info(task_info: ti);
334 }
335 }
336 }
337 mutex_unlock(lock: &vm->process_info->lock);
338
339 return r;
340}
341
342static void amdgpu_gem_object_close(struct drm_gem_object *obj,
343 struct drm_file *file_priv)
344{
345 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
346 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev: bo->tbo.bdev);
347 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
348 struct amdgpu_vm *vm = &fpriv->vm;
349
350 struct dma_fence *fence = NULL;
351 struct amdgpu_bo_va *bo_va;
352 struct drm_exec exec;
353 long r;
354
355 drm_exec_init(exec: &exec, DRM_EXEC_IGNORE_DUPLICATES, nr: 0);
356 drm_exec_until_all_locked(&exec) {
357 r = drm_exec_prepare_obj(exec: &exec, obj: &bo->tbo.base, num_fences: 1);
358 drm_exec_retry_on_contention(&exec);
359 if (unlikely(r))
360 goto out_unlock;
361
362 r = amdgpu_vm_lock_pd(vm, exec: &exec, num_fences: 0);
363 drm_exec_retry_on_contention(&exec);
364 if (unlikely(r))
365 goto out_unlock;
366 }
367
368 if (!amdgpu_vm_is_bo_always_valid(vm, bo))
369 amdgpu_eviction_fence_detach(evf_mgr: &fpriv->evf_mgr, bo);
370
371 bo_va = amdgpu_vm_bo_find(vm, bo);
372 if (!bo_va || --bo_va->ref_count)
373 goto out_unlock;
374
375 amdgpu_vm_bo_del(adev, bo_va);
376 amdgpu_vm_bo_update_shared(bo);
377 if (!amdgpu_vm_ready(vm))
378 goto out_unlock;
379
380 r = amdgpu_vm_clear_freed(adev, vm, fence: &fence);
381 if (unlikely(r < 0))
382 dev_err(adev->dev, "failed to clear page "
383 "tables on GEM object close (%ld)\n", r);
384 if (r || !fence)
385 goto out_unlock;
386
387 amdgpu_bo_fence(bo, fence, shared: true);
388 dma_fence_put(fence);
389
390out_unlock:
391 if (r)
392 dev_err(adev->dev, "leaking bo va (%ld)\n", r);
393 drm_exec_fini(exec: &exec);
394}
395
396static int amdgpu_gem_object_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma)
397{
398 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
399
400 if (amdgpu_ttm_tt_get_usermm(ttm: bo->tbo.ttm))
401 return -EPERM;
402 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
403 return -EPERM;
404
405 /* Workaround for Thunk bug creating PROT_NONE,MAP_PRIVATE mappings
406 * for debugger access to invisible VRAM. Should have used MAP_SHARED
407 * instead. Clearing VM_MAYWRITE prevents the mapping from ever
408 * becoming writable and makes is_cow_mapping(vm_flags) false.
409 */
410 if (is_cow_mapping(flags: vma->vm_flags) &&
411 !(vma->vm_flags & VM_ACCESS_FLAGS))
412 vm_flags_clear(vma, VM_MAYWRITE);
413
414 return drm_gem_ttm_mmap(gem: obj, vma);
415}
416
417const struct drm_gem_object_funcs amdgpu_gem_object_funcs = {
418 .free = amdgpu_gem_object_free,
419 .open = amdgpu_gem_object_open,
420 .close = amdgpu_gem_object_close,
421 .export = amdgpu_gem_prime_export,
422 .vmap = drm_gem_ttm_vmap,
423 .vunmap = drm_gem_ttm_vunmap,
424 .mmap = amdgpu_gem_object_mmap,
425 .vm_ops = &amdgpu_gem_vm_ops,
426};
427
428/*
429 * GEM ioctls.
430 */
431int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
432 struct drm_file *filp)
433{
434 struct amdgpu_device *adev = drm_to_adev(ddev: dev);
435 struct amdgpu_fpriv *fpriv = filp->driver_priv;
436 struct amdgpu_vm *vm = &fpriv->vm;
437 union drm_amdgpu_gem_create *args = data;
438 uint64_t flags = args->in.domain_flags;
439 uint64_t size = args->in.bo_size;
440 struct dma_resv *resv = NULL;
441 struct drm_gem_object *gobj;
442 uint32_t handle, initial_domain;
443 int r;
444
445 /* reject invalid gem flags */
446 if (flags & ~AMDGPU_GEM_CREATE_SETTABLE_MASK)
447 return -EINVAL;
448
449 /* reject invalid gem domains */
450 if (args->in.domains & ~AMDGPU_GEM_DOMAIN_MASK)
451 return -EINVAL;
452
453 if (!amdgpu_is_tmz(adev) && (flags & AMDGPU_GEM_CREATE_ENCRYPTED)) {
454 DRM_NOTE_ONCE("Cannot allocate secure buffer since TMZ is disabled\n");
455 return -EINVAL;
456 }
457
458 /* always clear VRAM */
459 flags |= AMDGPU_GEM_CREATE_VRAM_CLEARED;
460
461 if (args->in.domains & AMDGPU_GEM_DOMAIN_MMIO_REMAP)
462 return -EINVAL;
463
464 /* create a gem object to contain this object in */
465 if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS |
466 AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
467 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
468 /* if gds bo is created from user space, it must be
469 * passed to bo list
470 */
471 DRM_ERROR("GDS bo cannot be per-vm-bo\n");
472 return -EINVAL;
473 }
474 flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
475 }
476
477 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
478 r = amdgpu_bo_reserve(bo: vm->root.bo, no_intr: false);
479 if (r)
480 return r;
481
482 resv = vm->root.bo->tbo.base.resv;
483 }
484
485 initial_domain = (u32)(0xffffffff & args->in.domains);
486retry:
487 r = amdgpu_gem_object_create(adev, size, alignment: args->in.alignment,
488 initial_domain,
489 flags, type: ttm_bo_type_device, resv, obj: &gobj, xcp_id_plus1: fpriv->xcp_id + 1);
490 if (r && r != -ERESTARTSYS) {
491 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) {
492 flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
493 goto retry;
494 }
495
496 if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) {
497 initial_domain |= AMDGPU_GEM_DOMAIN_GTT;
498 goto retry;
499 }
500 DRM_DEBUG("Failed to allocate GEM object (%llu, %d, %llu, %d)\n",
501 size, initial_domain, args->in.alignment, r);
502 }
503
504 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
505 if (!r) {
506 struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
507
508 abo->parent = amdgpu_bo_ref(bo: vm->root.bo);
509 }
510 amdgpu_bo_unreserve(bo: vm->root.bo);
511 }
512 if (r)
513 return r;
514
515 r = drm_gem_handle_create(file_priv: filp, obj: gobj, handlep: &handle);
516 /* drop reference from allocate - handle holds it now */
517 drm_gem_object_put(obj: gobj);
518 if (r)
519 return r;
520
521 memset(args, 0, sizeof(*args));
522 args->out.handle = handle;
523 return 0;
524}
525
526int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
527 struct drm_file *filp)
528{
529 struct ttm_operation_ctx ctx = { true, false };
530 struct amdgpu_device *adev = drm_to_adev(ddev: dev);
531 struct drm_amdgpu_gem_userptr *args = data;
532 struct amdgpu_fpriv *fpriv = filp->driver_priv;
533 struct drm_gem_object *gobj;
534 struct amdgpu_hmm_range *range;
535 struct amdgpu_bo *bo;
536 uint32_t handle;
537 int r;
538
539 args->addr = untagged_addr(args->addr);
540
541 if (offset_in_page(args->addr | args->size))
542 return -EINVAL;
543
544 /* reject unknown flag values */
545 if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY |
546 AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE |
547 AMDGPU_GEM_USERPTR_REGISTER))
548 return -EINVAL;
549
550 if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) &&
551 !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) {
552
553 /* if we want to write to it we must install a MMU notifier */
554 return -EACCES;
555 }
556
557 /* create a gem object to contain this object in */
558 r = amdgpu_gem_object_create(adev, size: args->size, alignment: 0, AMDGPU_GEM_DOMAIN_CPU,
559 flags: 0, type: ttm_bo_type_device, NULL, obj: &gobj, xcp_id_plus1: fpriv->xcp_id + 1);
560 if (r)
561 return r;
562
563 bo = gem_to_amdgpu_bo(gobj);
564 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;
565 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
566 r = amdgpu_ttm_tt_set_userptr(bo: &bo->tbo, addr: args->addr, flags: args->flags);
567 if (r)
568 goto release_object;
569
570 r = amdgpu_hmm_register(bo, addr: args->addr);
571 if (r)
572 goto release_object;
573
574 if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) {
575 range = amdgpu_hmm_range_alloc(NULL);
576 if (unlikely(!range))
577 return -ENOMEM;
578 r = amdgpu_ttm_tt_get_user_pages(bo, range);
579 if (r) {
580 amdgpu_hmm_range_free(range);
581 goto release_object;
582 }
583 r = amdgpu_bo_reserve(bo, no_intr: true);
584 if (r)
585 goto user_pages_done;
586
587 amdgpu_ttm_tt_set_user_pages(ttm: bo->tbo.ttm, range);
588
589 amdgpu_bo_placement_from_domain(abo: bo, AMDGPU_GEM_DOMAIN_GTT);
590 r = ttm_bo_validate(bo: &bo->tbo, placement: &bo->placement, ctx: &ctx);
591 amdgpu_bo_unreserve(bo);
592 if (r)
593 goto user_pages_done;
594 }
595
596 r = drm_gem_handle_create(file_priv: filp, obj: gobj, handlep: &handle);
597 if (r)
598 goto user_pages_done;
599
600 args->handle = handle;
601
602user_pages_done:
603 if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE)
604 amdgpu_hmm_range_free(range);
605release_object:
606 drm_gem_object_put(obj: gobj);
607
608 return r;
609}
610
611int amdgpu_mode_dumb_mmap(struct drm_file *filp,
612 struct drm_device *dev,
613 uint32_t handle, uint64_t *offset_p)
614{
615 struct drm_gem_object *gobj;
616 struct amdgpu_bo *robj;
617
618 gobj = drm_gem_object_lookup(filp, handle);
619 if (!gobj)
620 return -ENOENT;
621
622 robj = gem_to_amdgpu_bo(gobj);
623 if (amdgpu_ttm_tt_get_usermm(ttm: robj->tbo.ttm) ||
624 (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) {
625 drm_gem_object_put(obj: gobj);
626 return -EPERM;
627 }
628 *offset_p = amdgpu_bo_mmap_offset(bo: robj);
629 drm_gem_object_put(obj: gobj);
630 return 0;
631}
632
633int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
634 struct drm_file *filp)
635{
636 union drm_amdgpu_gem_mmap *args = data;
637 uint32_t handle = args->in.handle;
638
639 memset(args, 0, sizeof(*args));
640 return amdgpu_mode_dumb_mmap(filp, dev, handle, offset_p: &args->out.addr_ptr);
641}
642
643/**
644 * amdgpu_gem_timeout - calculate jiffies timeout from absolute value
645 *
646 * @timeout_ns: timeout in ns
647 *
648 * Calculate the timeout in jiffies from an absolute timeout in ns.
649 */
650unsigned long amdgpu_gem_timeout(uint64_t timeout_ns)
651{
652 unsigned long timeout_jiffies;
653 ktime_t timeout;
654
655 /* clamp timeout if it's to large */
656 if (((int64_t)timeout_ns) < 0)
657 return MAX_SCHEDULE_TIMEOUT;
658
659 timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get());
660 if (ktime_to_ns(kt: timeout) < 0)
661 return 0;
662
663 timeout_jiffies = nsecs_to_jiffies(n: ktime_to_ns(kt: timeout));
664 /* clamp timeout to avoid unsigned-> signed overflow */
665 if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT)
666 return MAX_SCHEDULE_TIMEOUT - 1;
667
668 return timeout_jiffies;
669}
670
671int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
672 struct drm_file *filp)
673{
674 union drm_amdgpu_gem_wait_idle *args = data;
675 struct drm_gem_object *gobj;
676 struct amdgpu_bo *robj;
677 uint32_t handle = args->in.handle;
678 unsigned long timeout = amdgpu_gem_timeout(timeout_ns: args->in.timeout);
679 int r = 0;
680 long ret;
681
682 gobj = drm_gem_object_lookup(filp, handle);
683 if (!gobj)
684 return -ENOENT;
685
686 robj = gem_to_amdgpu_bo(gobj);
687 ret = dma_resv_wait_timeout(obj: robj->tbo.base.resv, usage: DMA_RESV_USAGE_READ,
688 intr: true, timeout);
689
690 /* ret == 0 means not signaled,
691 * ret > 0 means signaled
692 * ret < 0 means interrupted before timeout
693 */
694 if (ret >= 0) {
695 memset(args, 0, sizeof(*args));
696 args->out.status = (ret == 0);
697 } else
698 r = ret;
699
700 drm_gem_object_put(obj: gobj);
701 return r;
702}
703
704int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
705 struct drm_file *filp)
706{
707 struct drm_amdgpu_gem_metadata *args = data;
708 struct drm_gem_object *gobj;
709 struct amdgpu_bo *robj;
710 int r = -1;
711
712 DRM_DEBUG("%d\n", args->handle);
713 gobj = drm_gem_object_lookup(filp, handle: args->handle);
714 if (gobj == NULL)
715 return -ENOENT;
716 robj = gem_to_amdgpu_bo(gobj);
717
718 r = amdgpu_bo_reserve(bo: robj, no_intr: false);
719 if (unlikely(r != 0))
720 goto out;
721
722 if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) {
723 amdgpu_bo_get_tiling_flags(bo: robj, tiling_flags: &args->data.tiling_info);
724 r = amdgpu_bo_get_metadata(bo: robj, buffer: args->data.data,
725 buffer_size: sizeof(args->data.data),
726 metadata_size: &args->data.data_size_bytes,
727 flags: &args->data.flags);
728 } else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) {
729 if (args->data.data_size_bytes > sizeof(args->data.data)) {
730 r = -EINVAL;
731 goto unreserve;
732 }
733 r = amdgpu_bo_set_tiling_flags(bo: robj, tiling_flags: args->data.tiling_info);
734 if (!r)
735 r = amdgpu_bo_set_metadata(bo: robj, metadata: args->data.data,
736 metadata_size: args->data.data_size_bytes,
737 flags: args->data.flags);
738 }
739
740unreserve:
741 amdgpu_bo_unreserve(bo: robj);
742out:
743 drm_gem_object_put(obj: gobj);
744 return r;
745}
746
747/**
748 * amdgpu_gem_va_update_vm -update the bo_va in its VM
749 *
750 * @adev: amdgpu_device pointer
751 * @vm: vm to update
752 * @bo_va: bo_va to update
753 * @operation: map, unmap or clear
754 *
755 * Update the bo_va directly after setting its address. Errors are not
756 * vital here, so they are not reported back to userspace.
757 *
758 * Returns resulting fence if freed BO(s) got cleared from the PT.
759 * otherwise stub fence in case of error.
760 */
761static struct dma_fence *
762amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
763 struct amdgpu_vm *vm,
764 struct amdgpu_bo_va *bo_va,
765 uint32_t operation)
766{
767 struct dma_fence *fence = dma_fence_get_stub();
768 int r;
769
770 if (!amdgpu_vm_ready(vm))
771 return fence;
772
773 r = amdgpu_vm_clear_freed(adev, vm, fence: &fence);
774 if (r)
775 goto error;
776
777 if (operation == AMDGPU_VA_OP_MAP ||
778 operation == AMDGPU_VA_OP_REPLACE) {
779 r = amdgpu_vm_bo_update(adev, bo_va, clear: false);
780 if (r)
781 goto error;
782 }
783
784 r = amdgpu_vm_update_pdes(adev, vm, immediate: false);
785
786error:
787 if (r && r != -ERESTARTSYS)
788 DRM_ERROR("Couldn't update BO_VA (%d)\n", r);
789
790 return fence;
791}
792
793int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
794 struct drm_file *filp)
795{
796 const uint32_t valid_flags = AMDGPU_VM_DELAY_UPDATE |
797 AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE |
798 AMDGPU_VM_PAGE_EXECUTABLE | AMDGPU_VM_MTYPE_MASK |
799 AMDGPU_VM_PAGE_NOALLOC;
800 const uint32_t prt_flags = AMDGPU_VM_DELAY_UPDATE |
801 AMDGPU_VM_PAGE_PRT;
802
803 struct drm_amdgpu_gem_va *args = data;
804 struct drm_gem_object *gobj;
805 struct amdgpu_device *adev = drm_to_adev(ddev: dev);
806 struct amdgpu_fpriv *fpriv = filp->driver_priv;
807 struct amdgpu_bo *abo;
808 struct amdgpu_bo_va *bo_va;
809 struct drm_syncobj *timeline_syncobj = NULL;
810 struct dma_fence_chain *timeline_chain = NULL;
811 struct dma_fence *fence;
812 struct drm_exec exec;
813 uint64_t vm_size;
814 int r = 0;
815
816 if (args->va_address < AMDGPU_VA_RESERVED_BOTTOM) {
817 dev_dbg(dev->dev,
818 "va_address 0x%llx is in reserved area 0x%llx\n",
819 args->va_address, AMDGPU_VA_RESERVED_BOTTOM);
820 return -EINVAL;
821 }
822
823 if (args->va_address >= AMDGPU_GMC_HOLE_START &&
824 args->va_address < AMDGPU_GMC_HOLE_END) {
825 dev_dbg(dev->dev,
826 "va_address 0x%llx is in VA hole 0x%llx-0x%llx\n",
827 args->va_address, AMDGPU_GMC_HOLE_START,
828 AMDGPU_GMC_HOLE_END);
829 return -EINVAL;
830 }
831
832 args->va_address &= AMDGPU_GMC_HOLE_MASK;
833
834 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
835 vm_size -= AMDGPU_VA_RESERVED_TOP;
836 if (args->va_address + args->map_size > vm_size) {
837 dev_dbg(dev->dev,
838 "va_address 0x%llx is in top reserved area 0x%llx\n",
839 args->va_address + args->map_size, vm_size);
840 return -EINVAL;
841 }
842
843 if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) {
844 dev_dbg(dev->dev, "invalid flags combination 0x%08X\n",
845 args->flags);
846 return -EINVAL;
847 }
848
849 switch (args->operation) {
850 case AMDGPU_VA_OP_MAP:
851 case AMDGPU_VA_OP_UNMAP:
852 case AMDGPU_VA_OP_CLEAR:
853 case AMDGPU_VA_OP_REPLACE:
854 break;
855 default:
856 dev_dbg(dev->dev, "unsupported operation %d\n",
857 args->operation);
858 return -EINVAL;
859 }
860
861 if ((args->operation != AMDGPU_VA_OP_CLEAR) &&
862 !(args->flags & AMDGPU_VM_PAGE_PRT)) {
863 gobj = drm_gem_object_lookup(filp, handle: args->handle);
864 if (gobj == NULL)
865 return -ENOENT;
866 abo = gem_to_amdgpu_bo(gobj);
867 } else {
868 gobj = NULL;
869 abo = NULL;
870 }
871
872 r = amdgpu_gem_add_input_fence(filp,
873 syncobj_handles_array: args->input_fence_syncobj_handles,
874 num_syncobj_handles: args->num_syncobj_handles);
875 if (r)
876 goto error_put_gobj;
877
878 drm_exec_init(exec: &exec, DRM_EXEC_INTERRUPTIBLE_WAIT |
879 DRM_EXEC_IGNORE_DUPLICATES, nr: 0);
880 drm_exec_until_all_locked(&exec) {
881 if (gobj) {
882 r = drm_exec_lock_obj(exec: &exec, obj: gobj);
883 drm_exec_retry_on_contention(&exec);
884 if (unlikely(r))
885 goto error;
886 }
887
888 r = amdgpu_vm_lock_pd(vm: &fpriv->vm, exec: &exec, num_fences: 2);
889 drm_exec_retry_on_contention(&exec);
890 if (unlikely(r))
891 goto error;
892 }
893
894 if (abo) {
895 bo_va = amdgpu_vm_bo_find(vm: &fpriv->vm, bo: abo);
896 if (!bo_va) {
897 r = -ENOENT;
898 goto error;
899 }
900 } else if (args->operation != AMDGPU_VA_OP_CLEAR) {
901 bo_va = fpriv->prt_va;
902 } else {
903 bo_va = NULL;
904 }
905
906 r = amdgpu_gem_update_timeline_node(filp,
907 syncobj_handle: args->vm_timeline_syncobj_out,
908 point: args->vm_timeline_point,
909 syncobj: &timeline_syncobj,
910 chain: &timeline_chain);
911 if (r)
912 goto error;
913
914 switch (args->operation) {
915 case AMDGPU_VA_OP_MAP:
916 r = amdgpu_vm_bo_map(adev, bo_va, addr: args->va_address,
917 offset: args->offset_in_bo, size: args->map_size,
918 flags: args->flags);
919 break;
920 case AMDGPU_VA_OP_UNMAP:
921 r = amdgpu_vm_bo_unmap(adev, bo_va, addr: args->va_address);
922 break;
923
924 case AMDGPU_VA_OP_CLEAR:
925 r = amdgpu_vm_bo_clear_mappings(adev, vm: &fpriv->vm,
926 saddr: args->va_address,
927 size: args->map_size);
928 break;
929 case AMDGPU_VA_OP_REPLACE:
930 r = amdgpu_vm_bo_replace_map(adev, bo_va, addr: args->va_address,
931 offset: args->offset_in_bo, size: args->map_size,
932 flags: args->flags);
933 break;
934 default:
935 break;
936 }
937 if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && !adev->debug_vm) {
938 fence = amdgpu_gem_va_update_vm(adev, vm: &fpriv->vm, bo_va,
939 operation: args->operation);
940
941 if (timeline_syncobj)
942 amdgpu_gem_update_bo_mapping(filp, bo_va,
943 operation: args->operation,
944 point: args->vm_timeline_point,
945 fence, syncobj: timeline_syncobj,
946 chain: timeline_chain);
947 else
948 dma_fence_put(fence);
949
950 }
951
952error:
953 drm_exec_fini(exec: &exec);
954error_put_gobj:
955 drm_gem_object_put(obj: gobj);
956 return r;
957}
958
959int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
960 struct drm_file *filp)
961{
962 struct drm_amdgpu_gem_op *args = data;
963 struct drm_gem_object *gobj;
964 struct amdgpu_vm_bo_base *base;
965 struct amdgpu_bo *robj;
966 struct drm_exec exec;
967 struct amdgpu_fpriv *fpriv = filp->driver_priv;
968 int r;
969
970 if (args->padding)
971 return -EINVAL;
972
973 gobj = drm_gem_object_lookup(filp, handle: args->handle);
974 if (!gobj)
975 return -ENOENT;
976
977 robj = gem_to_amdgpu_bo(gobj);
978
979 drm_exec_init(exec: &exec, DRM_EXEC_INTERRUPTIBLE_WAIT |
980 DRM_EXEC_IGNORE_DUPLICATES, nr: 0);
981 drm_exec_until_all_locked(&exec) {
982 r = drm_exec_lock_obj(exec: &exec, obj: gobj);
983 drm_exec_retry_on_contention(&exec);
984 if (r)
985 goto out_exec;
986
987 if (args->op == AMDGPU_GEM_OP_GET_MAPPING_INFO) {
988 r = amdgpu_vm_lock_pd(vm: &fpriv->vm, exec: &exec, num_fences: 0);
989 drm_exec_retry_on_contention(&exec);
990 if (r)
991 goto out_exec;
992 }
993 }
994
995 switch (args->op) {
996 case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: {
997 struct drm_amdgpu_gem_create_in info;
998 void __user *out = u64_to_user_ptr(args->value);
999
1000 info.bo_size = robj->tbo.base.size;
1001 info.alignment = robj->tbo.page_alignment << PAGE_SHIFT;
1002 info.domains = robj->preferred_domains;
1003 info.domain_flags = robj->flags;
1004 drm_exec_fini(exec: &exec);
1005 if (copy_to_user(to: out, from: &info, n: sizeof(info)))
1006 r = -EFAULT;
1007 break;
1008 }
1009 case AMDGPU_GEM_OP_SET_PLACEMENT:
1010 if (drm_gem_is_imported(obj: &robj->tbo.base) &&
1011 args->value & AMDGPU_GEM_DOMAIN_VRAM) {
1012 r = -EINVAL;
1013 goto out_exec;
1014 }
1015 if (amdgpu_ttm_tt_get_usermm(ttm: robj->tbo.ttm)) {
1016 r = -EPERM;
1017 goto out_exec;
1018 }
1019 for (base = robj->vm_bo; base; base = base->next)
1020 if (amdgpu_xgmi_same_hive(adev: amdgpu_ttm_adev(bdev: robj->tbo.bdev),
1021 bo_adev: amdgpu_ttm_adev(bdev: base->vm->root.bo->tbo.bdev))) {
1022 r = -EINVAL;
1023 goto out_exec;
1024 }
1025
1026
1027 robj->preferred_domains = args->value & (AMDGPU_GEM_DOMAIN_VRAM |
1028 AMDGPU_GEM_DOMAIN_GTT |
1029 AMDGPU_GEM_DOMAIN_CPU);
1030 robj->allowed_domains = robj->preferred_domains;
1031 if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
1032 robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
1033
1034 if (robj->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)
1035 amdgpu_vm_bo_invalidate(bo: robj, evicted: true);
1036 drm_exec_fini(exec: &exec);
1037 break;
1038 case AMDGPU_GEM_OP_GET_MAPPING_INFO: {
1039 struct amdgpu_bo_va *bo_va = amdgpu_vm_bo_find(vm: &fpriv->vm, bo: robj);
1040 struct drm_amdgpu_gem_vm_entry *vm_entries;
1041 struct amdgpu_bo_va_mapping *mapping;
1042 int num_mappings = 0;
1043 /*
1044 * num_entries is set as an input to the size of the user-allocated array of
1045 * drm_amdgpu_gem_vm_entry stored at args->value.
1046 * num_entries is sent back as output as the number of mappings the bo has.
1047 * If that number is larger than the size of the array, the ioctl must
1048 * be retried.
1049 */
1050 vm_entries = kvcalloc(args->num_entries, sizeof(*vm_entries), GFP_KERNEL);
1051 if (!vm_entries)
1052 return -ENOMEM;
1053
1054 amdgpu_vm_bo_va_for_each_valid_mapping(bo_va, mapping) {
1055 if (num_mappings < args->num_entries) {
1056 vm_entries[num_mappings].addr = mapping->start * AMDGPU_GPU_PAGE_SIZE;
1057 vm_entries[num_mappings].size = (mapping->last - mapping->start + 1) * AMDGPU_GPU_PAGE_SIZE;
1058 vm_entries[num_mappings].offset = mapping->offset;
1059 vm_entries[num_mappings].flags = mapping->flags;
1060 }
1061 num_mappings += 1;
1062 }
1063
1064 amdgpu_vm_bo_va_for_each_invalid_mapping(bo_va, mapping) {
1065 if (num_mappings < args->num_entries) {
1066 vm_entries[num_mappings].addr = mapping->start * AMDGPU_GPU_PAGE_SIZE;
1067 vm_entries[num_mappings].size = (mapping->last - mapping->start + 1) * AMDGPU_GPU_PAGE_SIZE;
1068 vm_entries[num_mappings].offset = mapping->offset;
1069 vm_entries[num_mappings].flags = mapping->flags;
1070 }
1071 num_mappings += 1;
1072 }
1073
1074 drm_exec_fini(exec: &exec);
1075
1076 if (num_mappings > 0 && num_mappings <= args->num_entries)
1077 if (copy_to_user(u64_to_user_ptr(args->value), from: vm_entries, n: num_mappings * sizeof(*vm_entries)))
1078 r = -EFAULT;
1079
1080 args->num_entries = num_mappings;
1081
1082 kvfree(addr: vm_entries);
1083 break;
1084 }
1085 default:
1086 drm_exec_fini(exec: &exec);
1087 r = -EINVAL;
1088 }
1089
1090 drm_gem_object_put(obj: gobj);
1091 return r;
1092out_exec:
1093 drm_exec_fini(exec: &exec);
1094 drm_gem_object_put(obj: gobj);
1095 return r;
1096}
1097
1098/**
1099 * amdgpu_gem_list_handles_ioctl - get information about a process' buffer objects
1100 *
1101 * @dev: drm device pointer
1102 * @data: drm_amdgpu_gem_list_handles
1103 * @filp: drm file pointer
1104 *
1105 * num_entries is set as an input to the size of the entries array.
1106 * num_entries is sent back as output as the number of bos in the process.
1107 * If that number is larger than the size of the array, the ioctl must
1108 * be retried.
1109 *
1110 * Returns:
1111 * 0 for success, -errno for errors.
1112 */
1113int amdgpu_gem_list_handles_ioctl(struct drm_device *dev, void *data,
1114 struct drm_file *filp)
1115{
1116 struct drm_amdgpu_gem_list_handles *args = data;
1117 struct drm_amdgpu_gem_list_handles_entry *bo_entries;
1118 struct drm_gem_object *gobj;
1119 int id, ret = 0;
1120 int bo_index = 0;
1121 int num_bos = 0;
1122
1123 spin_lock(lock: &filp->table_lock);
1124 idr_for_each_entry(&filp->object_idr, gobj, id)
1125 num_bos += 1;
1126 spin_unlock(lock: &filp->table_lock);
1127
1128 if (args->num_entries < num_bos) {
1129 args->num_entries = num_bos;
1130 return 0;
1131 }
1132
1133 if (num_bos == 0) {
1134 args->num_entries = 0;
1135 return 0;
1136 }
1137
1138 bo_entries = kvcalloc(num_bos, sizeof(*bo_entries), GFP_KERNEL);
1139 if (!bo_entries)
1140 return -ENOMEM;
1141
1142 spin_lock(lock: &filp->table_lock);
1143 idr_for_each_entry(&filp->object_idr, gobj, id) {
1144 struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
1145 struct drm_amdgpu_gem_list_handles_entry *bo_entry;
1146
1147 if (bo_index >= num_bos) {
1148 ret = -EAGAIN;
1149 break;
1150 }
1151
1152 bo_entry = &bo_entries[bo_index];
1153
1154 bo_entry->size = amdgpu_bo_size(bo);
1155 bo_entry->alloc_flags = bo->flags & AMDGPU_GEM_CREATE_SETTABLE_MASK;
1156 bo_entry->preferred_domains = bo->preferred_domains;
1157 bo_entry->gem_handle = id;
1158 bo_entry->alignment = bo->tbo.page_alignment;
1159
1160 if (bo->tbo.base.import_attach)
1161 bo_entry->flags |= AMDGPU_GEM_LIST_HANDLES_FLAG_IS_IMPORT;
1162
1163 bo_index += 1;
1164 }
1165 spin_unlock(lock: &filp->table_lock);
1166
1167 args->num_entries = bo_index;
1168
1169 if (!ret)
1170 if (copy_to_user(u64_to_user_ptr(args->entries), from: bo_entries, n: num_bos * sizeof(*bo_entries)))
1171 ret = -EFAULT;
1172
1173 kvfree(addr: bo_entries);
1174
1175 return ret;
1176}
1177
1178static int amdgpu_gem_align_pitch(struct amdgpu_device *adev,
1179 int width,
1180 int cpp,
1181 bool tiled)
1182{
1183 int aligned = width;
1184 int pitch_mask = 0;
1185
1186 switch (cpp) {
1187 case 1:
1188 pitch_mask = 255;
1189 break;
1190 case 2:
1191 pitch_mask = 127;
1192 break;
1193 case 3:
1194 case 4:
1195 pitch_mask = 63;
1196 break;
1197 }
1198
1199 aligned += pitch_mask;
1200 aligned &= ~pitch_mask;
1201 return aligned * cpp;
1202}
1203
1204int amdgpu_mode_dumb_create(struct drm_file *file_priv,
1205 struct drm_device *dev,
1206 struct drm_mode_create_dumb *args)
1207{
1208 struct amdgpu_device *adev = drm_to_adev(ddev: dev);
1209 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
1210 struct drm_gem_object *gobj;
1211 uint32_t handle;
1212 u64 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
1213 AMDGPU_GEM_CREATE_CPU_GTT_USWC |
1214 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
1215 u32 domain;
1216 int r;
1217
1218 /*
1219 * The buffer returned from this function should be cleared, but
1220 * it can only be done if the ring is enabled or we'll fail to
1221 * create the buffer.
1222 */
1223 if (adev->mman.buffer_funcs_enabled)
1224 flags |= AMDGPU_GEM_CREATE_VRAM_CLEARED;
1225
1226 args->pitch = amdgpu_gem_align_pitch(adev, width: args->width,
1227 DIV_ROUND_UP(args->bpp, 8), tiled: 0);
1228 args->size = (u64)args->pitch * args->height;
1229 args->size = ALIGN(args->size, PAGE_SIZE);
1230 domain = amdgpu_bo_get_preferred_domain(adev,
1231 domain: amdgpu_display_supported_domains(adev, bo_flags: flags));
1232 r = amdgpu_gem_object_create(adev, size: args->size, alignment: 0, initial_domain: domain, flags,
1233 type: ttm_bo_type_device, NULL, obj: &gobj, xcp_id_plus1: fpriv->xcp_id + 1);
1234 if (r)
1235 return -ENOMEM;
1236
1237 r = drm_gem_handle_create(file_priv, obj: gobj, handlep: &handle);
1238 /* drop reference from allocate - handle holds it now */
1239 drm_gem_object_put(obj: gobj);
1240 if (r)
1241 return r;
1242
1243 args->handle = handle;
1244 return 0;
1245}
1246
1247#if defined(CONFIG_DEBUG_FS)
1248static int amdgpu_debugfs_gem_info_show(struct seq_file *m, void *unused)
1249{
1250 struct amdgpu_device *adev = m->private;
1251 struct drm_device *dev = adev_to_drm(adev);
1252 struct drm_file *file;
1253 int r;
1254
1255 r = mutex_lock_interruptible(&dev->filelist_mutex);
1256 if (r)
1257 return r;
1258
1259 list_for_each_entry(file, &dev->filelist, lhead) {
1260 struct task_struct *task;
1261 struct drm_gem_object *gobj;
1262 struct pid *pid;
1263 int id;
1264
1265 /*
1266 * Although we have a valid reference on file->pid, that does
1267 * not guarantee that the task_struct who called get_pid() is
1268 * still alive (e.g. get_pid(current) => fork() => exit()).
1269 * Therefore, we need to protect this ->comm access using RCU.
1270 */
1271 rcu_read_lock();
1272 pid = rcu_dereference(file->pid);
1273 task = pid_task(pid, PIDTYPE_TGID);
1274 seq_printf(m, fmt: "pid %8d command %s:\n", pid_nr(pid),
1275 task ? task->comm : "<unknown>");
1276 rcu_read_unlock();
1277
1278 spin_lock(lock: &file->table_lock);
1279 idr_for_each_entry(&file->object_idr, gobj, id) {
1280 struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
1281
1282 amdgpu_bo_print_info(id, bo, m);
1283 }
1284 spin_unlock(lock: &file->table_lock);
1285 }
1286
1287 mutex_unlock(lock: &dev->filelist_mutex);
1288 return 0;
1289}
1290
1291DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_gem_info);
1292
1293#endif
1294
1295void amdgpu_debugfs_gem_init(struct amdgpu_device *adev)
1296{
1297#if defined(CONFIG_DEBUG_FS)
1298 struct drm_minor *minor = adev_to_drm(adev)->primary;
1299 struct dentry *root = minor->debugfs_root;
1300
1301 debugfs_create_file("amdgpu_gem_info", 0444, root, adev,
1302 &amdgpu_debugfs_gem_info_fops);
1303#endif
1304}
1305

source code of linux/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c