| 1 | /* |
| 2 | * Copyright 2023 Advanced Micro Devices, Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | */ |
| 22 | |
| 23 | uint32_t kgd_gfx_v10_enable_debug_trap(struct amdgpu_device *adev, |
| 24 | bool restore_dbg_registers, |
| 25 | uint32_t vmid); |
| 26 | uint32_t kgd_gfx_v10_disable_debug_trap(struct amdgpu_device *adev, |
| 27 | bool keep_trap_enabled, |
| 28 | uint32_t vmid); |
| 29 | int kgd_gfx_v10_validate_trap_override_request(struct amdgpu_device *adev, |
| 30 | uint32_t trap_override, |
| 31 | uint32_t *trap_mask_supported); |
| 32 | uint32_t kgd_gfx_v10_set_wave_launch_trap_override(struct amdgpu_device *adev, |
| 33 | uint32_t vmid, |
| 34 | uint32_t trap_override, |
| 35 | uint32_t trap_mask_bits, |
| 36 | uint32_t trap_mask_request, |
| 37 | uint32_t *trap_mask_prev, |
| 38 | uint32_t kfd_dbg_trap_cntl_prev); |
| 39 | uint32_t kgd_gfx_v10_set_wave_launch_mode(struct amdgpu_device *adev, |
| 40 | uint8_t wave_launch_mode, |
| 41 | uint32_t vmid); |
| 42 | uint32_t kgd_gfx_v10_set_address_watch(struct amdgpu_device *adev, |
| 43 | uint64_t watch_address, |
| 44 | uint32_t watch_address_mask, |
| 45 | uint32_t watch_id, |
| 46 | uint32_t watch_mode, |
| 47 | uint32_t debug_vmid, |
| 48 | uint32_t inst); |
| 49 | uint32_t kgd_gfx_v10_clear_address_watch(struct amdgpu_device *adev, |
| 50 | uint32_t watch_id); |
| 51 | void kgd_gfx_v10_get_iq_wait_times(struct amdgpu_device *adev, |
| 52 | uint32_t *wait_times, |
| 53 | uint32_t inst); |
| 54 | void kgd_gfx_v10_build_dequeue_wait_counts_packet_info(struct amdgpu_device *adev, |
| 55 | uint32_t wait_times, |
| 56 | uint32_t sch_wave, |
| 57 | uint32_t que_sleep, |
| 58 | uint32_t *reg_offset, |
| 59 | uint32_t *reg_data); |
| 60 | uint64_t kgd_gfx_v10_hqd_get_pq_addr(struct amdgpu_device *adev, |
| 61 | uint32_t pipe_id, |
| 62 | uint32_t queue_id, |
| 63 | uint32_t inst); |
| 64 | uint64_t kgd_gfx_v10_hqd_reset(struct amdgpu_device *adev, |
| 65 | uint32_t pipe_id, |
| 66 | uint32_t queue_id, |
| 67 | uint32_t inst, |
| 68 | unsigned int utimeout); |
| 69 | uint32_t kgd_gfx_v10_hqd_sdma_get_doorbell(struct amdgpu_device *adev, |
| 70 | int engine, int queue); |
| 71 | |