1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include <linux/irqdomain.h>
27#include <linux/pci.h>
28#include <linux/pm_domain.h>
29#include <linux/platform_device.h>
30#include <sound/designware_i2s.h>
31#include <sound/pcm.h>
32#include <linux/acpi.h>
33#include <linux/dmi.h>
34
35#include "amdgpu.h"
36#include "atom.h"
37#include "amdgpu_acp.h"
38
39#include "acp_gfx_if.h"
40
41#define ST_JADEITE 1
42#define ACP_TILE_ON_MASK 0x03
43#define ACP_TILE_OFF_MASK 0x02
44#define ACP_TILE_ON_RETAIN_REG_MASK 0x1f
45#define ACP_TILE_OFF_RETAIN_REG_MASK 0x20
46
47#define ACP_TILE_P1_MASK 0x3e
48#define ACP_TILE_P2_MASK 0x3d
49#define ACP_TILE_DSP0_MASK 0x3b
50#define ACP_TILE_DSP1_MASK 0x37
51
52#define ACP_TILE_DSP2_MASK 0x2f
53
54#define ACP_DMA_REGS_END 0x146c0
55#define ACP_I2S_PLAY_REGS_START 0x14840
56#define ACP_I2S_PLAY_REGS_END 0x148b4
57#define ACP_I2S_CAP_REGS_START 0x148b8
58#define ACP_I2S_CAP_REGS_END 0x1496c
59
60#define ACP_I2S_COMP1_CAP_REG_OFFSET 0xac
61#define ACP_I2S_COMP2_CAP_REG_OFFSET 0xa8
62#define ACP_I2S_COMP1_PLAY_REG_OFFSET 0x6c
63#define ACP_I2S_COMP2_PLAY_REG_OFFSET 0x68
64#define ACP_BT_PLAY_REGS_START 0x14970
65#define ACP_BT_PLAY_REGS_END 0x14a24
66#define ACP_BT_COMP1_REG_OFFSET 0xac
67#define ACP_BT_COMP2_REG_OFFSET 0xa8
68
69#define mmACP_PGFSM_RETAIN_REG 0x51c9
70#define mmACP_PGFSM_CONFIG_REG 0x51ca
71#define mmACP_PGFSM_READ_REG_0 0x51cc
72
73#define mmACP_MEM_SHUT_DOWN_REQ_LO 0x51f8
74#define mmACP_MEM_SHUT_DOWN_REQ_HI 0x51f9
75#define mmACP_MEM_SHUT_DOWN_STS_LO 0x51fa
76#define mmACP_MEM_SHUT_DOWN_STS_HI 0x51fb
77
78#define mmACP_CONTROL 0x5131
79#define mmACP_STATUS 0x5133
80#define mmACP_SOFT_RESET 0x5134
81#define ACP_CONTROL__ClkEn_MASK 0x1
82#define ACP_SOFT_RESET__SoftResetAud_MASK 0x100
83#define ACP_SOFT_RESET__SoftResetAudDone_MASK 0x1000000
84#define ACP_CLOCK_EN_TIME_OUT_VALUE 0x000000FF
85#define ACP_SOFT_RESET_DONE_TIME_OUT_VALUE 0x000000FF
86
87#define ACP_TIMEOUT_LOOP 0x000000FF
88#define ACP_DEVS 4
89#define ACP_SRC_ID 162
90
91static unsigned long acp_machine_id;
92
93enum {
94 ACP_TILE_P1 = 0,
95 ACP_TILE_P2,
96 ACP_TILE_DSP0,
97 ACP_TILE_DSP1,
98 ACP_TILE_DSP2,
99};
100
101static int acp_sw_init(struct amdgpu_ip_block *ip_block)
102{
103 struct amdgpu_device *adev = ip_block->adev;
104
105 adev->acp.parent = adev->dev;
106
107 adev->acp.cgs_device =
108 amdgpu_cgs_create_device(adev);
109 if (!adev->acp.cgs_device)
110 return -EINVAL;
111
112 return 0;
113}
114
115static int acp_sw_fini(struct amdgpu_ip_block *ip_block)
116{
117 struct amdgpu_device *adev = ip_block->adev;
118
119 if (adev->acp.cgs_device)
120 amdgpu_cgs_destroy_device(cgs_device: adev->acp.cgs_device);
121
122 return 0;
123}
124
125struct acp_pm_domain {
126 void *adev;
127 struct generic_pm_domain gpd;
128};
129
130static int acp_poweroff(struct generic_pm_domain *genpd)
131{
132 struct acp_pm_domain *apd;
133 struct amdgpu_device *adev;
134
135 apd = container_of(genpd, struct acp_pm_domain, gpd);
136 adev = apd->adev;
137 /* call smu to POWER GATE ACP block
138 * smu will
139 * 1. turn off the acp clock
140 * 2. power off the acp tiles
141 * 3. check and enter ulv state
142 */
143 amdgpu_dpm_set_powergating_by_smu(adev, block_type: AMD_IP_BLOCK_TYPE_ACP, gate: true, inst: 0);
144 return 0;
145}
146
147static int acp_poweron(struct generic_pm_domain *genpd)
148{
149 struct acp_pm_domain *apd;
150 struct amdgpu_device *adev;
151
152 apd = container_of(genpd, struct acp_pm_domain, gpd);
153 adev = apd->adev;
154 /* call smu to UNGATE ACP block
155 * smu will
156 * 1. exit ulv
157 * 2. turn on acp clock
158 * 3. power on acp tiles
159 */
160 amdgpu_dpm_set_powergating_by_smu(adev, block_type: AMD_IP_BLOCK_TYPE_ACP, gate: false, inst: 0);
161 return 0;
162}
163
164static int acp_genpd_add_device(struct device *dev, void *data)
165{
166 struct generic_pm_domain *gpd = data;
167 int ret;
168
169 ret = pm_genpd_add_device(genpd: gpd, dev);
170 if (ret)
171 dev_err(dev, "Failed to add dev to genpd %d\n", ret);
172
173 return ret;
174}
175
176static int acp_genpd_remove_device(struct device *dev, void *data)
177{
178 int ret;
179
180 ret = pm_genpd_remove_device(dev);
181 if (ret)
182 dev_err(dev, "Failed to remove dev from genpd %d\n", ret);
183
184 /* Continue to remove */
185 return 0;
186}
187
188static int acp_quirk_cb(const struct dmi_system_id *id)
189{
190 acp_machine_id = ST_JADEITE;
191 return 1;
192}
193
194static const struct dmi_system_id acp_quirk_table[] = {
195 {
196 .callback = acp_quirk_cb,
197 .matches = {
198 DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "AMD"),
199 DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "Jadeite"),
200 }
201 },
202 {
203 .callback = acp_quirk_cb,
204 .matches = {
205 DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "IP3 Technology CO.,Ltd."),
206 DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "ASN1D"),
207 },
208 },
209 {
210 .callback = acp_quirk_cb,
211 .matches = {
212 DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "Standard"),
213 DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "ASN10"),
214 },
215 },
216 {}
217};
218
219/**
220 * acp_hw_init - start and test ACP block
221 *
222 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
223 *
224 */
225static int acp_hw_init(struct amdgpu_ip_block *ip_block)
226{
227 int r;
228 u64 acp_base;
229 u32 val = 0;
230 u32 count = 0;
231 struct i2s_platform_data *i2s_pdata = NULL;
232
233 struct amdgpu_device *adev = ip_block->adev;
234
235 r = amd_acp_hw_init(cgs_device: adev->acp.cgs_device,
236 acp_version_major: ip_block->version->major, acp_version_minor: ip_block->version->minor);
237 /* -ENODEV means board uses AZ rather than ACP */
238 if (r == -ENODEV) {
239 amdgpu_dpm_set_powergating_by_smu(adev, block_type: AMD_IP_BLOCK_TYPE_ACP, gate: true, inst: 0);
240 return 0;
241 } else if (r) {
242 return r;
243 }
244
245 if (adev->rmmio_size == 0 || adev->rmmio_size < 0x5289)
246 return -EINVAL;
247
248 acp_base = adev->rmmio_base;
249 adev->acp.acp_genpd = kzalloc(sizeof(struct acp_pm_domain), GFP_KERNEL);
250 if (!adev->acp.acp_genpd)
251 return -ENOMEM;
252
253 adev->acp.acp_genpd->gpd.name = "ACP_AUDIO";
254 adev->acp.acp_genpd->gpd.power_off = acp_poweroff;
255 adev->acp.acp_genpd->gpd.power_on = acp_poweron;
256 adev->acp.acp_genpd->adev = adev;
257
258 pm_genpd_init(genpd: &adev->acp.acp_genpd->gpd, NULL, is_off: false);
259 dmi_check_system(list: acp_quirk_table);
260 switch (acp_machine_id) {
261 case ST_JADEITE:
262 {
263 adev->acp.acp_cell = kcalloc(2, sizeof(struct mfd_cell),
264 GFP_KERNEL);
265 if (!adev->acp.acp_cell) {
266 r = -ENOMEM;
267 goto failure;
268 }
269
270 adev->acp.acp_res = kcalloc(3, sizeof(struct resource), GFP_KERNEL);
271 if (!adev->acp.acp_res) {
272 r = -ENOMEM;
273 goto failure;
274 }
275
276 i2s_pdata = kcalloc(1, sizeof(struct i2s_platform_data), GFP_KERNEL);
277 if (!i2s_pdata) {
278 r = -ENOMEM;
279 goto failure;
280 }
281
282 i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET |
283 DW_I2S_QUIRK_16BIT_IDX_OVERRIDE;
284 i2s_pdata[0].cap = DWC_I2S_PLAY | DWC_I2S_RECORD;
285 i2s_pdata[0].snd_rates = SNDRV_PCM_RATE_8000_96000;
286 i2s_pdata[0].i2s_reg_comp1 = ACP_I2S_COMP1_CAP_REG_OFFSET;
287 i2s_pdata[0].i2s_reg_comp2 = ACP_I2S_COMP2_CAP_REG_OFFSET;
288
289 adev->acp.acp_res[0].name = "acp2x_dma";
290 adev->acp.acp_res[0].flags = IORESOURCE_MEM;
291 adev->acp.acp_res[0].start = acp_base;
292 adev->acp.acp_res[0].end = acp_base + ACP_DMA_REGS_END;
293
294 adev->acp.acp_res[1].name = "acp2x_dw_i2s_play_cap";
295 adev->acp.acp_res[1].flags = IORESOURCE_MEM;
296 adev->acp.acp_res[1].start = acp_base + ACP_I2S_CAP_REGS_START;
297 adev->acp.acp_res[1].end = acp_base + ACP_I2S_CAP_REGS_END;
298
299 adev->acp.acp_res[2].name = "acp2x_dma_irq";
300 adev->acp.acp_res[2].flags = IORESOURCE_IRQ;
301 adev->acp.acp_res[2].start = amdgpu_irq_create_mapping(adev, src_id: 162);
302 adev->acp.acp_res[2].end = adev->acp.acp_res[2].start;
303
304 adev->acp.acp_cell[0].name = "acp_audio_dma";
305 adev->acp.acp_cell[0].id = 0;
306 adev->acp.acp_cell[0].num_resources = 3;
307 adev->acp.acp_cell[0].resources = &adev->acp.acp_res[0];
308 adev->acp.acp_cell[0].platform_data = &adev->asic_type;
309 adev->acp.acp_cell[0].pdata_size = sizeof(adev->asic_type);
310
311 adev->acp.acp_cell[1].name = "designware-i2s";
312 adev->acp.acp_cell[1].id = 1;
313 adev->acp.acp_cell[1].num_resources = 1;
314 adev->acp.acp_cell[1].resources = &adev->acp.acp_res[1];
315 adev->acp.acp_cell[1].platform_data = &i2s_pdata[0];
316 adev->acp.acp_cell[1].pdata_size = sizeof(struct i2s_platform_data);
317 r = mfd_add_devices(parent: adev->acp.parent, id: 0, cells: adev->acp.acp_cell, n_devs: 2, NULL, irq_base: 0, NULL);
318 if (r)
319 goto failure;
320 r = device_for_each_child(parent: adev->acp.parent, data: &adev->acp.acp_genpd->gpd,
321 fn: acp_genpd_add_device);
322 if (r)
323 goto failure;
324 break;
325 }
326 default:
327 adev->acp.acp_cell = kcalloc(ACP_DEVS, sizeof(struct mfd_cell),
328 GFP_KERNEL);
329
330 if (!adev->acp.acp_cell) {
331 r = -ENOMEM;
332 goto failure;
333 }
334
335 adev->acp.acp_res = kcalloc(5, sizeof(struct resource), GFP_KERNEL);
336 if (!adev->acp.acp_res) {
337 r = -ENOMEM;
338 goto failure;
339 }
340
341 i2s_pdata = kcalloc(3, sizeof(struct i2s_platform_data), GFP_KERNEL);
342 if (!i2s_pdata) {
343 r = -ENOMEM;
344 goto failure;
345 }
346
347 switch (adev->asic_type) {
348 case CHIP_STONEY:
349 i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET |
350 DW_I2S_QUIRK_16BIT_IDX_OVERRIDE;
351 break;
352 default:
353 i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET;
354 }
355 i2s_pdata[0].cap = DWC_I2S_PLAY;
356 i2s_pdata[0].snd_rates = SNDRV_PCM_RATE_8000_96000;
357 i2s_pdata[0].i2s_reg_comp1 = ACP_I2S_COMP1_PLAY_REG_OFFSET;
358 i2s_pdata[0].i2s_reg_comp2 = ACP_I2S_COMP2_PLAY_REG_OFFSET;
359 switch (adev->asic_type) {
360 case CHIP_STONEY:
361 i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET |
362 DW_I2S_QUIRK_COMP_PARAM1 |
363 DW_I2S_QUIRK_16BIT_IDX_OVERRIDE;
364 break;
365 default:
366 i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET |
367 DW_I2S_QUIRK_COMP_PARAM1;
368 }
369
370 i2s_pdata[1].cap = DWC_I2S_RECORD;
371 i2s_pdata[1].snd_rates = SNDRV_PCM_RATE_8000_96000;
372 i2s_pdata[1].i2s_reg_comp1 = ACP_I2S_COMP1_CAP_REG_OFFSET;
373 i2s_pdata[1].i2s_reg_comp2 = ACP_I2S_COMP2_CAP_REG_OFFSET;
374
375 i2s_pdata[2].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET;
376 switch (adev->asic_type) {
377 case CHIP_STONEY:
378 i2s_pdata[2].quirks |= DW_I2S_QUIRK_16BIT_IDX_OVERRIDE;
379 break;
380 default:
381 break;
382 }
383
384 i2s_pdata[2].cap = DWC_I2S_PLAY | DWC_I2S_RECORD;
385 i2s_pdata[2].snd_rates = SNDRV_PCM_RATE_8000_96000;
386 i2s_pdata[2].i2s_reg_comp1 = ACP_BT_COMP1_REG_OFFSET;
387 i2s_pdata[2].i2s_reg_comp2 = ACP_BT_COMP2_REG_OFFSET;
388
389 adev->acp.acp_res[0].name = "acp2x_dma";
390 adev->acp.acp_res[0].flags = IORESOURCE_MEM;
391 adev->acp.acp_res[0].start = acp_base;
392 adev->acp.acp_res[0].end = acp_base + ACP_DMA_REGS_END;
393
394 adev->acp.acp_res[1].name = "acp2x_dw_i2s_play";
395 adev->acp.acp_res[1].flags = IORESOURCE_MEM;
396 adev->acp.acp_res[1].start = acp_base + ACP_I2S_PLAY_REGS_START;
397 adev->acp.acp_res[1].end = acp_base + ACP_I2S_PLAY_REGS_END;
398
399 adev->acp.acp_res[2].name = "acp2x_dw_i2s_cap";
400 adev->acp.acp_res[2].flags = IORESOURCE_MEM;
401 adev->acp.acp_res[2].start = acp_base + ACP_I2S_CAP_REGS_START;
402 adev->acp.acp_res[2].end = acp_base + ACP_I2S_CAP_REGS_END;
403
404 adev->acp.acp_res[3].name = "acp2x_dw_bt_i2s_play_cap";
405 adev->acp.acp_res[3].flags = IORESOURCE_MEM;
406 adev->acp.acp_res[3].start = acp_base + ACP_BT_PLAY_REGS_START;
407 adev->acp.acp_res[3].end = acp_base + ACP_BT_PLAY_REGS_END;
408
409 adev->acp.acp_res[4].name = "acp2x_dma_irq";
410 adev->acp.acp_res[4].flags = IORESOURCE_IRQ;
411 adev->acp.acp_res[4].start = amdgpu_irq_create_mapping(adev, src_id: 162);
412 adev->acp.acp_res[4].end = adev->acp.acp_res[4].start;
413
414 adev->acp.acp_cell[0].name = "acp_audio_dma";
415 adev->acp.acp_cell[0].id = 0;
416 adev->acp.acp_cell[0].num_resources = 5;
417 adev->acp.acp_cell[0].resources = &adev->acp.acp_res[0];
418 adev->acp.acp_cell[0].platform_data = &adev->asic_type;
419 adev->acp.acp_cell[0].pdata_size = sizeof(adev->asic_type);
420
421 adev->acp.acp_cell[1].name = "designware-i2s";
422 adev->acp.acp_cell[1].id = 1;
423 adev->acp.acp_cell[1].num_resources = 1;
424 adev->acp.acp_cell[1].resources = &adev->acp.acp_res[1];
425 adev->acp.acp_cell[1].platform_data = &i2s_pdata[0];
426 adev->acp.acp_cell[1].pdata_size = sizeof(struct i2s_platform_data);
427
428 adev->acp.acp_cell[2].name = "designware-i2s";
429 adev->acp.acp_cell[2].id = 2;
430 adev->acp.acp_cell[2].num_resources = 1;
431 adev->acp.acp_cell[2].resources = &adev->acp.acp_res[2];
432 adev->acp.acp_cell[2].platform_data = &i2s_pdata[1];
433 adev->acp.acp_cell[2].pdata_size = sizeof(struct i2s_platform_data);
434
435 adev->acp.acp_cell[3].name = "designware-i2s";
436 adev->acp.acp_cell[3].id = 3;
437 adev->acp.acp_cell[3].num_resources = 1;
438 adev->acp.acp_cell[3].resources = &adev->acp.acp_res[3];
439 adev->acp.acp_cell[3].platform_data = &i2s_pdata[2];
440 adev->acp.acp_cell[3].pdata_size = sizeof(struct i2s_platform_data);
441
442 r = mfd_add_devices(parent: adev->acp.parent, id: 0, cells: adev->acp.acp_cell, ACP_DEVS, NULL, irq_base: 0, NULL);
443 if (r)
444 goto failure;
445
446 r = device_for_each_child(parent: adev->acp.parent, data: &adev->acp.acp_genpd->gpd,
447 fn: acp_genpd_add_device);
448 if (r)
449 goto failure;
450 }
451
452 /* Assert Soft reset of ACP */
453 val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
454
455 val |= ACP_SOFT_RESET__SoftResetAud_MASK;
456 cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val);
457
458 count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE;
459 while (true) {
460 val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
461 if (ACP_SOFT_RESET__SoftResetAudDone_MASK ==
462 (val & ACP_SOFT_RESET__SoftResetAudDone_MASK))
463 break;
464 if (--count == 0) {
465 dev_err(&adev->pdev->dev, "Failed to reset ACP\n");
466 r = -ETIMEDOUT;
467 goto failure;
468 }
469 udelay(usec: 100);
470 }
471 /* Enable clock to ACP and wait until the clock is enabled */
472 val = cgs_read_register(adev->acp.cgs_device, mmACP_CONTROL);
473 val = val | ACP_CONTROL__ClkEn_MASK;
474 cgs_write_register(adev->acp.cgs_device, mmACP_CONTROL, val);
475
476 count = ACP_CLOCK_EN_TIME_OUT_VALUE;
477
478 while (true) {
479 val = cgs_read_register(adev->acp.cgs_device, mmACP_STATUS);
480 if (val & (u32) 0x1)
481 break;
482 if (--count == 0) {
483 dev_err(&adev->pdev->dev, "Failed to reset ACP\n");
484 r = -ETIMEDOUT;
485 goto failure;
486 }
487 udelay(usec: 100);
488 }
489 /* Deassert the SOFT RESET flags */
490 val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
491 val &= ~ACP_SOFT_RESET__SoftResetAud_MASK;
492 cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val);
493 return 0;
494
495failure:
496 kfree(objp: i2s_pdata);
497 kfree(objp: adev->acp.acp_res);
498 kfree(objp: adev->acp.acp_cell);
499 kfree(objp: adev->acp.acp_genpd);
500 return r;
501}
502
503/**
504 * acp_hw_fini - stop the hardware block
505 *
506 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
507 *
508 */
509static int acp_hw_fini(struct amdgpu_ip_block *ip_block)
510{
511 u32 val = 0;
512 u32 count = 0;
513 struct amdgpu_device *adev = ip_block->adev;
514
515 /* return early if no ACP */
516 if (!adev->acp.acp_genpd) {
517 amdgpu_dpm_set_powergating_by_smu(adev, block_type: AMD_IP_BLOCK_TYPE_ACP, gate: false, inst: 0);
518 return 0;
519 }
520
521 /* Assert Soft reset of ACP */
522 val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
523
524 val |= ACP_SOFT_RESET__SoftResetAud_MASK;
525 cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val);
526
527 count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE;
528 while (true) {
529 val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
530 if (ACP_SOFT_RESET__SoftResetAudDone_MASK ==
531 (val & ACP_SOFT_RESET__SoftResetAudDone_MASK))
532 break;
533 if (--count == 0) {
534 dev_err(&adev->pdev->dev, "Failed to reset ACP\n");
535 return -ETIMEDOUT;
536 }
537 udelay(usec: 100);
538 }
539 /* Disable ACP clock */
540 val = cgs_read_register(adev->acp.cgs_device, mmACP_CONTROL);
541 val &= ~ACP_CONTROL__ClkEn_MASK;
542 cgs_write_register(adev->acp.cgs_device, mmACP_CONTROL, val);
543
544 count = ACP_CLOCK_EN_TIME_OUT_VALUE;
545
546 while (true) {
547 val = cgs_read_register(adev->acp.cgs_device, mmACP_STATUS);
548 if (val & (u32) 0x1)
549 break;
550 if (--count == 0) {
551 dev_err(&adev->pdev->dev, "Failed to reset ACP\n");
552 return -ETIMEDOUT;
553 }
554 udelay(usec: 100);
555 }
556
557 device_for_each_child(parent: adev->acp.parent, NULL,
558 fn: acp_genpd_remove_device);
559
560 mfd_remove_devices(parent: adev->acp.parent);
561 kfree(objp: adev->acp.acp_res);
562 kfree(objp: adev->acp.acp_genpd);
563 kfree(objp: adev->acp.acp_cell);
564
565 return 0;
566}
567
568static int acp_suspend(struct amdgpu_ip_block *ip_block)
569{
570 struct amdgpu_device *adev = ip_block->adev;
571
572 /* power up on suspend */
573 if (!adev->acp.acp_cell)
574 amdgpu_dpm_set_powergating_by_smu(adev, block_type: AMD_IP_BLOCK_TYPE_ACP, gate: false, inst: 0);
575 return 0;
576}
577
578static int acp_resume(struct amdgpu_ip_block *ip_block)
579{
580 struct amdgpu_device *adev = ip_block->adev;
581
582 /* power down again on resume */
583 if (!adev->acp.acp_cell)
584 amdgpu_dpm_set_powergating_by_smu(adev, block_type: AMD_IP_BLOCK_TYPE_ACP, gate: true, inst: 0);
585 return 0;
586}
587
588static bool acp_is_idle(struct amdgpu_ip_block *ip_block)
589{
590 return true;
591}
592
593static int acp_set_clockgating_state(struct amdgpu_ip_block *ip_block,
594 enum amd_clockgating_state state)
595{
596 return 0;
597}
598
599static int acp_set_powergating_state(struct amdgpu_ip_block *ip_block,
600 enum amd_powergating_state state)
601{
602 struct amdgpu_device *adev = ip_block->adev;
603 bool enable = (state == AMD_PG_STATE_GATE);
604
605 amdgpu_dpm_set_powergating_by_smu(adev, block_type: AMD_IP_BLOCK_TYPE_ACP, gate: enable, inst: 0);
606
607 return 0;
608}
609
610static const struct amd_ip_funcs acp_ip_funcs = {
611 .name = "acp_ip",
612 .sw_init = acp_sw_init,
613 .sw_fini = acp_sw_fini,
614 .hw_init = acp_hw_init,
615 .hw_fini = acp_hw_fini,
616 .suspend = acp_suspend,
617 .resume = acp_resume,
618 .is_idle = acp_is_idle,
619 .set_clockgating_state = acp_set_clockgating_state,
620 .set_powergating_state = acp_set_powergating_state,
621};
622
623const struct amdgpu_ip_block_version acp_ip_block = {
624 .type = AMD_IP_BLOCK_TYPE_ACP,
625 .major = 2,
626 .minor = 2,
627 .rev = 0,
628 .funcs = &acp_ip_funcs,
629};
630

source code of linux/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c