1// SPDX-License-Identifier: GPL-2.0-only
2//
3// Copyright 2020 Google Inc
4// Copyright 2025 Linaro Ltd.
5//
6// GPIO driver for Maxim MAX77759
7
8#include <linux/dev_printk.h>
9#include <linux/device.h>
10#include <linux/device/driver.h>
11#include <linux/gpio/driver.h>
12#include <linux/interrupt.h>
13#include <linux/irq.h>
14#include <linux/irqreturn.h>
15#include <linux/lockdep.h>
16#include <linux/mfd/max77759.h>
17#include <linux/mod_devicetable.h>
18#include <linux/module.h>
19#include <linux/overflow.h>
20#include <linux/platform_device.h>
21#include <linux/regmap.h>
22#include <linux/seq_file.h>
23
24#define MAX77759_N_GPIOS ARRAY_SIZE(max77759_gpio_line_names)
25static const char * const max77759_gpio_line_names[] = { "GPIO5", "GPIO6" };
26
27struct max77759_gpio_chip {
28 struct regmap *map;
29 struct max77759 *max77759;
30 struct gpio_chip gc;
31 struct mutex maxq_lock; /* protect MaxQ r/m/w operations */
32
33 struct mutex irq_lock; /* protect irq bus */
34 int irq_mask;
35 int irq_mask_changed;
36 int irq_trig;
37 int irq_trig_changed;
38};
39
40#define MAX77759_GPIOx_TRIGGER(offs, val) (((val) & 1) << (offs))
41#define MAX77759_GPIOx_TRIGGER_MASK(offs) MAX77759_GPIOx_TRIGGER(offs, ~0)
42enum max77759_trigger_gpio_type {
43 MAX77759_GPIO_TRIGGER_RISING = 0,
44 MAX77759_GPIO_TRIGGER_FALLING = 1
45};
46
47#define MAX77759_GPIOx_DIR(offs, dir) (((dir) & 1) << (2 + (3 * (offs))))
48#define MAX77759_GPIOx_DIR_MASK(offs) MAX77759_GPIOx_DIR(offs, ~0)
49enum max77759_control_gpio_dir {
50 MAX77759_GPIO_DIR_IN = 0,
51 MAX77759_GPIO_DIR_OUT = 1
52};
53
54#define MAX77759_GPIOx_OUTVAL(offs, val) (((val) & 1) << (3 + (3 * (offs))))
55#define MAX77759_GPIOx_OUTVAL_MASK(offs) MAX77759_GPIOx_OUTVAL(offs, ~0)
56
57#define MAX77759_GPIOx_INVAL_MASK(offs) (BIT(4) << (3 * (offs)))
58
59static int max77759_gpio_maxq_gpio_trigger_read(struct max77759_gpio_chip *chip)
60{
61 DEFINE_FLEX(struct max77759_maxq_command, cmd, cmd, length, 1);
62 DEFINE_FLEX(struct max77759_maxq_response, rsp, rsp, length, 2);
63 int ret;
64
65 cmd->cmd[0] = MAX77759_MAXQ_OPCODE_GPIO_TRIGGER_READ;
66
67 ret = max77759_maxq_command(max77759: chip->max77759, cmd, rsp);
68 if (ret < 0)
69 return ret;
70
71 return rsp->rsp[1];
72}
73
74static int max77759_gpio_maxq_gpio_trigger_write(struct max77759_gpio_chip *chip,
75 u8 trigger)
76{
77 DEFINE_FLEX(struct max77759_maxq_command, cmd, cmd, length, 2);
78
79 cmd->cmd[0] = MAX77759_MAXQ_OPCODE_GPIO_TRIGGER_WRITE;
80 cmd->cmd[1] = trigger;
81
82 return max77759_maxq_command(max77759: chip->max77759, cmd, NULL);
83}
84
85static int max77759_gpio_maxq_gpio_control_read(struct max77759_gpio_chip *chip)
86{
87 DEFINE_FLEX(struct max77759_maxq_command, cmd, cmd, length, 1);
88 DEFINE_FLEX(struct max77759_maxq_response, rsp, rsp, length, 2);
89 int ret;
90
91 cmd->cmd[0] = MAX77759_MAXQ_OPCODE_GPIO_CONTROL_READ;
92
93 ret = max77759_maxq_command(max77759: chip->max77759, cmd, rsp);
94 if (ret < 0)
95 return ret;
96
97 return rsp->rsp[1];
98}
99
100static int max77759_gpio_maxq_gpio_control_write(struct max77759_gpio_chip *chip,
101 u8 ctrl)
102{
103 DEFINE_FLEX(struct max77759_maxq_command, cmd, cmd, length, 2);
104
105 cmd->cmd[0] = MAX77759_MAXQ_OPCODE_GPIO_CONTROL_WRITE;
106 cmd->cmd[1] = ctrl;
107
108 return max77759_maxq_command(max77759: chip->max77759, cmd, NULL);
109}
110
111static int
112max77759_gpio_direction_from_control(int ctrl, unsigned int offset)
113{
114 enum max77759_control_gpio_dir dir;
115
116 dir = !!(ctrl & MAX77759_GPIOx_DIR_MASK(offset));
117 return ((dir == MAX77759_GPIO_DIR_OUT)
118 ? GPIO_LINE_DIRECTION_OUT
119 : GPIO_LINE_DIRECTION_IN);
120}
121
122static int max77759_gpio_get_direction(struct gpio_chip *gc,
123 unsigned int offset)
124{
125 struct max77759_gpio_chip *chip = gpiochip_get_data(gc);
126 int ctrl;
127
128 ctrl = max77759_gpio_maxq_gpio_control_read(chip);
129 if (ctrl < 0)
130 return ctrl;
131
132 return max77759_gpio_direction_from_control(ctrl, offset);
133}
134
135static int max77759_gpio_direction_helper(struct gpio_chip *gc,
136 unsigned int offset,
137 enum max77759_control_gpio_dir dir,
138 int value)
139{
140 struct max77759_gpio_chip *chip = gpiochip_get_data(gc);
141 int ctrl, new_ctrl;
142
143 guard(mutex)(T: &chip->maxq_lock);
144
145 ctrl = max77759_gpio_maxq_gpio_control_read(chip);
146 if (ctrl < 0)
147 return ctrl;
148
149 new_ctrl = ctrl & ~MAX77759_GPIOx_DIR_MASK(offset);
150 new_ctrl |= MAX77759_GPIOx_DIR(offset, dir);
151
152 if (dir == MAX77759_GPIO_DIR_OUT) {
153 new_ctrl &= ~MAX77759_GPIOx_OUTVAL_MASK(offset);
154 new_ctrl |= MAX77759_GPIOx_OUTVAL(offset, value);
155 }
156
157 if (new_ctrl == ctrl)
158 return 0;
159
160 return max77759_gpio_maxq_gpio_control_write(chip, ctrl: new_ctrl);
161}
162
163static int max77759_gpio_direction_input(struct gpio_chip *gc,
164 unsigned int offset)
165{
166 return max77759_gpio_direction_helper(gc, offset,
167 dir: MAX77759_GPIO_DIR_IN, value: -1);
168}
169
170static int max77759_gpio_direction_output(struct gpio_chip *gc,
171 unsigned int offset, int value)
172{
173 return max77759_gpio_direction_helper(gc, offset,
174 dir: MAX77759_GPIO_DIR_OUT, value);
175}
176
177static int max77759_gpio_get_value(struct gpio_chip *gc, unsigned int offset)
178{
179 struct max77759_gpio_chip *chip = gpiochip_get_data(gc);
180 int ctrl, mask;
181
182 ctrl = max77759_gpio_maxq_gpio_control_read(chip);
183 if (ctrl < 0)
184 return ctrl;
185
186 /*
187 * The input status bit doesn't reflect the pin state when the GPIO is
188 * configured as an output. Check the direction, and inspect the input
189 * or output bit accordingly.
190 */
191 mask = ((max77759_gpio_direction_from_control(ctrl, offset)
192 == GPIO_LINE_DIRECTION_IN)
193 ? MAX77759_GPIOx_INVAL_MASK(offset)
194 : MAX77759_GPIOx_OUTVAL_MASK(offset));
195
196 return !!(ctrl & mask);
197}
198
199static int max77759_gpio_set_value(struct gpio_chip *gc,
200 unsigned int offset, int value)
201{
202 struct max77759_gpio_chip *chip = gpiochip_get_data(gc);
203 int ctrl, new_ctrl;
204
205 guard(mutex)(T: &chip->maxq_lock);
206
207 ctrl = max77759_gpio_maxq_gpio_control_read(chip);
208 if (ctrl < 0)
209 return ctrl;
210
211 new_ctrl = ctrl & ~MAX77759_GPIOx_OUTVAL_MASK(offset);
212 new_ctrl |= MAX77759_GPIOx_OUTVAL(offset, value);
213
214 if (new_ctrl == ctrl)
215 return 0;
216
217 return max77759_gpio_maxq_gpio_control_write(chip, ctrl: new_ctrl);
218}
219
220static void max77759_gpio_irq_mask(struct irq_data *d)
221{
222 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
223 struct max77759_gpio_chip *chip = gpiochip_get_data(gc);
224 irq_hw_number_t hwirq = irqd_to_hwirq(d);
225
226 chip->irq_mask &= ~MAX77759_MAXQ_REG_UIC_INT1_GPIOxI_MASK(hwirq);
227 chip->irq_mask |= MAX77759_MAXQ_REG_UIC_INT1_GPIOxI(hwirq, 1);
228 chip->irq_mask_changed |= MAX77759_MAXQ_REG_UIC_INT1_GPIOxI(hwirq, 1);
229
230 gpiochip_disable_irq(gc, offset: hwirq);
231}
232
233static void max77759_gpio_irq_unmask(struct irq_data *d)
234{
235 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
236 struct max77759_gpio_chip *chip = gpiochip_get_data(gc);
237 irq_hw_number_t hwirq = irqd_to_hwirq(d);
238
239 gpiochip_enable_irq(gc, offset: hwirq);
240
241 chip->irq_mask &= ~MAX77759_MAXQ_REG_UIC_INT1_GPIOxI_MASK(hwirq);
242 chip->irq_mask |= MAX77759_MAXQ_REG_UIC_INT1_GPIOxI(hwirq, 0);
243 chip->irq_mask_changed |= MAX77759_MAXQ_REG_UIC_INT1_GPIOxI(hwirq, 1);
244}
245
246static int max77759_gpio_set_irq_type(struct irq_data *d, unsigned int type)
247{
248 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
249 struct max77759_gpio_chip *chip = gpiochip_get_data(gc);
250 irq_hw_number_t hwirq = irqd_to_hwirq(d);
251
252 chip->irq_trig &= ~MAX77759_GPIOx_TRIGGER_MASK(hwirq);
253 switch (type) {
254 case IRQ_TYPE_EDGE_RISING:
255 chip->irq_trig |= MAX77759_GPIOx_TRIGGER(hwirq,
256 MAX77759_GPIO_TRIGGER_RISING);
257 break;
258
259 case IRQ_TYPE_EDGE_FALLING:
260 chip->irq_trig |= MAX77759_GPIOx_TRIGGER(hwirq,
261 MAX77759_GPIO_TRIGGER_FALLING);
262 break;
263
264 default:
265 return -EINVAL;
266 }
267
268 chip->irq_trig_changed |= MAX77759_GPIOx_TRIGGER(hwirq, 1);
269
270 return 0;
271}
272
273static void max77759_gpio_bus_lock(struct irq_data *d)
274{
275 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
276 struct max77759_gpio_chip *chip = gpiochip_get_data(gc);
277
278 mutex_lock(&chip->irq_lock);
279}
280
281static int max77759_gpio_bus_sync_unlock_helper(struct gpio_chip *gc,
282 struct max77759_gpio_chip *chip)
283 __must_hold(&chip->maxq_lock)
284{
285 int ctrl, trigger, new_trigger, new_ctrl;
286 unsigned long irq_trig_changed;
287 int offset;
288 int ret;
289
290 lockdep_assert_held(&chip->maxq_lock);
291
292 ctrl = max77759_gpio_maxq_gpio_control_read(chip);
293 trigger = max77759_gpio_maxq_gpio_trigger_read(chip);
294 if (ctrl < 0 || trigger < 0) {
295 dev_err(gc->parent, "failed to read current state: %d / %d\n",
296 ctrl, trigger);
297 return (ctrl < 0) ? ctrl : trigger;
298 }
299
300 new_trigger = trigger & ~chip->irq_trig_changed;
301 new_trigger |= (chip->irq_trig & chip->irq_trig_changed);
302
303 /* change GPIO direction if required */
304 new_ctrl = ctrl;
305 irq_trig_changed = chip->irq_trig_changed;
306 for_each_set_bit(offset, &irq_trig_changed, MAX77759_N_GPIOS) {
307 new_ctrl &= ~MAX77759_GPIOx_DIR_MASK(offset);
308 new_ctrl |= MAX77759_GPIOx_DIR(offset, MAX77759_GPIO_DIR_IN);
309 }
310
311 if (new_trigger != trigger) {
312 ret = max77759_gpio_maxq_gpio_trigger_write(chip, trigger: new_trigger);
313 if (ret) {
314 dev_err(gc->parent,
315 "failed to write new trigger: %d\n", ret);
316 return ret;
317 }
318 }
319
320 if (new_ctrl != ctrl) {
321 ret = max77759_gpio_maxq_gpio_control_write(chip, ctrl: new_ctrl);
322 if (ret) {
323 dev_err(gc->parent,
324 "failed to write new control: %d\n", ret);
325 return ret;
326 }
327 }
328
329 chip->irq_trig_changed = 0;
330
331 return 0;
332}
333
334static void max77759_gpio_bus_sync_unlock(struct irq_data *d)
335{
336 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
337 struct max77759_gpio_chip *chip = gpiochip_get_data(gc);
338 int ret;
339
340 scoped_guard(mutex, &chip->maxq_lock) {
341 ret = max77759_gpio_bus_sync_unlock_helper(gc, chip);
342 if (ret)
343 goto out_unlock;
344 }
345
346 ret = regmap_update_bits(map: chip->map,
347 MAX77759_MAXQ_REG_UIC_INT1_M,
348 mask: chip->irq_mask_changed, val: chip->irq_mask);
349 if (ret) {
350 dev_err(gc->parent,
351 "failed to update UIC_INT1 irq mask: %d\n", ret);
352 goto out_unlock;
353 }
354
355 chip->irq_mask_changed = 0;
356
357out_unlock:
358 mutex_unlock(lock: &chip->irq_lock);
359}
360
361static void max77759_gpio_irq_print_chip(struct irq_data *d, struct seq_file *p)
362{
363 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
364
365 seq_puts(m: p, s: dev_name(dev: gc->parent));
366}
367
368static const struct irq_chip max77759_gpio_irq_chip = {
369 .irq_mask = max77759_gpio_irq_mask,
370 .irq_unmask = max77759_gpio_irq_unmask,
371 .irq_set_type = max77759_gpio_set_irq_type,
372 .irq_bus_lock = max77759_gpio_bus_lock,
373 .irq_bus_sync_unlock = max77759_gpio_bus_sync_unlock,
374 .irq_print_chip = max77759_gpio_irq_print_chip,
375 .flags = IRQCHIP_IMMUTABLE,
376 GPIOCHIP_IRQ_RESOURCE_HELPERS,
377};
378
379static irqreturn_t max77759_gpio_irqhandler(int irq, void *data)
380{
381 struct max77759_gpio_chip *chip = data;
382 struct gpio_chip *gc = &chip->gc;
383 bool handled = false;
384
385 /* iterate until no interrupt is pending */
386 while (true) {
387 unsigned int uic_int1;
388 int ret;
389 unsigned long pending;
390 int offset;
391
392 ret = regmap_read(map: chip->map, MAX77759_MAXQ_REG_UIC_INT1,
393 val: &uic_int1);
394 if (ret < 0) {
395 dev_err_ratelimited(gc->parent,
396 "failed to read IRQ status: %d\n",
397 ret);
398 /*
399 * If !handled, we have looped not even once, which
400 * means we should return IRQ_NONE in that case (and
401 * of course IRQ_HANDLED otherwise).
402 */
403 return IRQ_RETVAL(handled);
404 }
405
406 pending = uic_int1;
407 pending &= (MAX77759_MAXQ_REG_UIC_INT1_GPIO6I
408 | MAX77759_MAXQ_REG_UIC_INT1_GPIO5I);
409 if (!pending)
410 break;
411
412 for_each_set_bit(offset, &pending, MAX77759_N_GPIOS) {
413 /*
414 * ACK interrupt by writing 1 to bit 'offset', all
415 * others need to be written as 0. This needs to be
416 * done unconditionally hence regmap_set_bits() is
417 * inappropriate here.
418 */
419 regmap_write(map: chip->map, MAX77759_MAXQ_REG_UIC_INT1,
420 BIT(offset));
421
422 handle_nested_irq(irq: irq_find_mapping(domain: gc->irq.domain,
423 hwirq: offset));
424
425 handled = true;
426 }
427 }
428
429 return IRQ_RETVAL(handled);
430}
431
432static int max77759_gpio_probe(struct platform_device *pdev)
433{
434 struct max77759_gpio_chip *chip;
435 int irq;
436 struct gpio_irq_chip *girq;
437 int ret;
438 unsigned long irq_flags;
439 struct irq_data *irqd;
440
441 chip = devm_kzalloc(dev: &pdev->dev, size: sizeof(*chip), GFP_KERNEL);
442 if (!chip)
443 return -ENOMEM;
444
445 chip->map = dev_get_regmap(dev: pdev->dev.parent, name: "maxq");
446 if (!chip->map)
447 return dev_err_probe(dev: &pdev->dev, err: -ENODEV, fmt: "Missing regmap\n");
448
449 irq = platform_get_irq_byname(pdev, "GPI");
450 if (irq < 0)
451 return dev_err_probe(dev: &pdev->dev, err: irq, fmt: "Failed to get IRQ\n");
452
453 chip->max77759 = dev_get_drvdata(dev: pdev->dev.parent);
454 ret = devm_mutex_init(&pdev->dev, &chip->maxq_lock);
455 if (ret)
456 return ret;
457 ret = devm_mutex_init(&pdev->dev, &chip->irq_lock);
458 if (ret)
459 return ret;
460
461 chip->gc.base = -1;
462 chip->gc.label = dev_name(dev: &pdev->dev);
463 chip->gc.parent = &pdev->dev;
464 chip->gc.can_sleep = true;
465
466 chip->gc.names = max77759_gpio_line_names;
467 chip->gc.ngpio = MAX77759_N_GPIOS;
468 chip->gc.get_direction = max77759_gpio_get_direction;
469 chip->gc.direction_input = max77759_gpio_direction_input;
470 chip->gc.direction_output = max77759_gpio_direction_output;
471 chip->gc.get = max77759_gpio_get_value;
472 chip->gc.set = max77759_gpio_set_value;
473
474 girq = &chip->gc.irq;
475 gpio_irq_chip_set_chip(girq, chip: &max77759_gpio_irq_chip);
476 /* This will let us handle the parent IRQ in the driver */
477 girq->parent_handler = NULL;
478 girq->num_parents = 0;
479 girq->parents = NULL;
480 girq->default_type = IRQ_TYPE_NONE;
481 girq->handler = handle_simple_irq;
482 girq->threaded = true;
483
484 ret = devm_gpiochip_add_data(&pdev->dev, &chip->gc, chip);
485 if (ret < 0)
486 return dev_err_probe(dev: &pdev->dev, err: ret,
487 fmt: "Failed to add GPIO chip\n");
488
489 irq_flags = IRQF_ONESHOT | IRQF_SHARED;
490 irqd = irq_get_irq_data(irq);
491 if (irqd)
492 irq_flags |= irqd_get_trigger_type(d: irqd);
493
494 ret = devm_request_threaded_irq(dev: &pdev->dev, irq, NULL,
495 thread_fn: max77759_gpio_irqhandler, irqflags: irq_flags,
496 devname: dev_name(dev: &pdev->dev), dev_id: chip);
497 if (ret < 0)
498 return dev_err_probe(dev: &pdev->dev, err: ret,
499 fmt: "Failed to request IRQ\n");
500
501 return ret;
502}
503
504static const struct of_device_id max77759_gpio_of_id[] = {
505 { .compatible = "maxim,max77759-gpio", },
506 { }
507};
508MODULE_DEVICE_TABLE(of, max77759_gpio_of_id);
509
510static const struct platform_device_id max77759_gpio_platform_id[] = {
511 { "max77759-gpio", },
512 { }
513};
514MODULE_DEVICE_TABLE(platform, max77759_gpio_platform_id);
515
516static struct platform_driver max77759_gpio_driver = {
517 .driver = {
518 .name = "max77759-gpio",
519 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
520 .of_match_table = max77759_gpio_of_id,
521 },
522 .probe = max77759_gpio_probe,
523 .id_table = max77759_gpio_platform_id,
524};
525
526module_platform_driver(max77759_gpio_driver);
527
528MODULE_AUTHOR("André Draszik <andre.draszik@linaro.org>");
529MODULE_DESCRIPTION("GPIO driver for Maxim MAX77759");
530MODULE_LICENSE("GPL");
531

source code of linux/drivers/gpio/gpio-max77759.c