| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* |
| 3 | * Copyright 2020 Google Inc. |
| 4 | * Copyright 2025 Linaro Ltd. |
| 5 | * |
| 6 | * Maxim MAX77759 core driver |
| 7 | */ |
| 8 | |
| 9 | #ifndef __LINUX_MFD_MAX77759_H |
| 10 | #define __LINUX_MFD_MAX77759_H |
| 11 | |
| 12 | #include <linux/completion.h> |
| 13 | #include <linux/mutex.h> |
| 14 | #include <linux/regmap.h> |
| 15 | |
| 16 | #define MAX77759_PMIC_REG_PMIC_ID 0x00 |
| 17 | #define MAX77759_PMIC_REG_PMIC_REVISION 0x01 |
| 18 | #define MAX77759_PMIC_REG_OTP_REVISION 0x02 |
| 19 | #define MAX77759_PMIC_REG_INTSRC 0x22 |
| 20 | #define MAX77759_PMIC_REG_INTSRCMASK 0x23 |
| 21 | #define MAX77759_PMIC_REG_INTSRC_MAXQ BIT(3) |
| 22 | #define MAX77759_PMIC_REG_INTSRC_TOPSYS BIT(1) |
| 23 | #define MAX77759_PMIC_REG_INTSRC_CHGR BIT(0) |
| 24 | #define MAX77759_PMIC_REG_TOPSYS_INT 0x24 |
| 25 | #define MAX77759_PMIC_REG_TOPSYS_INT_MASK 0x26 |
| 26 | #define MAX77759_PMIC_REG_TOPSYS_INT_TSHDN BIT(6) |
| 27 | #define MAX77759_PMIC_REG_TOPSYS_INT_SYSOVLO BIT(5) |
| 28 | #define MAX77759_PMIC_REG_TOPSYS_INT_SYSUVLO BIT(4) |
| 29 | #define MAX77759_PMIC_REG_TOPSYS_INT_FSHIP BIT(0) |
| 30 | #define MAX77759_PMIC_REG_I2C_CNFG 0x40 |
| 31 | #define MAX77759_PMIC_REG_SWRESET 0x50 |
| 32 | #define MAX77759_PMIC_REG_CONTROL_FG 0x51 |
| 33 | |
| 34 | #define MAX77759_MAXQ_REG_UIC_INT1 0x64 |
| 35 | #define MAX77759_MAXQ_REG_UIC_INT1_APCMDRESI BIT(7) |
| 36 | #define MAX77759_MAXQ_REG_UIC_INT1_SYSMSGI BIT(6) |
| 37 | #define MAX77759_MAXQ_REG_UIC_INT1_GPIO6I BIT(1) |
| 38 | #define MAX77759_MAXQ_REG_UIC_INT1_GPIO5I BIT(0) |
| 39 | #define MAX77759_MAXQ_REG_UIC_INT1_GPIOxI(offs, en) (((en) & 1) << (offs)) |
| 40 | #define MAX77759_MAXQ_REG_UIC_INT1_GPIOxI_MASK(offs) \ |
| 41 | MAX77759_MAXQ_REG_UIC_INT1_GPIOxI(offs, ~0) |
| 42 | #define MAX77759_MAXQ_REG_UIC_INT2 0x65 |
| 43 | #define MAX77759_MAXQ_REG_UIC_INT3 0x66 |
| 44 | #define MAX77759_MAXQ_REG_UIC_INT4 0x67 |
| 45 | #define MAX77759_MAXQ_REG_UIC_UIC_STATUS1 0x68 |
| 46 | #define MAX77759_MAXQ_REG_UIC_UIC_STATUS2 0x69 |
| 47 | #define MAX77759_MAXQ_REG_UIC_UIC_STATUS3 0x6a |
| 48 | #define MAX77759_MAXQ_REG_UIC_UIC_STATUS4 0x6b |
| 49 | #define MAX77759_MAXQ_REG_UIC_UIC_STATUS5 0x6c |
| 50 | #define MAX77759_MAXQ_REG_UIC_UIC_STATUS6 0x6d |
| 51 | #define MAX77759_MAXQ_REG_UIC_UIC_STATUS7 0x6f |
| 52 | #define MAX77759_MAXQ_REG_UIC_UIC_STATUS8 0x6f |
| 53 | #define MAX77759_MAXQ_REG_UIC_INT1_M 0x70 |
| 54 | #define MAX77759_MAXQ_REG_UIC_INT2_M 0x71 |
| 55 | #define MAX77759_MAXQ_REG_UIC_INT3_M 0x72 |
| 56 | #define MAX77759_MAXQ_REG_UIC_INT4_M 0x73 |
| 57 | #define MAX77759_MAXQ_REG_AP_DATAOUT0 0x81 |
| 58 | #define MAX77759_MAXQ_REG_AP_DATAOUT32 0xa1 |
| 59 | #define MAX77759_MAXQ_REG_AP_DATAIN0 0xb1 |
| 60 | #define MAX77759_MAXQ_REG_UIC_SWRST 0xe0 |
| 61 | |
| 62 | #define MAX77759_CHGR_REG_CHG_INT 0xb0 |
| 63 | #define MAX77759_CHGR_REG_CHG_INT2 0xb1 |
| 64 | #define MAX77759_CHGR_REG_CHG_INT_MASK 0xb2 |
| 65 | #define MAX77759_CHGR_REG_CHG_INT2_MASK 0xb3 |
| 66 | #define MAX77759_CHGR_REG_CHG_INT_OK 0xb4 |
| 67 | #define MAX77759_CHGR_REG_CHG_DETAILS_00 0xb5 |
| 68 | #define MAX77759_CHGR_REG_CHG_DETAILS_01 0xb6 |
| 69 | #define MAX77759_CHGR_REG_CHG_DETAILS_02 0xb7 |
| 70 | #define MAX77759_CHGR_REG_CHG_DETAILS_03 0xb8 |
| 71 | #define MAX77759_CHGR_REG_CHG_CNFG_00 0xb9 |
| 72 | #define MAX77759_CHGR_REG_CHG_CNFG_01 0xba |
| 73 | #define MAX77759_CHGR_REG_CHG_CNFG_02 0xbb |
| 74 | #define MAX77759_CHGR_REG_CHG_CNFG_03 0xbc |
| 75 | #define MAX77759_CHGR_REG_CHG_CNFG_04 0xbd |
| 76 | #define MAX77759_CHGR_REG_CHG_CNFG_05 0xbe |
| 77 | #define MAX77759_CHGR_REG_CHG_CNFG_06 0xbf |
| 78 | #define MAX77759_CHGR_REG_CHG_CNFG_07 0xc0 |
| 79 | #define MAX77759_CHGR_REG_CHG_CNFG_08 0xc1 |
| 80 | #define MAX77759_CHGR_REG_CHG_CNFG_09 0xc2 |
| 81 | #define MAX77759_CHGR_REG_CHG_CNFG_10 0xc3 |
| 82 | #define MAX77759_CHGR_REG_CHG_CNFG_11 0xc4 |
| 83 | #define MAX77759_CHGR_REG_CHG_CNFG_12 0xc5 |
| 84 | #define MAX77759_CHGR_REG_CHG_CNFG_13 0xc6 |
| 85 | #define MAX77759_CHGR_REG_CHG_CNFG_14 0xc7 |
| 86 | #define MAX77759_CHGR_REG_CHG_CNFG_15 0xc8 |
| 87 | #define MAX77759_CHGR_REG_CHG_CNFG_16 0xc9 |
| 88 | #define MAX77759_CHGR_REG_CHG_CNFG_17 0xca |
| 89 | #define MAX77759_CHGR_REG_CHG_CNFG_18 0xcb |
| 90 | #define MAX77759_CHGR_REG_CHG_CNFG_19 0xcc |
| 91 | |
| 92 | /* MaxQ opcodes for max77759_maxq_command() */ |
| 93 | #define MAX77759_MAXQ_OPCODE_MAXLENGTH (MAX77759_MAXQ_REG_AP_DATAOUT32 - \ |
| 94 | MAX77759_MAXQ_REG_AP_DATAOUT0 + \ |
| 95 | 1) |
| 96 | |
| 97 | #define MAX77759_MAXQ_OPCODE_GPIO_TRIGGER_READ 0x21 |
| 98 | #define MAX77759_MAXQ_OPCODE_GPIO_TRIGGER_WRITE 0x22 |
| 99 | #define MAX77759_MAXQ_OPCODE_GPIO_CONTROL_READ 0x23 |
| 100 | #define MAX77759_MAXQ_OPCODE_GPIO_CONTROL_WRITE 0x24 |
| 101 | #define MAX77759_MAXQ_OPCODE_USER_SPACE_READ 0x81 |
| 102 | #define MAX77759_MAXQ_OPCODE_USER_SPACE_WRITE 0x82 |
| 103 | |
| 104 | /** |
| 105 | * struct max77759 - core max77759 internal data structure |
| 106 | * |
| 107 | * @regmap_top: Regmap for accessing TOP registers |
| 108 | * @maxq_lock: Lock for serializing access to MaxQ |
| 109 | * @regmap_maxq: Regmap for accessing MaxQ registers |
| 110 | * @cmd_done: Used to signal completion of a MaxQ command |
| 111 | * @regmap_charger: Regmap for accessing charger registers |
| 112 | * |
| 113 | * The MAX77759 comprises several sub-blocks, namely TOP, MaxQ, Charger, |
| 114 | * Fuel Gauge, and TCPCI. |
| 115 | */ |
| 116 | struct max77759 { |
| 117 | struct regmap *regmap_top; |
| 118 | |
| 119 | /* This protects MaxQ commands - only one can be active */ |
| 120 | struct mutex maxq_lock; |
| 121 | struct regmap *regmap_maxq; |
| 122 | struct completion cmd_done; |
| 123 | |
| 124 | struct regmap *regmap_charger; |
| 125 | }; |
| 126 | |
| 127 | /** |
| 128 | * struct max77759_maxq_command - structure containing the MaxQ command to |
| 129 | * send |
| 130 | * |
| 131 | * @length: The number of bytes to send. |
| 132 | * @cmd: The data to send. |
| 133 | */ |
| 134 | struct max77759_maxq_command { |
| 135 | u8 length; |
| 136 | u8 cmd[] __counted_by(length); |
| 137 | }; |
| 138 | |
| 139 | /** |
| 140 | * struct max77759_maxq_response - structure containing the MaxQ response |
| 141 | * |
| 142 | * @length: The number of bytes to receive. |
| 143 | * @rsp: The data received. Must have at least @length bytes space. |
| 144 | */ |
| 145 | struct max77759_maxq_response { |
| 146 | u8 length; |
| 147 | u8 rsp[] __counted_by(length); |
| 148 | }; |
| 149 | |
| 150 | /** |
| 151 | * max77759_maxq_command() - issue a MaxQ command and wait for the response |
| 152 | * and associated data |
| 153 | * |
| 154 | * @max77759: The core max77759 device handle. |
| 155 | * @cmd: The command to be sent. |
| 156 | * @rsp: Any response data associated with the command will be copied here; |
| 157 | * can be %NULL if the command has no response (other than ACK). |
| 158 | * |
| 159 | * Return: 0 on success, a negative error number otherwise. |
| 160 | */ |
| 161 | int max77759_maxq_command(struct max77759 *max77759, |
| 162 | const struct max77759_maxq_command *cmd, |
| 163 | struct max77759_maxq_response *rsp); |
| 164 | |
| 165 | #endif /* __LINUX_MFD_MAX77759_H */ |
| 166 | |