1// SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only)
2/* Copyright(c) 2014 - 2020 Intel Corporation */
3#include "adf_accel_devices.h"
4#include "adf_common_drv.h"
5#include "adf_transport_internal.h"
6
7#define ADF_ARB_NUM 4
8#define ADF_ARB_REG_SIZE 0x4
9
10#define WRITE_CSR_ARB_SARCONFIG(csr_addr, arb_offset, index, value) \
11 ADF_CSR_WR(csr_addr, (arb_offset) + \
12 (ADF_ARB_REG_SIZE * (index)), value)
13
14#define WRITE_CSR_ARB_WT2SAM(csr_addr, arb_offset, wt_offset, index, value) \
15 ADF_CSR_WR(csr_addr, ((arb_offset) + (wt_offset)) + \
16 (ADF_ARB_REG_SIZE * (index)), value)
17
18int adf_init_arb(struct adf_accel_dev *accel_dev)
19{
20 struct adf_hw_device_data *hw_data = accel_dev->hw_device;
21 void __iomem *csr = accel_dev->transport->banks[0].csr_addr;
22 unsigned long ae_mask = hw_data->ae_mask;
23 u32 arb_off, wt_off, arb_cfg;
24 const u32 *thd_2_arb_cfg;
25 struct arb_info info;
26 int arb, i;
27
28 hw_data->get_arb_info(&info);
29 arb_cfg = info.arb_cfg;
30 arb_off = info.arb_offset;
31 wt_off = info.wt2sam_offset;
32
33 /* Service arb configured for 32 bytes responses and
34 * ring flow control check enabled. */
35 for (arb = 0; arb < ADF_ARB_NUM; arb++)
36 WRITE_CSR_ARB_SARCONFIG(csr, arb_off, arb, arb_cfg);
37
38 /* Map worker threads to service arbiters */
39 thd_2_arb_cfg = hw_data->get_arb_mapping(accel_dev);
40
41 for_each_set_bit(i, &ae_mask, hw_data->num_engines)
42 WRITE_CSR_ARB_WT2SAM(csr, arb_off, wt_off, i, thd_2_arb_cfg[i]);
43
44 return 0;
45}
46EXPORT_SYMBOL_GPL(adf_init_arb);
47
48void adf_update_ring_arb(struct adf_etr_ring_data *ring)
49{
50 struct adf_accel_dev *accel_dev = ring->bank->accel_dev;
51 struct adf_hw_device_data *hw_data = accel_dev->hw_device;
52 struct adf_hw_csr_ops *csr_ops = GET_CSR_OPS(accel_dev);
53 u32 tx_ring_mask = hw_data->tx_rings_mask;
54 u32 shift = hw_data->tx_rx_gap;
55 u32 arben, arben_tx, arben_rx;
56 u32 rx_ring_mask;
57
58 /*
59 * Enable arbitration on a ring only if the TX half of the ring mask
60 * matches the RX part. This results in writes to CSR on both TX and
61 * RX update - only one is necessary, but both are done for
62 * simplicity.
63 */
64 rx_ring_mask = tx_ring_mask << shift;
65 arben_tx = (ring->bank->ring_mask & tx_ring_mask) >> 0;
66 arben_rx = (ring->bank->ring_mask & rx_ring_mask) >> shift;
67 arben = arben_tx & arben_rx;
68
69 csr_ops->write_csr_ring_srv_arb_en(ring->bank->csr_addr,
70 ring->bank->bank_number, arben);
71}
72
73void adf_exit_arb(struct adf_accel_dev *accel_dev)
74{
75 struct adf_hw_device_data *hw_data = accel_dev->hw_device;
76 struct adf_hw_csr_ops *csr_ops = GET_CSR_OPS(accel_dev);
77 u32 arb_off, wt_off;
78 struct arb_info info;
79 void __iomem *csr;
80 unsigned int i;
81
82 hw_data->get_arb_info(&info);
83 arb_off = info.arb_offset;
84 wt_off = info.wt2sam_offset;
85
86 if (!accel_dev->transport)
87 return;
88
89 csr = accel_dev->transport->banks[0].csr_addr;
90
91 hw_data->get_arb_info(&info);
92
93 /* Unmap worker threads to service arbiters */
94 for (i = 0; i < hw_data->num_engines; i++)
95 WRITE_CSR_ARB_WT2SAM(csr, arb_off, wt_off, i, 0);
96
97 /* Disable arbitration on all rings */
98 for (i = 0; i < GET_MAX_BANKS(accel_dev); i++)
99 csr_ops->write_csr_ring_srv_arb_en(csr, i, 0);
100}
101EXPORT_SYMBOL_GPL(adf_exit_arb);
102
103int adf_disable_arb_thd(struct adf_accel_dev *accel_dev, u32 ae, u32 thr)
104{
105 void __iomem *csr = accel_dev->transport->banks[0].csr_addr;
106 struct adf_hw_device_data *hw_data = accel_dev->hw_device;
107 const u32 *thd_2_arb_cfg;
108 struct arb_info info;
109 u32 ae_thr_map;
110
111 if (ADF_AE_STRAND0_THREAD == thr || ADF_AE_STRAND1_THREAD == thr)
112 thr = ADF_AE_ADMIN_THREAD;
113
114 hw_data->get_arb_info(&info);
115 thd_2_arb_cfg = hw_data->get_arb_mapping(accel_dev);
116 if (!thd_2_arb_cfg)
117 return -EFAULT;
118
119 /* Disable scheduling for this particular AE and thread */
120 ae_thr_map = *(thd_2_arb_cfg + ae);
121 ae_thr_map &= ~(GENMASK(3, 0) << (thr * BIT(2)));
122
123 WRITE_CSR_ARB_WT2SAM(csr, info.arb_offset, info.wt2sam_offset, ae,
124 ae_thr_map);
125 return 0;
126}
127

source code of linux/drivers/crypto/intel/qat/qat_common/adf_hw_arbiter.c