1// SPDX-License-Identifier: GPL-2.0-only
2/* Copyright (c) 2023 Intel Corporation. */
3#include <linux/export.h>
4#include <linux/kernel.h>
5
6#include "adf_gen4_tl.h"
7#include "adf_telemetry.h"
8#include "adf_tl_debugfs.h"
9
10#define ADF_GEN4_TL_DEV_REG_OFF(reg) ADF_TL_DEV_REG_OFF(reg, gen4)
11
12#define ADF_GEN4_TL_RP_REG_OFF(reg) ADF_TL_RP_REG_OFF(reg, gen4)
13
14#define ADF_GEN4_TL_SL_UTIL_COUNTER(_name) \
15 ADF_TL_COUNTER("util_" #_name, \
16 ADF_TL_SIMPLE_COUNT, \
17 ADF_TL_SLICE_REG_OFF(_name, reg_tm_slice_util, gen4))
18
19#define ADF_GEN4_TL_SL_EXEC_COUNTER(_name) \
20 ADF_TL_COUNTER("exec_" #_name, \
21 ADF_TL_SIMPLE_COUNT, \
22 ADF_TL_SLICE_REG_OFF(_name, reg_tm_slice_exec_cnt, gen4))
23
24/* Device level counters. */
25static const struct adf_tl_dbg_counter dev_counters[] = {
26 /* PCIe partial transactions. */
27 ADF_TL_COUNTER(PCI_TRANS_CNT_NAME, ADF_TL_SIMPLE_COUNT,
28 ADF_GEN4_TL_DEV_REG_OFF(reg_tl_pci_trans_cnt)),
29 /* Max read latency[ns]. */
30 ADF_TL_COUNTER(MAX_RD_LAT_NAME, ADF_TL_COUNTER_NS,
31 ADF_GEN4_TL_DEV_REG_OFF(reg_tl_rd_lat_max)),
32 /* Read latency average[ns]. */
33 ADF_TL_COUNTER_LATENCY(RD_LAT_ACC_NAME, ADF_TL_COUNTER_NS_AVG,
34 ADF_GEN4_TL_DEV_REG_OFF(reg_tl_rd_lat_acc),
35 ADF_GEN4_TL_DEV_REG_OFF(reg_tl_rd_cmpl_cnt)),
36 /* Max get to put latency[ns]. */
37 ADF_TL_COUNTER(MAX_LAT_NAME, ADF_TL_COUNTER_NS,
38 ADF_GEN4_TL_DEV_REG_OFF(reg_tl_gp_lat_max)),
39 /* Get to put latency average[ns]. */
40 ADF_TL_COUNTER_LATENCY(LAT_ACC_NAME, ADF_TL_COUNTER_NS_AVG,
41 ADF_GEN4_TL_DEV_REG_OFF(reg_tl_gp_lat_acc),
42 ADF_GEN4_TL_DEV_REG_OFF(reg_tl_ae_put_cnt)),
43 /* PCIe write bandwidth[Mbps]. */
44 ADF_TL_COUNTER(BW_IN_NAME, ADF_TL_COUNTER_MBPS,
45 ADF_GEN4_TL_DEV_REG_OFF(reg_tl_bw_in)),
46 /* PCIe read bandwidth[Mbps]. */
47 ADF_TL_COUNTER(BW_OUT_NAME, ADF_TL_COUNTER_MBPS,
48 ADF_GEN4_TL_DEV_REG_OFF(reg_tl_bw_out)),
49 /* Page request latency average[ns]. */
50 ADF_TL_COUNTER_LATENCY(PAGE_REQ_LAT_NAME, ADF_TL_COUNTER_NS_AVG,
51 ADF_GEN4_TL_DEV_REG_OFF(reg_tl_at_page_req_lat_acc),
52 ADF_GEN4_TL_DEV_REG_OFF(reg_tl_at_page_req_cnt)),
53 /* Page translation latency average[ns]. */
54 ADF_TL_COUNTER_LATENCY(AT_TRANS_LAT_NAME, ADF_TL_COUNTER_NS_AVG,
55 ADF_GEN4_TL_DEV_REG_OFF(reg_tl_at_trans_lat_acc),
56 ADF_GEN4_TL_DEV_REG_OFF(reg_tl_at_trans_lat_cnt)),
57 /* Maximum uTLB used. */
58 ADF_TL_COUNTER(AT_MAX_UTLB_USED_NAME, ADF_TL_SIMPLE_COUNT,
59 ADF_GEN4_TL_DEV_REG_OFF(reg_tl_at_max_tlb_used)),
60};
61
62/* Slice utilization counters. */
63static const struct adf_tl_dbg_counter sl_util_counters[ADF_TL_SL_CNT_COUNT] = {
64 /* Compression slice utilization. */
65 ADF_GEN4_TL_SL_UTIL_COUNTER(cpr),
66 /* Translator slice utilization. */
67 ADF_GEN4_TL_SL_UTIL_COUNTER(xlt),
68 /* Decompression slice utilization. */
69 ADF_GEN4_TL_SL_UTIL_COUNTER(dcpr),
70 /* PKE utilization. */
71 ADF_GEN4_TL_SL_UTIL_COUNTER(pke),
72 /* Wireless Authentication slice utilization. */
73 ADF_GEN4_TL_SL_UTIL_COUNTER(wat),
74 /* Wireless Cipher slice utilization. */
75 ADF_GEN4_TL_SL_UTIL_COUNTER(wcp),
76 /* UCS slice utilization. */
77 ADF_GEN4_TL_SL_UTIL_COUNTER(ucs),
78 /* Cipher slice utilization. */
79 ADF_GEN4_TL_SL_UTIL_COUNTER(cph),
80 /* Authentication slice utilization. */
81 ADF_GEN4_TL_SL_UTIL_COUNTER(ath),
82};
83
84/* Slice execution counters. */
85static const struct adf_tl_dbg_counter sl_exec_counters[ADF_TL_SL_CNT_COUNT] = {
86 /* Compression slice execution count. */
87 ADF_GEN4_TL_SL_EXEC_COUNTER(cpr),
88 /* Translator slice execution count. */
89 ADF_GEN4_TL_SL_EXEC_COUNTER(xlt),
90 /* Decompression slice execution count. */
91 ADF_GEN4_TL_SL_EXEC_COUNTER(dcpr),
92 /* PKE execution count. */
93 ADF_GEN4_TL_SL_EXEC_COUNTER(pke),
94 /* Wireless Authentication slice execution count. */
95 ADF_GEN4_TL_SL_EXEC_COUNTER(wat),
96 /* Wireless Cipher slice execution count. */
97 ADF_GEN4_TL_SL_EXEC_COUNTER(wcp),
98 /* UCS slice execution count. */
99 ADF_GEN4_TL_SL_EXEC_COUNTER(ucs),
100 /* Cipher slice execution count. */
101 ADF_GEN4_TL_SL_EXEC_COUNTER(cph),
102 /* Authentication slice execution count. */
103 ADF_GEN4_TL_SL_EXEC_COUNTER(ath),
104};
105
106/* Ring pair counters. */
107static const struct adf_tl_dbg_counter rp_counters[] = {
108 /* PCIe partial transactions. */
109 ADF_TL_COUNTER(PCI_TRANS_CNT_NAME, ADF_TL_SIMPLE_COUNT,
110 ADF_GEN4_TL_RP_REG_OFF(reg_tl_pci_trans_cnt)),
111 /* Get to put latency average[ns]. */
112 ADF_TL_COUNTER_LATENCY(LAT_ACC_NAME, ADF_TL_COUNTER_NS_AVG,
113 ADF_GEN4_TL_RP_REG_OFF(reg_tl_gp_lat_acc),
114 ADF_GEN4_TL_RP_REG_OFF(reg_tl_ae_put_cnt)),
115 /* PCIe write bandwidth[Mbps]. */
116 ADF_TL_COUNTER(BW_IN_NAME, ADF_TL_COUNTER_MBPS,
117 ADF_GEN4_TL_RP_REG_OFF(reg_tl_bw_in)),
118 /* PCIe read bandwidth[Mbps]. */
119 ADF_TL_COUNTER(BW_OUT_NAME, ADF_TL_COUNTER_MBPS,
120 ADF_GEN4_TL_RP_REG_OFF(reg_tl_bw_out)),
121 /* Message descriptor DevTLB hit rate. */
122 ADF_TL_COUNTER(AT_GLOB_DTLB_HIT_NAME, ADF_TL_SIMPLE_COUNT,
123 ADF_GEN4_TL_RP_REG_OFF(reg_tl_at_glob_devtlb_hit)),
124 /* Message descriptor DevTLB miss rate. */
125 ADF_TL_COUNTER(AT_GLOB_DTLB_MISS_NAME, ADF_TL_SIMPLE_COUNT,
126 ADF_GEN4_TL_RP_REG_OFF(reg_tl_at_glob_devtlb_miss)),
127 /* Payload DevTLB hit rate. */
128 ADF_TL_COUNTER(AT_PAYLD_DTLB_HIT_NAME, ADF_TL_SIMPLE_COUNT,
129 ADF_GEN4_TL_RP_REG_OFF(reg_tl_at_payld_devtlb_hit)),
130 /* Payload DevTLB miss rate. */
131 ADF_TL_COUNTER(AT_PAYLD_DTLB_MISS_NAME, ADF_TL_SIMPLE_COUNT,
132 ADF_GEN4_TL_RP_REG_OFF(reg_tl_at_payld_devtlb_miss)),
133};
134
135void adf_gen4_init_tl_data(struct adf_tl_hw_data *tl_data)
136{
137 tl_data->layout_sz = ADF_GEN4_TL_LAYOUT_SZ;
138 tl_data->slice_reg_sz = ADF_GEN4_TL_SLICE_REG_SZ;
139 tl_data->rp_reg_sz = ADF_GEN4_TL_RP_REG_SZ;
140 tl_data->num_hbuff = ADF_GEN4_TL_NUM_HIST_BUFFS;
141 tl_data->max_rp = ADF_GEN4_TL_MAX_RP_NUM;
142 tl_data->msg_cnt_off = ADF_GEN4_TL_MSG_CNT_OFF;
143 tl_data->cpp_ns_per_cycle = ADF_GEN4_CPP_NS_PER_CYCLE;
144 tl_data->bw_units_to_bytes = ADF_GEN4_TL_BW_HW_UNITS_TO_BYTES;
145
146 tl_data->dev_counters = dev_counters;
147 tl_data->num_dev_counters = ARRAY_SIZE(dev_counters);
148 tl_data->sl_util_counters = sl_util_counters;
149 tl_data->sl_exec_counters = sl_exec_counters;
150 tl_data->rp_counters = rp_counters;
151 tl_data->num_rp_counters = ARRAY_SIZE(rp_counters);
152 tl_data->max_sl_cnt = ADF_GEN4_TL_MAX_SLICES_PER_TYPE;
153}
154EXPORT_SYMBOL_GPL(adf_gen4_init_tl_data);
155

source code of linux/drivers/crypto/intel/qat/qat_common/adf_gen4_tl.c