1// SPDX-License-Identifier: GPL-2.0-only
2/* Copyright(c) 2023 Intel Corporation */
3#include <linux/dma-mapping.h>
4#include <linux/string_helpers.h>
5
6#include "adf_accel_devices.h"
7#include "adf_admin.h"
8#include "adf_common_drv.h"
9#include "adf_gen4_pm.h"
10#include "adf_pm_dbgfs_utils.h"
11#include "icp_qat_fw_init_admin.h"
12
13#define PM_INFO_REGSET_ENTRY(_reg_, _field_) \
14 PM_INFO_REGSET_ENTRY_MASK(_reg_, _field_, ADF_GEN4_PM_##_field_##_MASK)
15
16static const struct pm_status_row pm_fuse_rows[] = {
17 PM_INFO_REGSET_ENTRY(fusectl0, ENABLE_PM),
18 PM_INFO_REGSET_ENTRY(fusectl0, ENABLE_PM_IDLE),
19 PM_INFO_REGSET_ENTRY(fusectl0, ENABLE_DEEP_PM_IDLE),
20};
21
22static const struct pm_status_row pm_info_rows[] = {
23 PM_INFO_REGSET_ENTRY(pm.status, CPM_PM_STATE),
24 PM_INFO_REGSET_ENTRY(pm.status, PENDING_WP),
25 PM_INFO_REGSET_ENTRY(pm.status, CURRENT_WP),
26 PM_INFO_REGSET_ENTRY(pm.fw_init, IDLE_ENABLE),
27 PM_INFO_REGSET_ENTRY(pm.fw_init, IDLE_FILTER),
28 PM_INFO_REGSET_ENTRY(pm.main, MIN_PWR_ACK),
29 PM_INFO_REGSET_ENTRY(pm.thread, MIN_PWR_ACK_PENDING),
30 PM_INFO_REGSET_ENTRY(pm.main, THR_VALUE),
31};
32
33static const struct pm_status_row pm_ssm_rows[] = {
34 PM_INFO_REGSET_ENTRY(ssm.pm_enable, SSM_PM_ENABLE),
35 PM_INFO_REGSET_ENTRY32(ssm.active_constraint, ACTIVE_CONSTRAINT),
36 PM_INFO_REGSET_ENTRY(ssm.pm_domain_status, DOMAIN_POWER_GATED),
37 PM_INFO_REGSET_ENTRY(ssm.pm_active_status, ATH_ACTIVE_COUNT),
38 PM_INFO_REGSET_ENTRY(ssm.pm_active_status, CPH_ACTIVE_COUNT),
39 PM_INFO_REGSET_ENTRY(ssm.pm_active_status, PKE_ACTIVE_COUNT),
40 PM_INFO_REGSET_ENTRY(ssm.pm_active_status, CPR_ACTIVE_COUNT),
41 PM_INFO_REGSET_ENTRY(ssm.pm_active_status, DCPR_ACTIVE_COUNT),
42 PM_INFO_REGSET_ENTRY(ssm.pm_active_status, UCS_ACTIVE_COUNT),
43 PM_INFO_REGSET_ENTRY(ssm.pm_active_status, XLT_ACTIVE_COUNT),
44 PM_INFO_REGSET_ENTRY(ssm.pm_active_status, WAT_ACTIVE_COUNT),
45 PM_INFO_REGSET_ENTRY(ssm.pm_active_status, WCP_ACTIVE_COUNT),
46 PM_INFO_REGSET_ENTRY(ssm.pm_managed_status, ATH_MANAGED_COUNT),
47 PM_INFO_REGSET_ENTRY(ssm.pm_managed_status, CPH_MANAGED_COUNT),
48 PM_INFO_REGSET_ENTRY(ssm.pm_managed_status, PKE_MANAGED_COUNT),
49 PM_INFO_REGSET_ENTRY(ssm.pm_managed_status, CPR_MANAGED_COUNT),
50 PM_INFO_REGSET_ENTRY(ssm.pm_managed_status, DCPR_MANAGED_COUNT),
51 PM_INFO_REGSET_ENTRY(ssm.pm_managed_status, UCS_MANAGED_COUNT),
52 PM_INFO_REGSET_ENTRY(ssm.pm_managed_status, XLT_MANAGED_COUNT),
53 PM_INFO_REGSET_ENTRY(ssm.pm_managed_status, WAT_MANAGED_COUNT),
54 PM_INFO_REGSET_ENTRY(ssm.pm_managed_status, WCP_MANAGED_COUNT),
55};
56
57static const struct pm_status_row pm_log_rows[] = {
58 PM_INFO_REGSET_ENTRY32(event_counters.host_msg, HOST_MSG_EVENT_COUNT),
59 PM_INFO_REGSET_ENTRY32(event_counters.sys_pm, SYS_PM_EVENT_COUNT),
60 PM_INFO_REGSET_ENTRY32(event_counters.local_ssm, SSM_EVENT_COUNT),
61 PM_INFO_REGSET_ENTRY32(event_counters.timer, TIMER_EVENT_COUNT),
62 PM_INFO_REGSET_ENTRY32(event_counters.unknown, UNKNOWN_EVENT_COUNT),
63};
64
65static const struct pm_status_row pm_event_rows[ICP_QAT_NUMBER_OF_PM_EVENTS] = {
66 PM_INFO_REGSET_ENTRY32(event_log[0], EVENT0),
67 PM_INFO_REGSET_ENTRY32(event_log[1], EVENT1),
68 PM_INFO_REGSET_ENTRY32(event_log[2], EVENT2),
69 PM_INFO_REGSET_ENTRY32(event_log[3], EVENT3),
70 PM_INFO_REGSET_ENTRY32(event_log[4], EVENT4),
71 PM_INFO_REGSET_ENTRY32(event_log[5], EVENT5),
72 PM_INFO_REGSET_ENTRY32(event_log[6], EVENT6),
73 PM_INFO_REGSET_ENTRY32(event_log[7], EVENT7),
74};
75
76static const struct pm_status_row pm_csrs_rows[] = {
77 PM_INFO_REGSET_ENTRY32(pm.fw_init, CPM_PM_FW_INIT),
78 PM_INFO_REGSET_ENTRY32(pm.status, CPM_PM_STATUS),
79 PM_INFO_REGSET_ENTRY32(pm.main, CPM_PM_MASTER_FW),
80 PM_INFO_REGSET_ENTRY32(pm.pwrreq, CPM_PM_PWRREQ),
81};
82
83static_assert(sizeof(struct icp_qat_fw_init_admin_pm_info) < PAGE_SIZE);
84
85static ssize_t adf_gen4_print_pm_status(struct adf_accel_dev *accel_dev,
86 char __user *buf, size_t count,
87 loff_t *pos)
88{
89 void __iomem *pmisc = adf_get_pmisc_base(accel_dev);
90 struct adf_pm *pm = &accel_dev->power_management;
91 struct icp_qat_fw_init_admin_pm_info *pm_info;
92 dma_addr_t p_state_addr;
93 u32 *pm_info_regs;
94 char *pm_kv;
95 int len = 0;
96 u32 val;
97 int ret;
98
99 pm_info = kmalloc(PAGE_SIZE, GFP_KERNEL);
100 if (!pm_info)
101 return -ENOMEM;
102
103 pm_kv = kmalloc(PAGE_SIZE, GFP_KERNEL);
104 if (!pm_kv) {
105 ret = -ENOMEM;
106 goto out_free;
107 }
108
109 p_state_addr = dma_map_single(&GET_DEV(accel_dev), pm_info, PAGE_SIZE,
110 DMA_FROM_DEVICE);
111 ret = dma_mapping_error(dev: &GET_DEV(accel_dev), dma_addr: p_state_addr);
112 if (ret)
113 goto out_free;
114
115 /* Query PM info from QAT FW */
116 ret = adf_get_pm_info(accel_dev, p_state_addr, PAGE_SIZE);
117 dma_unmap_single(&GET_DEV(accel_dev), p_state_addr, PAGE_SIZE,
118 DMA_FROM_DEVICE);
119 if (ret)
120 goto out_free;
121
122 pm_info_regs = (u32 *)pm_info;
123
124 /* Fusectl related */
125 len += scnprintf(buf: &pm_kv[len], PAGE_SIZE - len,
126 fmt: "----------- PM Fuse info ---------\n");
127 len += adf_pm_scnprint_table_lower_keys(buff: &pm_kv[len], table: pm_fuse_rows,
128 pm_info_regs, PAGE_SIZE - len,
129 ARRAY_SIZE(pm_fuse_rows));
130 len += scnprintf(buf: &pm_kv[len], PAGE_SIZE - len, fmt: "max_pwrreq: %#x\n",
131 pm_info->max_pwrreq);
132 len += scnprintf(buf: &pm_kv[len], PAGE_SIZE - len, fmt: "min_pwrreq: %#x\n",
133 pm_info->min_pwrreq);
134
135 /* PM related */
136 len += scnprintf(buf: &pm_kv[len], PAGE_SIZE - len,
137 fmt: "------------ PM Info ------------\n");
138 len += scnprintf(buf: &pm_kv[len], PAGE_SIZE - len, fmt: "power_level: %s\n",
139 pm_info->pwr_state == PM_SET_MIN ? "min" : "max");
140 len += adf_pm_scnprint_table_lower_keys(buff: &pm_kv[len], table: pm_info_rows,
141 pm_info_regs, PAGE_SIZE - len,
142 ARRAY_SIZE(pm_info_rows));
143 len += scnprintf(buf: &pm_kv[len], PAGE_SIZE - len, fmt: "pm_mode: STATIC\n");
144
145 /* SSM related */
146 len += scnprintf(buf: &pm_kv[len], PAGE_SIZE - len,
147 fmt: "----------- SSM_PM Info ----------\n");
148 len += adf_pm_scnprint_table_lower_keys(buff: &pm_kv[len], table: pm_ssm_rows,
149 pm_info_regs, PAGE_SIZE - len,
150 ARRAY_SIZE(pm_ssm_rows));
151
152 /* Log related */
153 len += scnprintf(buf: &pm_kv[len], PAGE_SIZE - len,
154 fmt: "------------- PM Log -------------\n");
155 len += adf_pm_scnprint_table_lower_keys(buff: &pm_kv[len], table: pm_log_rows,
156 pm_info_regs, PAGE_SIZE - len,
157 ARRAY_SIZE(pm_log_rows));
158
159 len += adf_pm_scnprint_table_lower_keys(buff: &pm_kv[len], table: pm_event_rows,
160 pm_info_regs, PAGE_SIZE - len,
161 ARRAY_SIZE(pm_event_rows));
162
163 len += scnprintf(buf: &pm_kv[len], PAGE_SIZE - len, fmt: "idle_irq_count: %#x\n",
164 pm->idle_irq_counters);
165 len += scnprintf(buf: &pm_kv[len], PAGE_SIZE - len, fmt: "fw_irq_count: %#x\n",
166 pm->fw_irq_counters);
167 len += scnprintf(buf: &pm_kv[len], PAGE_SIZE - len,
168 fmt: "throttle_irq_count: %#x\n", pm->throttle_irq_counters);
169 len += scnprintf(buf: &pm_kv[len], PAGE_SIZE - len, fmt: "host_ack_count: %#x\n",
170 pm->host_ack_counter);
171 len += scnprintf(buf: &pm_kv[len], PAGE_SIZE - len, fmt: "host_nack_count: %#x\n",
172 pm->host_nack_counter);
173
174 /* CSRs content */
175 len += scnprintf(buf: &pm_kv[len], PAGE_SIZE - len,
176 fmt: "----------- HW PM CSRs -----------\n");
177 len += adf_pm_scnprint_table_upper_keys(buff: &pm_kv[len], table: pm_csrs_rows,
178 pm_info_regs, PAGE_SIZE - len,
179 ARRAY_SIZE(pm_csrs_rows));
180
181 val = ADF_CSR_RD(pmisc, ADF_GEN4_PM_HOST_MSG);
182 len += scnprintf(buf: &pm_kv[len], PAGE_SIZE - len,
183 fmt: "CPM_PM_HOST_MSG: %#x\n", val);
184 val = ADF_CSR_RD(pmisc, ADF_GEN4_PM_INTERRUPT);
185 len += scnprintf(buf: &pm_kv[len], PAGE_SIZE - len,
186 fmt: "CPM_PM_INTERRUPT: %#x\n", val);
187 ret = simple_read_from_buffer(to: buf, count, ppos: pos, from: pm_kv, available: len);
188
189out_free:
190 kfree(objp: pm_info);
191 kfree(objp: pm_kv);
192 return ret;
193}
194
195void adf_gen4_init_dev_pm_data(struct adf_accel_dev *accel_dev)
196{
197 accel_dev->power_management.print_pm_status = adf_gen4_print_pm_status;
198 accel_dev->power_management.present = true;
199}
200

source code of linux/drivers/crypto/intel/qat/qat_common/adf_gen4_pm_debugfs.c