1/* SPDX-License-Identifier: GPL-2.0-only */
2/* Copyright(c) 2024 Intel Corporation */
3#ifndef ADF_GEN2_HW_CSR_DATA_H_
4#define ADF_GEN2_HW_CSR_DATA_H_
5
6#include <linux/bitops.h>
7#include "adf_accel_devices.h"
8
9#define ADF_BANK_INT_SRC_SEL_MASK_0 0x4444444CUL
10#define ADF_BANK_INT_SRC_SEL_MASK_X 0x44444444UL
11#define ADF_RING_CSR_RING_CONFIG 0x000
12#define ADF_RING_CSR_RING_LBASE 0x040
13#define ADF_RING_CSR_RING_UBASE 0x080
14#define ADF_RING_CSR_RING_HEAD 0x0C0
15#define ADF_RING_CSR_RING_TAIL 0x100
16#define ADF_RING_CSR_E_STAT 0x14C
17#define ADF_RING_CSR_INT_FLAG 0x170
18#define ADF_RING_CSR_INT_SRCSEL 0x174
19#define ADF_RING_CSR_INT_SRCSEL_2 0x178
20#define ADF_RING_CSR_INT_COL_EN 0x17C
21#define ADF_RING_CSR_INT_COL_CTL 0x180
22#define ADF_RING_CSR_INT_FLAG_AND_COL 0x184
23#define ADF_RING_CSR_INT_COL_CTL_ENABLE 0x80000000
24#define ADF_RING_BUNDLE_SIZE 0x1000
25#define ADF_ARB_REG_SLOT 0x1000
26#define ADF_ARB_RINGSRVARBEN_OFFSET 0x19C
27
28#define BUILD_RING_BASE_ADDR(addr, size) \
29 (((addr) >> 6) & (GENMASK_ULL(63, 0) << (size)))
30#define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \
31 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
32 ADF_RING_CSR_RING_HEAD + ((ring) << 2))
33#define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \
34 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
35 ADF_RING_CSR_RING_TAIL + ((ring) << 2))
36#define READ_CSR_E_STAT(csr_base_addr, bank) \
37 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
38 ADF_RING_CSR_E_STAT)
39#define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \
40 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
41 ADF_RING_CSR_RING_CONFIG + ((ring) << 2), value)
42#define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \
43do { \
44 u32 l_base = 0, u_base = 0; \
45 l_base = (u32)((value) & 0xFFFFFFFF); \
46 u_base = (u32)(((value) & 0xFFFFFFFF00000000ULL) >> 32); \
47 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
48 ADF_RING_CSR_RING_LBASE + ((ring) << 2), l_base); \
49 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
50 ADF_RING_CSR_RING_UBASE + ((ring) << 2), u_base); \
51} while (0)
52
53#define WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value) \
54 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
55 ADF_RING_CSR_RING_HEAD + ((ring) << 2), value)
56#define WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value) \
57 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
58 ADF_RING_CSR_RING_TAIL + ((ring) << 2), value)
59#define WRITE_CSR_INT_FLAG(csr_base_addr, bank, value) \
60 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
61 ADF_RING_CSR_INT_FLAG, value)
62#define WRITE_CSR_INT_SRCSEL(csr_base_addr, bank) \
63do { \
64 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
65 ADF_RING_CSR_INT_SRCSEL, ADF_BANK_INT_SRC_SEL_MASK_0); \
66 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
67 ADF_RING_CSR_INT_SRCSEL_2, ADF_BANK_INT_SRC_SEL_MASK_X); \
68} while (0)
69#define WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value) \
70 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
71 ADF_RING_CSR_INT_COL_EN, value)
72#define WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value) \
73 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
74 ADF_RING_CSR_INT_COL_CTL, \
75 ADF_RING_CSR_INT_COL_CTL_ENABLE | (value))
76#define WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value) \
77 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
78 ADF_RING_CSR_INT_FLAG_AND_COL, value)
79
80#define WRITE_CSR_RING_SRV_ARB_EN(csr_addr, index, value) \
81 ADF_CSR_WR(csr_addr, ADF_ARB_RINGSRVARBEN_OFFSET + \
82 (ADF_ARB_REG_SLOT * (index)), value)
83
84void adf_gen2_init_hw_csr_ops(struct adf_hw_csr_ops *csr_ops);
85
86#endif
87

source code of linux/drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.h