1// SPDX-License-Identifier: GPL-2.0-only
2/* Copyright(c) 2022 Intel Corporation */
3#include "adf_accel_devices.h"
4#include "adf_dc.h"
5#include "icp_qat_fw_comp.h"
6
7int qat_comp_build_ctx(struct adf_accel_dev *accel_dev, void *ctx, enum adf_dc_algo algo)
8{
9 struct icp_qat_fw_comp_req *req_tmpl = ctx;
10 struct icp_qat_fw_comp_cd_hdr *comp_cd_ctrl = &req_tmpl->comp_cd_ctrl;
11 struct icp_qat_fw_comp_req_params *req_pars = &req_tmpl->comp_pars;
12 struct icp_qat_fw_comn_req_hdr *header = &req_tmpl->comn_hdr;
13 int ret;
14
15 memset(req_tmpl, 0, sizeof(*req_tmpl));
16 header->hdr_flags =
17 ICP_QAT_FW_COMN_HDR_FLAGS_BUILD(ICP_QAT_FW_COMN_REQ_FLAG_SET);
18 header->service_type = ICP_QAT_FW_COMN_REQ_CPM_FW_COMP;
19 header->comn_req_flags =
20 ICP_QAT_FW_COMN_FLAGS_BUILD(QAT_COMN_CD_FLD_TYPE_16BYTE_DATA,
21 QAT_COMN_PTR_TYPE_SGL);
22 header->serv_specif_flags =
23 ICP_QAT_FW_COMP_FLAGS_BUILD(ICP_QAT_FW_COMP_STATELESS_SESSION,
24 ICP_QAT_FW_COMP_NOT_AUTO_SELECT_BEST,
25 ICP_QAT_FW_COMP_NOT_ENH_AUTO_SELECT_BEST,
26 ICP_QAT_FW_COMP_NOT_DISABLE_TYPE0_ENH_AUTO_SELECT_BEST,
27 ICP_QAT_FW_COMP_ENABLE_SECURE_RAM_USED_AS_INTMD_BUF);
28
29 /* Build HW config block for compression */
30 ret = GET_DC_OPS(accel_dev)->build_comp_block(ctx, algo);
31 if (ret) {
32 dev_err(&GET_DEV(accel_dev), "Failed to build compression block\n");
33 return ret;
34 }
35
36 req_pars->crc.legacy.initial_adler = COMP_CPR_INITIAL_ADLER;
37 req_pars->crc.legacy.initial_crc32 = COMP_CPR_INITIAL_CRC;
38 req_pars->req_par_flags =
39 ICP_QAT_FW_COMP_REQ_PARAM_FLAGS_BUILD(ICP_QAT_FW_COMP_SOP,
40 ICP_QAT_FW_COMP_EOP,
41 ICP_QAT_FW_COMP_BFINAL,
42 ICP_QAT_FW_COMP_CNV,
43 ICP_QAT_FW_COMP_CNV_RECOVERY,
44 ICP_QAT_FW_COMP_NO_CNV_DFX,
45 ICP_QAT_FW_COMP_CRC_MODE_LEGACY,
46 ICP_QAT_FW_COMP_NO_XXHASH_ACC,
47 ICP_QAT_FW_COMP_CNV_ERROR_NONE,
48 ICP_QAT_FW_COMP_NO_APPEND_CRC,
49 ICP_QAT_FW_COMP_NO_DROP_DATA,
50 ICP_QAT_FW_COMP_NO_PARTIAL_DECOMPRESS);
51 ICP_QAT_FW_COMN_NEXT_ID_SET(comp_cd_ctrl, ICP_QAT_FW_SLICE_DRAM_WR);
52 ICP_QAT_FW_COMN_CURR_ID_SET(comp_cd_ctrl, ICP_QAT_FW_SLICE_COMP);
53
54 /* Fill second half of the template for decompression */
55 memcpy(req_tmpl + 1, req_tmpl, sizeof(*req_tmpl));
56 req_tmpl++;
57
58 /* Build HW config block for decompression */
59 ret = GET_DC_OPS(accel_dev)->build_decomp_block(req_tmpl, algo);
60 if (ret)
61 dev_err(&GET_DEV(accel_dev), "Failed to build decompression block\n");
62
63 return ret;
64}
65

source code of linux/drivers/crypto/intel/qat/qat_common/adf_dc.c