1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
4 */
5
6#include <linux/clk-provider.h>
7#include <linux/module.h>
8#include <linux/mod_devicetable.h>
9#include <linux/of.h>
10#include <linux/platform_device.h>
11#include <linux/regmap.h>
12
13#include <dt-bindings/clock/qcom,qcs615-gcc.h>
14
15#include "clk-alpha-pll.h"
16#include "clk-branch.h"
17#include "clk-rcg.h"
18#include "clk-regmap.h"
19#include "clk-regmap-divider.h"
20#include "clk-regmap-mux.h"
21#include "common.h"
22#include "gdsc.h"
23#include "reset.h"
24
25enum {
26 DT_BI_TCXO,
27 DT_BI_TCXO_AO,
28 DT_SLEEP_CLK,
29};
30
31enum {
32 P_BI_TCXO,
33 P_GPLL0_OUT_AUX2_DIV,
34 P_GPLL0_OUT_MAIN,
35 P_GPLL3_OUT_MAIN,
36 P_GPLL3_OUT_MAIN_DIV,
37 P_GPLL4_OUT_MAIN,
38 P_GPLL6_OUT_MAIN,
39 P_GPLL7_OUT_MAIN,
40 P_GPLL8_OUT_MAIN,
41 P_SLEEP_CLK,
42};
43
44static struct clk_alpha_pll gpll0 = {
45 .offset = 0x0,
46 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
47 .clkr = {
48 .enable_reg = 0x52000,
49 .enable_mask = BIT(0),
50 .hw.init = &(const struct clk_init_data) {
51 .name = "gpll0",
52 .parent_data = &(const struct clk_parent_data) {
53 .index = DT_BI_TCXO,
54 },
55 .num_parents = 1,
56 .ops = &clk_alpha_pll_ops,
57 },
58 },
59};
60
61/* Fixed divider clock of GPLL0 instead of PLL normal postdiv */
62static struct clk_fixed_factor gpll0_out_aux2_div = {
63 .mult = 1,
64 .div = 2,
65 .hw.init = &(struct clk_init_data) {
66 .name = "gpll0_out_aux2_div",
67 .parent_data = &(const struct clk_parent_data) {
68 .hw = &gpll0.clkr.hw,
69 },
70 .num_parents = 1,
71 .ops = &clk_fixed_factor_ops,
72 },
73};
74
75static struct clk_alpha_pll gpll3 = {
76 .offset = 0x3000,
77 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
78 .clkr = {
79 .enable_reg = 0x52000,
80 .enable_mask = BIT(3),
81 .hw.init = &(const struct clk_init_data) {
82 .name = "gpll3",
83 .parent_data = &(const struct clk_parent_data) {
84 .index = DT_BI_TCXO,
85 },
86 .num_parents = 1,
87 .ops = &clk_alpha_pll_ops,
88 },
89 },
90};
91
92/* Fixed divider clock of GPLL3 instead of PLL normal postdiv */
93static struct clk_fixed_factor gpll3_out_aux2_div = {
94 .mult = 1,
95 .div = 2,
96 .hw.init = &(struct clk_init_data) {
97 .name = "gpll3_out_aux2_div",
98 .parent_data = &(const struct clk_parent_data) {
99 .hw = &gpll3.clkr.hw,
100 },
101 .num_parents = 1,
102 .ops = &clk_fixed_factor_ops,
103 },
104};
105
106static struct clk_alpha_pll gpll4 = {
107 .offset = 0x76000,
108 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
109 .clkr = {
110 .enable_reg = 0x52000,
111 .enable_mask = BIT(4),
112 .hw.init = &(const struct clk_init_data) {
113 .name = "gpll4",
114 .parent_data = &(const struct clk_parent_data) {
115 .index = DT_BI_TCXO,
116 },
117 .num_parents = 1,
118 .ops = &clk_alpha_pll_ops,
119 },
120 },
121};
122
123static struct clk_alpha_pll gpll6 = {
124 .offset = 0x13000,
125 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
126 .clkr = {
127 .enable_reg = 0x52000,
128 .enable_mask = BIT(6),
129 .hw.init = &(const struct clk_init_data) {
130 .name = "gpll6",
131 .parent_data = &(const struct clk_parent_data) {
132 .index = DT_BI_TCXO,
133 },
134 .num_parents = 1,
135 .ops = &clk_alpha_pll_ops,
136 },
137 },
138};
139
140static const struct clk_div_table post_div_table_gpll6_out_main[] = {
141 { 0x1, 2 },
142 { }
143};
144
145static struct clk_alpha_pll_postdiv gpll6_out_main = {
146 .offset = 0x13000,
147 .post_div_shift = 8,
148 .post_div_table = post_div_table_gpll6_out_main,
149 .num_post_div = ARRAY_SIZE(post_div_table_gpll6_out_main),
150 .width = 4,
151 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
152 .clkr.hw.init = &(const struct clk_init_data) {
153 .name = "gpll6_out_main",
154 .parent_hws = (const struct clk_hw*[]) {
155 &gpll6.clkr.hw,
156 },
157 .num_parents = 1,
158 .ops = &clk_alpha_pll_postdiv_ops,
159 },
160};
161
162static struct clk_alpha_pll gpll7 = {
163 .offset = 0x1a000,
164 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
165 .clkr = {
166 .enable_reg = 0x52000,
167 .enable_mask = BIT(7),
168 .hw.init = &(const struct clk_init_data) {
169 .name = "gpll7",
170 .parent_data = &(const struct clk_parent_data) {
171 .index = DT_BI_TCXO,
172 },
173 .num_parents = 1,
174 .ops = &clk_alpha_pll_ops,
175 },
176 },
177};
178
179static struct clk_alpha_pll gpll8 = {
180 .offset = 0x1b000,
181 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
182 .clkr = {
183 .enable_reg = 0x52000,
184 .enable_mask = BIT(8),
185 .hw.init = &(const struct clk_init_data) {
186 .name = "gpll8",
187 .parent_data = &(const struct clk_parent_data) {
188 .index = DT_BI_TCXO,
189 },
190 .num_parents = 1,
191 .ops = &clk_alpha_pll_ops,
192 },
193 },
194};
195
196static const struct clk_div_table post_div_table_gpll8_out_main[] = {
197 { 0x1, 2 },
198 { }
199};
200
201static struct clk_alpha_pll_postdiv gpll8_out_main = {
202 .offset = 0x1b000,
203 .post_div_shift = 8,
204 .post_div_table = post_div_table_gpll8_out_main,
205 .num_post_div = ARRAY_SIZE(post_div_table_gpll8_out_main),
206 .width = 4,
207 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
208 .clkr.hw.init = &(const struct clk_init_data) {
209 .name = "gpll8_out_main",
210 .parent_hws = (const struct clk_hw*[]) {
211 &gpll8.clkr.hw,
212 },
213 .num_parents = 1,
214 .ops = &clk_alpha_pll_postdiv_ops,
215 },
216};
217
218static const struct parent_map gcc_parent_map_0[] = {
219 { P_BI_TCXO, 0 },
220 { P_GPLL0_OUT_MAIN, 1 },
221 { P_GPLL0_OUT_AUX2_DIV, 6 },
222};
223
224static const struct clk_parent_data gcc_parent_data_0[] = {
225 { .index = DT_BI_TCXO },
226 { .hw = &gpll0.clkr.hw },
227 { .hw = &gpll0_out_aux2_div.hw },
228};
229
230static const struct clk_parent_data gcc_parent_data_0_ao[] = {
231 { .index = DT_BI_TCXO_AO },
232 { .hw = &gpll0.clkr.hw },
233 { .hw = &gpll0.clkr.hw },
234};
235
236static const struct parent_map gcc_parent_map_1[] = {
237 { P_BI_TCXO, 0 },
238 { P_GPLL0_OUT_MAIN, 1 },
239 { P_GPLL6_OUT_MAIN, 2 },
240 { P_GPLL0_OUT_AUX2_DIV, 6 },
241};
242
243static const struct clk_parent_data gcc_parent_data_1[] = {
244 { .index = DT_BI_TCXO },
245 { .hw = &gpll0.clkr.hw },
246 { .hw = &gpll6_out_main.clkr.hw },
247 { .hw = &gpll0_out_aux2_div.hw },
248};
249
250static const struct parent_map gcc_parent_map_2[] = {
251 { P_BI_TCXO, 0 },
252 { P_GPLL0_OUT_MAIN, 1 },
253 { P_SLEEP_CLK, 5 },
254 { P_GPLL0_OUT_AUX2_DIV, 6 },
255};
256
257static const struct clk_parent_data gcc_parent_data_2[] = {
258 { .index = DT_BI_TCXO },
259 { .hw = &gpll0.clkr.hw },
260 { .index = DT_SLEEP_CLK },
261 { .hw = &gpll0_out_aux2_div.hw },
262};
263
264static const struct parent_map gcc_parent_map_3[] = {
265 { P_BI_TCXO, 0 },
266 { P_SLEEP_CLK, 5 },
267};
268
269static const struct clk_parent_data gcc_parent_data_3[] = {
270 { .index = DT_BI_TCXO },
271 { .index = DT_SLEEP_CLK },
272};
273
274static const struct parent_map gcc_parent_map_4[] = {
275 { P_BI_TCXO, 0 },
276};
277
278static const struct clk_parent_data gcc_parent_data_4[] = {
279 { .index = DT_BI_TCXO },
280};
281
282static const struct parent_map gcc_parent_map_5[] = {
283 { P_BI_TCXO, 0 },
284 { P_GPLL0_OUT_MAIN, 1 },
285 { P_GPLL7_OUT_MAIN, 3 },
286 { P_GPLL4_OUT_MAIN, 5 },
287 { P_GPLL0_OUT_AUX2_DIV, 6 },
288};
289
290static const struct clk_parent_data gcc_parent_data_5[] = {
291 { .index = DT_BI_TCXO },
292 { .hw = &gpll0.clkr.hw },
293 { .hw = &gpll7.clkr.hw },
294 { .hw = &gpll4.clkr.hw },
295 { .hw = &gpll0_out_aux2_div.hw },
296};
297
298static const struct parent_map gcc_parent_map_6[] = {
299 { P_BI_TCXO, 0 },
300 { P_GPLL0_OUT_MAIN, 1 },
301 { P_GPLL7_OUT_MAIN, 3 },
302 { P_GPLL0_OUT_AUX2_DIV, 6 },
303};
304
305static const struct clk_parent_data gcc_parent_data_6[] = {
306 { .index = DT_BI_TCXO },
307 { .hw = &gpll0.clkr.hw },
308 { .hw = &gpll7.clkr.hw },
309 { .hw = &gpll0_out_aux2_div.hw },
310};
311
312static const struct parent_map gcc_parent_map_7[] = {
313 { P_BI_TCXO, 0 },
314 { P_GPLL0_OUT_MAIN, 1 },
315 { P_GPLL3_OUT_MAIN_DIV, 4 },
316 { P_GPLL0_OUT_AUX2_DIV, 6 },
317};
318
319static const struct clk_parent_data gcc_parent_data_7[] = {
320 { .index = DT_BI_TCXO },
321 { .hw = &gpll0.clkr.hw },
322 { .hw = &gpll3_out_aux2_div.hw },
323 { .hw = &gpll0_out_aux2_div.hw },
324};
325
326static const struct parent_map gcc_parent_map_8[] = {
327 { P_BI_TCXO, 0 },
328 { P_GPLL0_OUT_MAIN, 1 },
329 { P_GPLL8_OUT_MAIN, 2 },
330 { P_GPLL4_OUT_MAIN, 5 },
331 { P_GPLL0_OUT_AUX2_DIV, 6 },
332};
333
334static const struct clk_parent_data gcc_parent_data_8[] = {
335 { .index = DT_BI_TCXO },
336 { .hw = &gpll0.clkr.hw },
337 { .hw = &gpll8_out_main.clkr.hw },
338 { .hw = &gpll4.clkr.hw },
339 { .hw = &gpll0_out_aux2_div.hw },
340};
341
342static const struct parent_map gcc_parent_map_9[] = {
343 { P_BI_TCXO, 0 },
344 { P_GPLL0_OUT_MAIN, 1 },
345 { P_GPLL3_OUT_MAIN, 4 },
346};
347
348static const struct clk_parent_data gcc_parent_data_9[] = {
349 { .index = DT_BI_TCXO },
350 { .hw = &gpll0.clkr.hw },
351 { .hw = &gpll3.clkr.hw },
352};
353
354static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
355 F(19200000, P_BI_TCXO, 1, 0, 0),
356 { }
357};
358
359static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
360 .cmd_rcgr = 0x48014,
361 .mnd_width = 0,
362 .hid_width = 5,
363 .parent_map = gcc_parent_map_0,
364 .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
365 .clkr.hw.init = &(const struct clk_init_data) {
366 .name = "gcc_cpuss_ahb_clk_src",
367 .parent_data = gcc_parent_data_0_ao,
368 .num_parents = ARRAY_SIZE(gcc_parent_data_0_ao),
369 .ops = &clk_rcg2_ops,
370 },
371};
372
373static const struct freq_tbl ftbl_gcc_emac_ptp_clk_src[] = {
374 F(19200000, P_BI_TCXO, 1, 0, 0),
375 F(50000000, P_GPLL0_OUT_AUX2_DIV, 6, 0, 0),
376 F(75000000, P_GPLL0_OUT_AUX2_DIV, 4, 0, 0),
377 F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
378 F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0),
379 { }
380};
381
382static struct clk_rcg2 gcc_emac_ptp_clk_src = {
383 .cmd_rcgr = 0x6038,
384 .mnd_width = 0,
385 .hid_width = 5,
386 .parent_map = gcc_parent_map_5,
387 .freq_tbl = ftbl_gcc_emac_ptp_clk_src,
388 .clkr.hw.init = &(const struct clk_init_data) {
389 .name = "gcc_emac_ptp_clk_src",
390 .parent_data = gcc_parent_data_5,
391 .num_parents = ARRAY_SIZE(gcc_parent_data_5),
392 .ops = &clk_rcg2_ops,
393 },
394};
395
396static const struct freq_tbl ftbl_gcc_emac_rgmii_clk_src[] = {
397 F(2500000, P_BI_TCXO, 1, 25, 192),
398 F(5000000, P_BI_TCXO, 1, 25, 96),
399 F(19200000, P_BI_TCXO, 1, 0, 0),
400 F(25000000, P_GPLL0_OUT_AUX2_DIV, 12, 0, 0),
401 F(50000000, P_GPLL0_OUT_AUX2_DIV, 6, 0, 0),
402 F(75000000, P_GPLL0_OUT_AUX2_DIV, 4, 0, 0),
403 F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
404 F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0),
405 { }
406};
407
408static struct clk_rcg2 gcc_emac_rgmii_clk_src = {
409 .cmd_rcgr = 0x601c,
410 .mnd_width = 8,
411 .hid_width = 5,
412 .parent_map = gcc_parent_map_6,
413 .freq_tbl = ftbl_gcc_emac_rgmii_clk_src,
414 .clkr.hw.init = &(const struct clk_init_data) {
415 .name = "gcc_emac_rgmii_clk_src",
416 .parent_data = gcc_parent_data_6,
417 .num_parents = ARRAY_SIZE(gcc_parent_data_6),
418 .ops = &clk_rcg2_ops,
419 },
420};
421
422static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
423 F(25000000, P_GPLL0_OUT_AUX2_DIV, 12, 0, 0),
424 F(50000000, P_GPLL0_OUT_AUX2_DIV, 6, 0, 0),
425 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
426 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
427 { }
428};
429
430static struct clk_rcg2 gcc_gp1_clk_src = {
431 .cmd_rcgr = 0x64004,
432 .mnd_width = 8,
433 .hid_width = 5,
434 .parent_map = gcc_parent_map_2,
435 .freq_tbl = ftbl_gcc_gp1_clk_src,
436 .clkr.hw.init = &(const struct clk_init_data) {
437 .name = "gcc_gp1_clk_src",
438 .parent_data = gcc_parent_data_2,
439 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
440 .ops = &clk_rcg2_ops,
441 },
442};
443
444static struct clk_rcg2 gcc_gp2_clk_src = {
445 .cmd_rcgr = 0x65004,
446 .mnd_width = 8,
447 .hid_width = 5,
448 .parent_map = gcc_parent_map_2,
449 .freq_tbl = ftbl_gcc_gp1_clk_src,
450 .clkr.hw.init = &(const struct clk_init_data) {
451 .name = "gcc_gp2_clk_src",
452 .parent_data = gcc_parent_data_2,
453 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
454 .ops = &clk_rcg2_ops,
455 },
456};
457
458static struct clk_rcg2 gcc_gp3_clk_src = {
459 .cmd_rcgr = 0x66004,
460 .mnd_width = 8,
461 .hid_width = 5,
462 .parent_map = gcc_parent_map_2,
463 .freq_tbl = ftbl_gcc_gp1_clk_src,
464 .clkr.hw.init = &(const struct clk_init_data) {
465 .name = "gcc_gp3_clk_src",
466 .parent_data = gcc_parent_data_2,
467 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
468 .ops = &clk_rcg2_ops,
469 },
470};
471
472static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
473 F(9600000, P_BI_TCXO, 2, 0, 0),
474 F(19200000, P_BI_TCXO, 1, 0, 0),
475 { }
476};
477
478static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
479 .cmd_rcgr = 0x6b02c,
480 .mnd_width = 16,
481 .hid_width = 5,
482 .parent_map = gcc_parent_map_3,
483 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
484 .clkr.hw.init = &(const struct clk_init_data) {
485 .name = "gcc_pcie_0_aux_clk_src",
486 .parent_data = gcc_parent_data_3,
487 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
488 .ops = &clk_rcg2_shared_ops,
489 },
490};
491
492static const struct freq_tbl ftbl_gcc_pcie_phy_refgen_clk_src[] = {
493 F(19200000, P_BI_TCXO, 1, 0, 0),
494 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
495 { }
496};
497
498static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = {
499 .cmd_rcgr = 0x6f014,
500 .mnd_width = 0,
501 .hid_width = 5,
502 .parent_map = gcc_parent_map_0,
503 .freq_tbl = ftbl_gcc_pcie_phy_refgen_clk_src,
504 .clkr.hw.init = &(const struct clk_init_data) {
505 .name = "gcc_pcie_phy_refgen_clk_src",
506 .parent_data = gcc_parent_data_0,
507 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
508 .ops = &clk_rcg2_ops,
509 },
510};
511
512static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
513 F(19200000, P_BI_TCXO, 1, 0, 0),
514 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
515 { }
516};
517
518static struct clk_rcg2 gcc_pdm2_clk_src = {
519 .cmd_rcgr = 0x33010,
520 .mnd_width = 0,
521 .hid_width = 5,
522 .parent_map = gcc_parent_map_0,
523 .freq_tbl = ftbl_gcc_pdm2_clk_src,
524 .clkr.hw.init = &(const struct clk_init_data) {
525 .name = "gcc_pdm2_clk_src",
526 .parent_data = gcc_parent_data_0,
527 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
528 .ops = &clk_rcg2_ops,
529 },
530};
531
532static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = {
533 F(60000000, P_GPLL0_OUT_AUX2_DIV, 5, 0, 0),
534 F(133250000, P_GPLL3_OUT_MAIN_DIV, 4, 0, 0),
535 F(266500000, P_GPLL3_OUT_MAIN_DIV, 2, 0, 0),
536 { }
537};
538
539static struct clk_rcg2 gcc_qspi_core_clk_src = {
540 .cmd_rcgr = 0x4b008,
541 .mnd_width = 0,
542 .hid_width = 5,
543 .parent_map = gcc_parent_map_7,
544 .freq_tbl = ftbl_gcc_qspi_core_clk_src,
545 .clkr.hw.init = &(const struct clk_init_data) {
546 .name = "gcc_qspi_core_clk_src",
547 .parent_data = gcc_parent_data_7,
548 .num_parents = ARRAY_SIZE(gcc_parent_data_7),
549 .ops = &clk_rcg2_ops,
550 },
551};
552
553static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
554 F(7372800, P_GPLL0_OUT_AUX2_DIV, 1, 384, 15625),
555 F(14745600, P_GPLL0_OUT_AUX2_DIV, 1, 768, 15625),
556 F(19200000, P_BI_TCXO, 1, 0, 0),
557 F(29491200, P_GPLL0_OUT_AUX2_DIV, 1, 1536, 15625),
558 F(32000000, P_GPLL0_OUT_AUX2_DIV, 1, 8, 75),
559 F(48000000, P_GPLL0_OUT_AUX2_DIV, 1, 4, 25),
560 F(64000000, P_GPLL0_OUT_AUX2_DIV, 1, 16, 75),
561 F(75000000, P_GPLL0_OUT_AUX2_DIV, 4, 0, 0),
562 F(80000000, P_GPLL0_OUT_AUX2_DIV, 1, 4, 15),
563 F(96000000, P_GPLL0_OUT_AUX2_DIV, 1, 8, 25),
564 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
565 F(102400000, P_GPLL0_OUT_AUX2_DIV, 1, 128, 375),
566 F(112000000, P_GPLL0_OUT_AUX2_DIV, 1, 28, 75),
567 F(117964800, P_GPLL0_OUT_AUX2_DIV, 1, 6144, 15625),
568 F(120000000, P_GPLL0_OUT_AUX2_DIV, 2.5, 0, 0),
569 F(128000000, P_GPLL6_OUT_MAIN, 3, 0, 0),
570 { }
571};
572
573static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
574 .name = "gcc_qupv3_wrap0_s0_clk_src",
575 .parent_data = gcc_parent_data_1,
576 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
577 .ops = &clk_rcg2_ops,
578};
579
580static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
581 .cmd_rcgr = 0x17148,
582 .mnd_width = 16,
583 .hid_width = 5,
584 .parent_map = gcc_parent_map_1,
585 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
586 .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
587};
588
589static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
590 .name = "gcc_qupv3_wrap0_s1_clk_src",
591 .parent_data = gcc_parent_data_1,
592 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
593 .ops = &clk_rcg2_ops,
594};
595
596static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
597 .cmd_rcgr = 0x17278,
598 .mnd_width = 16,
599 .hid_width = 5,
600 .parent_map = gcc_parent_map_1,
601 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
602 .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
603};
604
605static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
606 .name = "gcc_qupv3_wrap0_s2_clk_src",
607 .parent_data = gcc_parent_data_1,
608 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
609 .ops = &clk_rcg2_ops,
610};
611
612static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
613 .cmd_rcgr = 0x173a8,
614 .mnd_width = 16,
615 .hid_width = 5,
616 .parent_map = gcc_parent_map_1,
617 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
618 .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
619};
620
621static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
622 .name = "gcc_qupv3_wrap0_s3_clk_src",
623 .parent_data = gcc_parent_data_1,
624 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
625 .ops = &clk_rcg2_ops,
626};
627
628static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
629 .cmd_rcgr = 0x174d8,
630 .mnd_width = 16,
631 .hid_width = 5,
632 .parent_map = gcc_parent_map_1,
633 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
634 .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
635};
636
637static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
638 .name = "gcc_qupv3_wrap0_s4_clk_src",
639 .parent_data = gcc_parent_data_1,
640 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
641 .ops = &clk_rcg2_ops,
642};
643
644static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
645 .cmd_rcgr = 0x17608,
646 .mnd_width = 16,
647 .hid_width = 5,
648 .parent_map = gcc_parent_map_1,
649 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
650 .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
651};
652
653static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
654 .name = "gcc_qupv3_wrap0_s5_clk_src",
655 .parent_data = gcc_parent_data_1,
656 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
657 .ops = &clk_rcg2_ops,
658};
659
660static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
661 .cmd_rcgr = 0x17738,
662 .mnd_width = 16,
663 .hid_width = 5,
664 .parent_map = gcc_parent_map_1,
665 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
666 .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
667};
668
669static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
670 .name = "gcc_qupv3_wrap1_s0_clk_src",
671 .parent_data = gcc_parent_data_1,
672 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
673 .ops = &clk_rcg2_ops,
674};
675
676static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
677 .cmd_rcgr = 0x18148,
678 .mnd_width = 16,
679 .hid_width = 5,
680 .parent_map = gcc_parent_map_1,
681 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
682 .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
683};
684
685static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
686 .name = "gcc_qupv3_wrap1_s1_clk_src",
687 .parent_data = gcc_parent_data_1,
688 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
689 .ops = &clk_rcg2_ops,
690};
691
692static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
693 .cmd_rcgr = 0x18278,
694 .mnd_width = 16,
695 .hid_width = 5,
696 .parent_map = gcc_parent_map_1,
697 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
698 .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
699};
700
701static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
702 .name = "gcc_qupv3_wrap1_s2_clk_src",
703 .parent_data = gcc_parent_data_1,
704 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
705 .ops = &clk_rcg2_ops,
706};
707
708static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
709 .cmd_rcgr = 0x183a8,
710 .mnd_width = 16,
711 .hid_width = 5,
712 .parent_map = gcc_parent_map_1,
713 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
714 .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
715};
716
717static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
718 .name = "gcc_qupv3_wrap1_s3_clk_src",
719 .parent_data = gcc_parent_data_1,
720 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
721 .ops = &clk_rcg2_ops,
722};
723
724static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
725 .cmd_rcgr = 0x184d8,
726 .mnd_width = 16,
727 .hid_width = 5,
728 .parent_map = gcc_parent_map_1,
729 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
730 .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
731};
732
733static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
734 .name = "gcc_qupv3_wrap1_s4_clk_src",
735 .parent_data = gcc_parent_data_1,
736 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
737 .ops = &clk_rcg2_ops,
738};
739
740static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
741 .cmd_rcgr = 0x18608,
742 .mnd_width = 16,
743 .hid_width = 5,
744 .parent_map = gcc_parent_map_1,
745 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
746 .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
747};
748
749static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
750 .name = "gcc_qupv3_wrap1_s5_clk_src",
751 .parent_data = gcc_parent_data_1,
752 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
753 .ops = &clk_rcg2_ops,
754};
755
756static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
757 .cmd_rcgr = 0x18738,
758 .mnd_width = 16,
759 .hid_width = 5,
760 .parent_map = gcc_parent_map_1,
761 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
762 .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
763};
764
765static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
766 F(144000, P_BI_TCXO, 16, 3, 25),
767 F(400000, P_BI_TCXO, 12, 1, 4),
768 F(20000000, P_GPLL0_OUT_AUX2_DIV, 5, 1, 3),
769 F(25000000, P_GPLL0_OUT_AUX2_DIV, 6, 1, 2),
770 F(50000000, P_GPLL0_OUT_AUX2_DIV, 6, 0, 0),
771 F(100000000, P_GPLL0_OUT_AUX2_DIV, 3, 0, 0),
772 F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
773 F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0),
774 { }
775};
776
777static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
778 .cmd_rcgr = 0x12028,
779 .mnd_width = 8,
780 .hid_width = 5,
781 .parent_map = gcc_parent_map_1,
782 .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
783 .clkr.hw.init = &(const struct clk_init_data) {
784 .name = "gcc_sdcc1_apps_clk_src",
785 .parent_data = gcc_parent_data_1,
786 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
787 .ops = &clk_rcg2_shared_floor_ops,
788 },
789};
790
791static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = {
792 F(75000000, P_GPLL0_OUT_AUX2_DIV, 4, 0, 0),
793 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
794 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
795 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
796 { }
797};
798
799static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
800 .cmd_rcgr = 0x12010,
801 .mnd_width = 0,
802 .hid_width = 5,
803 .parent_map = gcc_parent_map_0,
804 .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src,
805 .clkr.hw.init = &(const struct clk_init_data) {
806 .name = "gcc_sdcc1_ice_core_clk_src",
807 .parent_data = gcc_parent_data_0,
808 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
809 .ops = &clk_rcg2_shared_floor_ops,
810 },
811};
812
813static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
814 F(400000, P_BI_TCXO, 12, 1, 4),
815 F(19200000, P_BI_TCXO, 1, 0, 0),
816 F(25000000, P_GPLL0_OUT_AUX2_DIV, 12, 0, 0),
817 F(50000000, P_GPLL0_OUT_AUX2_DIV, 6, 0, 0),
818 F(100000000, P_GPLL0_OUT_AUX2_DIV, 3, 0, 0),
819 F(202000000, P_GPLL8_OUT_MAIN, 2, 0, 0),
820 { }
821};
822
823static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
824 .cmd_rcgr = 0x1400c,
825 .mnd_width = 8,
826 .hid_width = 5,
827 .parent_map = gcc_parent_map_8,
828 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
829 .clkr.hw.init = &(const struct clk_init_data) {
830 .name = "gcc_sdcc2_apps_clk_src",
831 .parent_data = gcc_parent_data_8,
832 .num_parents = ARRAY_SIZE(gcc_parent_data_8),
833 .ops = &clk_rcg2_shared_floor_ops,
834 },
835};
836
837static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
838 F(25000000, P_GPLL0_OUT_AUX2_DIV, 12, 0, 0),
839 F(50000000, P_GPLL0_OUT_AUX2_DIV, 6, 0, 0),
840 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
841 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
842 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
843 { }
844};
845
846static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
847 .cmd_rcgr = 0x77020,
848 .mnd_width = 8,
849 .hid_width = 5,
850 .parent_map = gcc_parent_map_0,
851 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
852 .clkr.hw.init = &(const struct clk_init_data) {
853 .name = "gcc_ufs_phy_axi_clk_src",
854 .parent_data = gcc_parent_data_0,
855 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
856 .ops = &clk_rcg2_ops,
857 },
858};
859
860static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
861 F(37500000, P_GPLL0_OUT_AUX2_DIV, 8, 0, 0),
862 F(75000000, P_GPLL0_OUT_AUX2_DIV, 4, 0, 0),
863 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
864 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
865 { }
866};
867
868static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
869 .cmd_rcgr = 0x77048,
870 .mnd_width = 0,
871 .hid_width = 5,
872 .parent_map = gcc_parent_map_0,
873 .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
874 .clkr.hw.init = &(const struct clk_init_data) {
875 .name = "gcc_ufs_phy_ice_core_clk_src",
876 .parent_data = gcc_parent_data_0,
877 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
878 .ops = &clk_rcg2_ops,
879 },
880};
881
882static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
883 .cmd_rcgr = 0x7707c,
884 .mnd_width = 0,
885 .hid_width = 5,
886 .parent_map = gcc_parent_map_4,
887 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
888 .clkr.hw.init = &(const struct clk_init_data) {
889 .name = "gcc_ufs_phy_phy_aux_clk_src",
890 .parent_data = gcc_parent_data_4,
891 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
892 .ops = &clk_rcg2_ops,
893 },
894};
895
896static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = {
897 F(37500000, P_GPLL0_OUT_AUX2_DIV, 8, 0, 0),
898 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
899 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
900 { }
901};
902
903static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
904 .cmd_rcgr = 0x77060,
905 .mnd_width = 0,
906 .hid_width = 5,
907 .parent_map = gcc_parent_map_0,
908 .freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src,
909 .clkr.hw.init = &(const struct clk_init_data) {
910 .name = "gcc_ufs_phy_unipro_core_clk_src",
911 .parent_data = gcc_parent_data_0,
912 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
913 .ops = &clk_rcg2_ops,
914 },
915};
916
917static const struct freq_tbl ftbl_gcc_usb20_sec_master_clk_src[] = {
918 F(19200000, P_BI_TCXO, 1, 0, 0),
919 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
920 F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
921 { }
922};
923
924static struct clk_rcg2 gcc_usb20_sec_master_clk_src = {
925 .cmd_rcgr = 0xa601c,
926 .mnd_width = 8,
927 .hid_width = 5,
928 .parent_map = gcc_parent_map_0,
929 .freq_tbl = ftbl_gcc_usb20_sec_master_clk_src,
930 .clkr.hw.init = &(const struct clk_init_data) {
931 .name = "gcc_usb20_sec_master_clk_src",
932 .parent_data = gcc_parent_data_0,
933 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
934 .ops = &clk_rcg2_ops,
935 },
936};
937
938static struct clk_rcg2 gcc_usb20_sec_mock_utmi_clk_src = {
939 .cmd_rcgr = 0xa6034,
940 .mnd_width = 0,
941 .hid_width = 5,
942 .parent_map = gcc_parent_map_0,
943 .freq_tbl = ftbl_gcc_pdm2_clk_src,
944 .clkr.hw.init = &(const struct clk_init_data) {
945 .name = "gcc_usb20_sec_mock_utmi_clk_src",
946 .parent_data = gcc_parent_data_0,
947 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
948 .ops = &clk_rcg2_ops,
949 },
950};
951
952static const struct freq_tbl ftbl_gcc_usb2_sec_phy_aux_clk_src[] = {
953 F(19200000, P_BI_TCXO, 1, 0, 0),
954 { }
955};
956
957static struct clk_rcg2 gcc_usb2_sec_phy_aux_clk_src = {
958 .cmd_rcgr = 0xa6060,
959 .mnd_width = 0,
960 .hid_width = 5,
961 .parent_map = gcc_parent_map_3,
962 .freq_tbl = ftbl_gcc_usb2_sec_phy_aux_clk_src,
963 .clkr.hw.init = &(const struct clk_init_data) {
964 .name = "gcc_usb2_sec_phy_aux_clk_src",
965 .parent_data = gcc_parent_data_3,
966 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
967 .ops = &clk_rcg2_ops,
968 },
969};
970
971static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
972 F(66666667, P_GPLL0_OUT_AUX2_DIV, 4.5, 0, 0),
973 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
974 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
975 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
976 { }
977};
978
979static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
980 .cmd_rcgr = 0xf01c,
981 .mnd_width = 8,
982 .hid_width = 5,
983 .parent_map = gcc_parent_map_0,
984 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
985 .clkr.hw.init = &(const struct clk_init_data) {
986 .name = "gcc_usb30_prim_master_clk_src",
987 .parent_data = gcc_parent_data_0,
988 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
989 .ops = &clk_rcg2_ops,
990 },
991};
992
993static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = {
994 F(19200000, P_BI_TCXO, 1, 0, 0),
995 F(20000000, P_GPLL0_OUT_AUX2_DIV, 15, 0, 0),
996 F(40000000, P_GPLL0_OUT_AUX2_DIV, 7.5, 0, 0),
997 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
998 { }
999};
1000
1001static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
1002 .cmd_rcgr = 0xf034,
1003 .mnd_width = 0,
1004 .hid_width = 5,
1005 .parent_map = gcc_parent_map_0,
1006 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
1007 .clkr.hw.init = &(const struct clk_init_data) {
1008 .name = "gcc_usb30_prim_mock_utmi_clk_src",
1009 .parent_data = gcc_parent_data_0,
1010 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1011 .ops = &clk_rcg2_ops,
1012 },
1013};
1014
1015static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
1016 .cmd_rcgr = 0xf060,
1017 .mnd_width = 0,
1018 .hid_width = 5,
1019 .parent_map = gcc_parent_map_3,
1020 .freq_tbl = ftbl_gcc_usb2_sec_phy_aux_clk_src,
1021 .clkr.hw.init = &(const struct clk_init_data) {
1022 .name = "gcc_usb3_prim_phy_aux_clk_src",
1023 .parent_data = gcc_parent_data_3,
1024 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
1025 .ops = &clk_rcg2_ops,
1026 },
1027};
1028
1029static const struct freq_tbl ftbl_gcc_vsensor_clk_src[] = {
1030 F(19200000, P_BI_TCXO, 1, 0, 0),
1031 F(400000000, P_GPLL0_OUT_MAIN, 1.5, 0, 0),
1032 { }
1033};
1034
1035static struct clk_rcg2 gcc_vsensor_clk_src = {
1036 .cmd_rcgr = 0x7a018,
1037 .mnd_width = 0,
1038 .hid_width = 5,
1039 .parent_map = gcc_parent_map_9,
1040 .freq_tbl = ftbl_gcc_vsensor_clk_src,
1041 .clkr.hw.init = &(const struct clk_init_data) {
1042 .name = "gcc_vsensor_clk_src",
1043 .parent_data = gcc_parent_data_9,
1044 .num_parents = ARRAY_SIZE(gcc_parent_data_9),
1045 .ops = &clk_rcg2_ops,
1046 },
1047};
1048
1049static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
1050 .halt_reg = 0x770c0,
1051 .halt_check = BRANCH_HALT_VOTED,
1052 .hwcg_reg = 0x770c0,
1053 .hwcg_bit = 1,
1054 .clkr = {
1055 .enable_reg = 0x770c0,
1056 .enable_mask = BIT(0),
1057 .hw.init = &(const struct clk_init_data) {
1058 .name = "gcc_aggre_ufs_phy_axi_clk",
1059 .parent_hws = (const struct clk_hw*[]) {
1060 &gcc_ufs_phy_axi_clk_src.clkr.hw,
1061 },
1062 .num_parents = 1,
1063 .flags = CLK_SET_RATE_PARENT,
1064 .ops = &clk_branch2_ops,
1065 },
1066 },
1067};
1068
1069static struct clk_branch gcc_aggre_usb2_sec_axi_clk = {
1070 .halt_reg = 0xa6084,
1071 .halt_check = BRANCH_HALT_VOTED,
1072 .clkr = {
1073 .enable_reg = 0xa6084,
1074 .enable_mask = BIT(0),
1075 .hw.init = &(const struct clk_init_data) {
1076 .name = "gcc_aggre_usb2_sec_axi_clk",
1077 .parent_hws = (const struct clk_hw*[]) {
1078 &gcc_usb20_sec_master_clk_src.clkr.hw,
1079 },
1080 .num_parents = 1,
1081 .flags = CLK_SET_RATE_PARENT,
1082 .ops = &clk_branch2_ops,
1083 },
1084 },
1085};
1086
1087static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
1088 .halt_reg = 0xf07c,
1089 .halt_check = BRANCH_HALT_VOTED,
1090 .clkr = {
1091 .enable_reg = 0xf07c,
1092 .enable_mask = BIT(0),
1093 .hw.init = &(const struct clk_init_data) {
1094 .name = "gcc_aggre_usb3_prim_axi_clk",
1095 .parent_hws = (const struct clk_hw*[]) {
1096 &gcc_usb30_prim_master_clk_src.clkr.hw,
1097 },
1098 .num_parents = 1,
1099 .flags = CLK_SET_RATE_PARENT,
1100 .ops = &clk_branch2_ops,
1101 },
1102 },
1103};
1104
1105static struct clk_branch gcc_ahb2phy_east_clk = {
1106 .halt_reg = 0x6a008,
1107 .halt_check = BRANCH_HALT_VOTED,
1108 .hwcg_reg = 0x6a008,
1109 .hwcg_bit = 1,
1110 .clkr = {
1111 .enable_reg = 0x6a008,
1112 .enable_mask = BIT(0),
1113 .hw.init = &(const struct clk_init_data) {
1114 .name = "gcc_ahb2phy_east_clk",
1115 .ops = &clk_branch2_ops,
1116 },
1117 },
1118};
1119
1120static struct clk_branch gcc_ahb2phy_west_clk = {
1121 .halt_reg = 0x6a004,
1122 .halt_check = BRANCH_HALT_VOTED,
1123 .hwcg_reg = 0x6a004,
1124 .hwcg_bit = 1,
1125 .clkr = {
1126 .enable_reg = 0x6a004,
1127 .enable_mask = BIT(0),
1128 .hw.init = &(const struct clk_init_data) {
1129 .name = "gcc_ahb2phy_west_clk",
1130 .ops = &clk_branch2_ops,
1131 },
1132 },
1133};
1134
1135static struct clk_branch gcc_boot_rom_ahb_clk = {
1136 .halt_reg = 0x38004,
1137 .halt_check = BRANCH_HALT_VOTED,
1138 .hwcg_reg = 0x38004,
1139 .hwcg_bit = 1,
1140 .clkr = {
1141 .enable_reg = 0x52004,
1142 .enable_mask = BIT(10),
1143 .hw.init = &(const struct clk_init_data) {
1144 .name = "gcc_boot_rom_ahb_clk",
1145 .ops = &clk_branch2_ops,
1146 },
1147 },
1148};
1149
1150static struct clk_branch gcc_camera_hf_axi_clk = {
1151 .halt_reg = 0xb030,
1152 .halt_check = BRANCH_HALT_VOTED,
1153 .clkr = {
1154 .enable_reg = 0xb030,
1155 .enable_mask = BIT(0),
1156 .hw.init = &(const struct clk_init_data) {
1157 .name = "gcc_camera_hf_axi_clk",
1158 .ops = &clk_branch2_ops,
1159 },
1160 },
1161};
1162
1163static struct clk_branch gcc_ce1_ahb_clk = {
1164 .halt_reg = 0x4100c,
1165 .halt_check = BRANCH_HALT_VOTED,
1166 .hwcg_reg = 0x4100c,
1167 .hwcg_bit = 1,
1168 .clkr = {
1169 .enable_reg = 0x52004,
1170 .enable_mask = BIT(3),
1171 .hw.init = &(const struct clk_init_data) {
1172 .name = "gcc_ce1_ahb_clk",
1173 .ops = &clk_branch2_ops,
1174 },
1175 },
1176};
1177
1178static struct clk_branch gcc_ce1_axi_clk = {
1179 .halt_reg = 0x41008,
1180 .halt_check = BRANCH_HALT_VOTED,
1181 .clkr = {
1182 .enable_reg = 0x52004,
1183 .enable_mask = BIT(4),
1184 .hw.init = &(const struct clk_init_data) {
1185 .name = "gcc_ce1_axi_clk",
1186 .ops = &clk_branch2_ops,
1187 },
1188 },
1189};
1190
1191static struct clk_branch gcc_ce1_clk = {
1192 .halt_reg = 0x41004,
1193 .halt_check = BRANCH_HALT_VOTED,
1194 .clkr = {
1195 .enable_reg = 0x52004,
1196 .enable_mask = BIT(5),
1197 .hw.init = &(const struct clk_init_data) {
1198 .name = "gcc_ce1_clk",
1199 .ops = &clk_branch2_ops,
1200 },
1201 },
1202};
1203
1204static struct clk_branch gcc_cfg_noc_usb2_sec_axi_clk = {
1205 .halt_reg = 0xa609c,
1206 .halt_check = BRANCH_HALT_VOTED,
1207 .clkr = {
1208 .enable_reg = 0xa609c,
1209 .enable_mask = BIT(0),
1210 .hw.init = &(const struct clk_init_data) {
1211 .name = "gcc_cfg_noc_usb2_sec_axi_clk",
1212 .parent_hws = (const struct clk_hw*[]) {
1213 &gcc_usb20_sec_master_clk_src.clkr.hw,
1214 },
1215 .num_parents = 1,
1216 .flags = CLK_SET_RATE_PARENT,
1217 .ops = &clk_branch2_ops,
1218 },
1219 },
1220};
1221
1222static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
1223 .halt_reg = 0xf078,
1224 .halt_check = BRANCH_HALT_VOTED,
1225 .clkr = {
1226 .enable_reg = 0xf078,
1227 .enable_mask = BIT(0),
1228 .hw.init = &(const struct clk_init_data) {
1229 .name = "gcc_cfg_noc_usb3_prim_axi_clk",
1230 .parent_hws = (const struct clk_hw*[]) {
1231 &gcc_usb30_prim_master_clk_src.clkr.hw,
1232 },
1233 .num_parents = 1,
1234 .flags = CLK_SET_RATE_PARENT,
1235 .ops = &clk_branch2_ops,
1236 },
1237 },
1238};
1239
1240static struct clk_branch gcc_cpuss_ahb_clk = {
1241 .halt_reg = 0x48000,
1242 .halt_check = BRANCH_HALT_VOTED,
1243 .clkr = {
1244 .enable_reg = 0x52004,
1245 .enable_mask = BIT(21),
1246 .hw.init = &(const struct clk_init_data) {
1247 .name = "gcc_cpuss_ahb_clk",
1248 .parent_hws = (const struct clk_hw*[]) {
1249 &gcc_cpuss_ahb_clk_src.clkr.hw,
1250 },
1251 .num_parents = 1,
1252 .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
1253 .ops = &clk_branch2_ops,
1254 },
1255 },
1256};
1257
1258static struct clk_branch gcc_ddrss_gpu_axi_clk = {
1259 .halt_reg = 0x71154,
1260 .halt_check = BRANCH_HALT_VOTED,
1261 .clkr = {
1262 .enable_reg = 0x71154,
1263 .enable_mask = BIT(0),
1264 .hw.init = &(const struct clk_init_data) {
1265 .name = "gcc_ddrss_gpu_axi_clk",
1266 .ops = &clk_branch2_ops,
1267 },
1268 },
1269};
1270
1271static struct clk_branch gcc_disp_gpll0_div_clk_src = {
1272 .halt_check = BRANCH_HALT_DELAY,
1273 .clkr = {
1274 .enable_reg = 0x52004,
1275 .enable_mask = BIT(20),
1276 .hw.init = &(const struct clk_init_data) {
1277 .name = "gcc_disp_gpll0_div_clk_src",
1278 .parent_hws = (const struct clk_hw*[]) {
1279 &gpll0_out_aux2_div.hw,
1280 },
1281 .num_parents = 1,
1282 .ops = &clk_branch2_ops,
1283 },
1284 },
1285};
1286
1287static struct clk_branch gcc_disp_hf_axi_clk = {
1288 .halt_reg = 0xb038,
1289 .halt_check = BRANCH_HALT_VOTED,
1290 .clkr = {
1291 .enable_reg = 0xb038,
1292 .enable_mask = BIT(0),
1293 .hw.init = &(const struct clk_init_data) {
1294 .name = "gcc_disp_hf_axi_clk",
1295 .ops = &clk_branch2_ops,
1296 },
1297 },
1298};
1299
1300static struct clk_branch gcc_emac_axi_clk = {
1301 .halt_reg = 0x6010,
1302 .halt_check = BRANCH_HALT,
1303 .clkr = {
1304 .enable_reg = 0x6010,
1305 .enable_mask = BIT(0),
1306 .hw.init = &(const struct clk_init_data) {
1307 .name = "gcc_emac_axi_clk",
1308 .ops = &clk_branch2_ops,
1309 },
1310 },
1311};
1312
1313static struct clk_branch gcc_emac_ptp_clk = {
1314 .halt_reg = 0x6034,
1315 .halt_check = BRANCH_HALT,
1316 .clkr = {
1317 .enable_reg = 0x6034,
1318 .enable_mask = BIT(0),
1319 .hw.init = &(const struct clk_init_data) {
1320 .name = "gcc_emac_ptp_clk",
1321 .parent_hws = (const struct clk_hw*[]) {
1322 &gcc_emac_ptp_clk_src.clkr.hw,
1323 },
1324 .num_parents = 1,
1325 .flags = CLK_SET_RATE_PARENT,
1326 .ops = &clk_branch2_ops,
1327 },
1328 },
1329};
1330
1331static struct clk_branch gcc_emac_rgmii_clk = {
1332 .halt_reg = 0x6018,
1333 .halt_check = BRANCH_HALT,
1334 .clkr = {
1335 .enable_reg = 0x6018,
1336 .enable_mask = BIT(0),
1337 .hw.init = &(const struct clk_init_data) {
1338 .name = "gcc_emac_rgmii_clk",
1339 .parent_hws = (const struct clk_hw*[]) {
1340 &gcc_emac_rgmii_clk_src.clkr.hw,
1341 },
1342 .num_parents = 1,
1343 .flags = CLK_SET_RATE_PARENT,
1344 .ops = &clk_branch2_ops,
1345 },
1346 },
1347};
1348
1349static struct clk_branch gcc_emac_slv_ahb_clk = {
1350 .halt_reg = 0x6014,
1351 .halt_check = BRANCH_HALT,
1352 .hwcg_reg = 0x6014,
1353 .hwcg_bit = 1,
1354 .clkr = {
1355 .enable_reg = 0x6014,
1356 .enable_mask = BIT(0),
1357 .hw.init = &(const struct clk_init_data) {
1358 .name = "gcc_emac_slv_ahb_clk",
1359 .ops = &clk_branch2_ops,
1360 },
1361 },
1362};
1363
1364static struct clk_branch gcc_gp1_clk = {
1365 .halt_reg = 0x64000,
1366 .halt_check = BRANCH_HALT,
1367 .clkr = {
1368 .enable_reg = 0x64000,
1369 .enable_mask = BIT(0),
1370 .hw.init = &(const struct clk_init_data) {
1371 .name = "gcc_gp1_clk",
1372 .parent_hws = (const struct clk_hw*[]) {
1373 &gcc_gp1_clk_src.clkr.hw,
1374 },
1375 .num_parents = 1,
1376 .flags = CLK_SET_RATE_PARENT,
1377 .ops = &clk_branch2_ops,
1378 },
1379 },
1380};
1381
1382static struct clk_branch gcc_gp2_clk = {
1383 .halt_reg = 0x65000,
1384 .halt_check = BRANCH_HALT,
1385 .clkr = {
1386 .enable_reg = 0x65000,
1387 .enable_mask = BIT(0),
1388 .hw.init = &(const struct clk_init_data) {
1389 .name = "gcc_gp2_clk",
1390 .parent_hws = (const struct clk_hw*[]) {
1391 &gcc_gp2_clk_src.clkr.hw,
1392 },
1393 .num_parents = 1,
1394 .flags = CLK_SET_RATE_PARENT,
1395 .ops = &clk_branch2_ops,
1396 },
1397 },
1398};
1399
1400static struct clk_branch gcc_gp3_clk = {
1401 .halt_reg = 0x66000,
1402 .halt_check = BRANCH_HALT,
1403 .clkr = {
1404 .enable_reg = 0x66000,
1405 .enable_mask = BIT(0),
1406 .hw.init = &(const struct clk_init_data) {
1407 .name = "gcc_gp3_clk",
1408 .parent_hws = (const struct clk_hw*[]) {
1409 &gcc_gp3_clk_src.clkr.hw,
1410 },
1411 .num_parents = 1,
1412 .flags = CLK_SET_RATE_PARENT,
1413 .ops = &clk_branch2_ops,
1414 },
1415 },
1416};
1417
1418static struct clk_branch gcc_gpu_gpll0_clk_src = {
1419 .halt_check = BRANCH_HALT_DELAY,
1420 .clkr = {
1421 .enable_reg = 0x52004,
1422 .enable_mask = BIT(15),
1423 .hw.init = &(const struct clk_init_data) {
1424 .name = "gcc_gpu_gpll0_clk_src",
1425 .parent_hws = (const struct clk_hw*[]) {
1426 &gpll0.clkr.hw,
1427 },
1428 .num_parents = 1,
1429 .ops = &clk_branch2_ops,
1430 },
1431 },
1432};
1433
1434static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
1435 .halt_check = BRANCH_HALT_DELAY,
1436 .clkr = {
1437 .enable_reg = 0x52004,
1438 .enable_mask = BIT(16),
1439 .hw.init = &(const struct clk_init_data) {
1440 .name = "gcc_gpu_gpll0_div_clk_src",
1441 .parent_hws = (const struct clk_hw*[]) {
1442 &gpll0_out_aux2_div.hw,
1443 },
1444 .num_parents = 1,
1445 .ops = &clk_branch2_ops,
1446 },
1447 },
1448};
1449
1450static struct clk_branch gcc_gpu_iref_clk = {
1451 .halt_reg = 0x8c010,
1452 .halt_check = BRANCH_HALT,
1453 .clkr = {
1454 .enable_reg = 0x8c010,
1455 .enable_mask = BIT(0),
1456 .hw.init = &(const struct clk_init_data) {
1457 .name = "gcc_gpu_iref_clk",
1458 .ops = &clk_branch2_ops,
1459 },
1460 },
1461};
1462
1463static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
1464 .halt_reg = 0x7100c,
1465 .halt_check = BRANCH_HALT_VOTED,
1466 .clkr = {
1467 .enable_reg = 0x7100c,
1468 .enable_mask = BIT(0),
1469 .hw.init = &(const struct clk_init_data) {
1470 .name = "gcc_gpu_memnoc_gfx_clk",
1471 .ops = &clk_branch2_ops,
1472 },
1473 },
1474};
1475
1476static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
1477 .halt_reg = 0x71018,
1478 .halt_check = BRANCH_HALT,
1479 .clkr = {
1480 .enable_reg = 0x71018,
1481 .enable_mask = BIT(0),
1482 .hw.init = &(const struct clk_init_data) {
1483 .name = "gcc_gpu_snoc_dvm_gfx_clk",
1484 .ops = &clk_branch2_ops,
1485 },
1486 },
1487};
1488
1489static struct clk_branch gcc_pcie0_phy_refgen_clk = {
1490 .halt_reg = 0x6f02c,
1491 .halt_check = BRANCH_HALT,
1492 .clkr = {
1493 .enable_reg = 0x6f02c,
1494 .enable_mask = BIT(0),
1495 .hw.init = &(const struct clk_init_data) {
1496 .name = "gcc_pcie0_phy_refgen_clk",
1497 .parent_hws = (const struct clk_hw*[]) {
1498 &gcc_pcie_phy_refgen_clk_src.clkr.hw,
1499 },
1500 .num_parents = 1,
1501 .flags = CLK_SET_RATE_PARENT,
1502 .ops = &clk_branch2_ops,
1503 },
1504 },
1505};
1506
1507static struct clk_branch gcc_pcie_0_aux_clk = {
1508 .halt_reg = 0x6b020,
1509 .halt_check = BRANCH_HALT_VOTED,
1510 .clkr = {
1511 .enable_reg = 0x5200c,
1512 .enable_mask = BIT(3),
1513 .hw.init = &(const struct clk_init_data) {
1514 .name = "gcc_pcie_0_aux_clk",
1515 .parent_hws = (const struct clk_hw*[]) {
1516 &gcc_pcie_0_aux_clk_src.clkr.hw,
1517 },
1518 .num_parents = 1,
1519 .flags = CLK_SET_RATE_PARENT,
1520 .ops = &clk_branch2_ops,
1521 },
1522 },
1523};
1524
1525static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
1526 .halt_reg = 0x6b01c,
1527 .halt_check = BRANCH_HALT_VOTED,
1528 .hwcg_reg = 0x6b01c,
1529 .hwcg_bit = 1,
1530 .clkr = {
1531 .enable_reg = 0x5200c,
1532 .enable_mask = BIT(2),
1533 .hw.init = &(const struct clk_init_data) {
1534 .name = "gcc_pcie_0_cfg_ahb_clk",
1535 .ops = &clk_branch2_ops,
1536 },
1537 },
1538};
1539
1540static struct clk_branch gcc_pcie_0_clkref_clk = {
1541 .halt_reg = 0x8c00c,
1542 .halt_check = BRANCH_HALT,
1543 .clkr = {
1544 .enable_reg = 0x8c00c,
1545 .enable_mask = BIT(0),
1546 .hw.init = &(const struct clk_init_data) {
1547 .name = "gcc_pcie_0_clkref_clk",
1548 .ops = &clk_branch2_ops,
1549 },
1550 },
1551};
1552
1553static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
1554 .halt_reg = 0x6b018,
1555 .halt_check = BRANCH_HALT_VOTED,
1556 .clkr = {
1557 .enable_reg = 0x5200c,
1558 .enable_mask = BIT(1),
1559 .hw.init = &(const struct clk_init_data) {
1560 .name = "gcc_pcie_0_mstr_axi_clk",
1561 .ops = &clk_branch2_ops,
1562 },
1563 },
1564};
1565
1566static struct clk_branch gcc_pcie_0_pipe_clk = {
1567 .halt_reg = 0x6b024,
1568 .halt_check = BRANCH_HALT_SKIP,
1569 .clkr = {
1570 .enable_reg = 0x5200c,
1571 .enable_mask = BIT(4),
1572 .hw.init = &(const struct clk_init_data) {
1573 .name = "gcc_pcie_0_pipe_clk",
1574 .ops = &clk_branch2_ops,
1575 },
1576 },
1577};
1578
1579static struct clk_branch gcc_pcie_0_slv_axi_clk = {
1580 .halt_reg = 0x6b014,
1581 .halt_check = BRANCH_HALT_VOTED,
1582 .hwcg_reg = 0x6b014,
1583 .hwcg_bit = 1,
1584 .clkr = {
1585 .enable_reg = 0x5200c,
1586 .enable_mask = BIT(0),
1587 .hw.init = &(const struct clk_init_data) {
1588 .name = "gcc_pcie_0_slv_axi_clk",
1589 .ops = &clk_branch2_ops,
1590 },
1591 },
1592};
1593
1594static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
1595 .halt_reg = 0x6b010,
1596 .halt_check = BRANCH_HALT_VOTED,
1597 .clkr = {
1598 .enable_reg = 0x5200c,
1599 .enable_mask = BIT(5),
1600 .hw.init = &(const struct clk_init_data) {
1601 .name = "gcc_pcie_0_slv_q2a_axi_clk",
1602 .ops = &clk_branch2_ops,
1603 },
1604 },
1605};
1606
1607static struct clk_branch gcc_pcie_phy_aux_clk = {
1608 .halt_reg = 0x6f004,
1609 .halt_check = BRANCH_HALT,
1610 .clkr = {
1611 .enable_reg = 0x6f004,
1612 .enable_mask = BIT(0),
1613 .hw.init = &(const struct clk_init_data) {
1614 .name = "gcc_pcie_phy_aux_clk",
1615 .parent_hws = (const struct clk_hw*[]) {
1616 &gcc_pcie_0_aux_clk_src.clkr.hw,
1617 },
1618 .num_parents = 1,
1619 .flags = CLK_SET_RATE_PARENT,
1620 .ops = &clk_branch2_ops,
1621 },
1622 },
1623};
1624
1625static struct clk_branch gcc_pdm2_clk = {
1626 .halt_reg = 0x3300c,
1627 .halt_check = BRANCH_HALT,
1628 .clkr = {
1629 .enable_reg = 0x3300c,
1630 .enable_mask = BIT(0),
1631 .hw.init = &(const struct clk_init_data) {
1632 .name = "gcc_pdm2_clk",
1633 .parent_hws = (const struct clk_hw*[]) {
1634 &gcc_pdm2_clk_src.clkr.hw,
1635 },
1636 .num_parents = 1,
1637 .flags = CLK_SET_RATE_PARENT,
1638 .ops = &clk_branch2_ops,
1639 },
1640 },
1641};
1642
1643static struct clk_branch gcc_pdm_ahb_clk = {
1644 .halt_reg = 0x33004,
1645 .halt_check = BRANCH_HALT,
1646 .hwcg_reg = 0x33004,
1647 .hwcg_bit = 1,
1648 .clkr = {
1649 .enable_reg = 0x33004,
1650 .enable_mask = BIT(0),
1651 .hw.init = &(const struct clk_init_data) {
1652 .name = "gcc_pdm_ahb_clk",
1653 .ops = &clk_branch2_ops,
1654 },
1655 },
1656};
1657
1658static struct clk_branch gcc_pdm_xo4_clk = {
1659 .halt_reg = 0x33008,
1660 .halt_check = BRANCH_HALT,
1661 .clkr = {
1662 .enable_reg = 0x33008,
1663 .enable_mask = BIT(0),
1664 .hw.init = &(const struct clk_init_data) {
1665 .name = "gcc_pdm_xo4_clk",
1666 .ops = &clk_branch2_ops,
1667 },
1668 },
1669};
1670
1671static struct clk_branch gcc_prng_ahb_clk = {
1672 .halt_reg = 0x34004,
1673 .halt_check = BRANCH_HALT_VOTED,
1674 .hwcg_reg = 0x34004,
1675 .hwcg_bit = 1,
1676 .clkr = {
1677 .enable_reg = 0x52004,
1678 .enable_mask = BIT(13),
1679 .hw.init = &(const struct clk_init_data) {
1680 .name = "gcc_prng_ahb_clk",
1681 .ops = &clk_branch2_ops,
1682 },
1683 },
1684};
1685
1686static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
1687 .halt_reg = 0xb018,
1688 .halt_check = BRANCH_HALT_VOTED,
1689 .hwcg_reg = 0xb018,
1690 .hwcg_bit = 1,
1691 .clkr = {
1692 .enable_reg = 0xb018,
1693 .enable_mask = BIT(0),
1694 .hw.init = &(const struct clk_init_data) {
1695 .name = "gcc_qmip_camera_nrt_ahb_clk",
1696 .ops = &clk_branch2_ops,
1697 },
1698 },
1699};
1700
1701static struct clk_branch gcc_qmip_disp_ahb_clk = {
1702 .halt_reg = 0xb020,
1703 .halt_check = BRANCH_HALT_VOTED,
1704 .hwcg_reg = 0xb020,
1705 .hwcg_bit = 1,
1706 .clkr = {
1707 .enable_reg = 0xb020,
1708 .enable_mask = BIT(0),
1709 .hw.init = &(const struct clk_init_data) {
1710 .name = "gcc_qmip_disp_ahb_clk",
1711 .ops = &clk_branch2_ops,
1712 },
1713 },
1714};
1715
1716static struct clk_branch gcc_qmip_pcie_ahb_clk = {
1717 .halt_reg = 0x6b044,
1718 .halt_check = BRANCH_HALT_VOTED,
1719 .hwcg_reg = 0x6b044,
1720 .hwcg_bit = 1,
1721 .clkr = {
1722 .enable_reg = 0x5200c,
1723 .enable_mask = BIT(28),
1724 .hw.init = &(const struct clk_init_data) {
1725 .name = "gcc_qmip_pcie_ahb_clk",
1726 .ops = &clk_branch2_ops,
1727 },
1728 },
1729};
1730
1731static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
1732 .halt_reg = 0xb014,
1733 .halt_check = BRANCH_HALT_VOTED,
1734 .hwcg_reg = 0xb014,
1735 .hwcg_bit = 1,
1736 .clkr = {
1737 .enable_reg = 0xb014,
1738 .enable_mask = BIT(0),
1739 .hw.init = &(const struct clk_init_data) {
1740 .name = "gcc_qmip_video_vcodec_ahb_clk",
1741 .ops = &clk_branch2_ops,
1742 },
1743 },
1744};
1745
1746static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = {
1747 .halt_reg = 0x4b000,
1748 .halt_check = BRANCH_HALT_VOTED,
1749 .clkr = {
1750 .enable_reg = 0x4b000,
1751 .enable_mask = BIT(0),
1752 .hw.init = &(const struct clk_init_data) {
1753 .name = "gcc_qspi_cnoc_periph_ahb_clk",
1754 .ops = &clk_branch2_ops,
1755 },
1756 },
1757};
1758
1759static struct clk_branch gcc_qspi_core_clk = {
1760 .halt_reg = 0x4b004,
1761 .halt_check = BRANCH_HALT,
1762 .clkr = {
1763 .enable_reg = 0x4b004,
1764 .enable_mask = BIT(0),
1765 .hw.init = &(const struct clk_init_data) {
1766 .name = "gcc_qspi_core_clk",
1767 .parent_hws = (const struct clk_hw*[]) {
1768 &gcc_qspi_core_clk_src.clkr.hw,
1769 },
1770 .num_parents = 1,
1771 .flags = CLK_SET_RATE_PARENT,
1772 .ops = &clk_branch2_ops,
1773 },
1774 },
1775};
1776
1777static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
1778 .halt_reg = 0x17014,
1779 .halt_check = BRANCH_HALT_VOTED,
1780 .clkr = {
1781 .enable_reg = 0x5200c,
1782 .enable_mask = BIT(9),
1783 .hw.init = &(const struct clk_init_data) {
1784 .name = "gcc_qupv3_wrap0_core_2x_clk",
1785 .ops = &clk_branch2_ops,
1786 },
1787 },
1788};
1789
1790static struct clk_branch gcc_qupv3_wrap0_core_clk = {
1791 .halt_reg = 0x1700c,
1792 .halt_check = BRANCH_HALT_VOTED,
1793 .clkr = {
1794 .enable_reg = 0x5200c,
1795 .enable_mask = BIT(8),
1796 .hw.init = &(const struct clk_init_data) {
1797 .name = "gcc_qupv3_wrap0_core_clk",
1798 .ops = &clk_branch2_ops,
1799 },
1800 },
1801};
1802
1803static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
1804 .halt_reg = 0x17144,
1805 .halt_check = BRANCH_HALT_VOTED,
1806 .clkr = {
1807 .enable_reg = 0x5200c,
1808 .enable_mask = BIT(10),
1809 .hw.init = &(const struct clk_init_data) {
1810 .name = "gcc_qupv3_wrap0_s0_clk",
1811 .parent_hws = (const struct clk_hw*[]) {
1812 &gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
1813 },
1814 .num_parents = 1,
1815 .flags = CLK_SET_RATE_PARENT,
1816 .ops = &clk_branch2_ops,
1817 },
1818 },
1819};
1820
1821static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
1822 .halt_reg = 0x17274,
1823 .halt_check = BRANCH_HALT_VOTED,
1824 .clkr = {
1825 .enable_reg = 0x5200c,
1826 .enable_mask = BIT(11),
1827 .hw.init = &(const struct clk_init_data) {
1828 .name = "gcc_qupv3_wrap0_s1_clk",
1829 .parent_hws = (const struct clk_hw*[]) {
1830 &gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
1831 },
1832 .num_parents = 1,
1833 .flags = CLK_SET_RATE_PARENT,
1834 .ops = &clk_branch2_ops,
1835 },
1836 },
1837};
1838
1839static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
1840 .halt_reg = 0x173a4,
1841 .halt_check = BRANCH_HALT_VOTED,
1842 .clkr = {
1843 .enable_reg = 0x5200c,
1844 .enable_mask = BIT(12),
1845 .hw.init = &(const struct clk_init_data) {
1846 .name = "gcc_qupv3_wrap0_s2_clk",
1847 .parent_hws = (const struct clk_hw*[]) {
1848 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
1849 },
1850 .num_parents = 1,
1851 .flags = CLK_SET_RATE_PARENT,
1852 .ops = &clk_branch2_ops,
1853 },
1854 },
1855};
1856
1857static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
1858 .halt_reg = 0x174d4,
1859 .halt_check = BRANCH_HALT_VOTED,
1860 .clkr = {
1861 .enable_reg = 0x5200c,
1862 .enable_mask = BIT(13),
1863 .hw.init = &(const struct clk_init_data) {
1864 .name = "gcc_qupv3_wrap0_s3_clk",
1865 .parent_hws = (const struct clk_hw*[]) {
1866 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
1867 },
1868 .num_parents = 1,
1869 .flags = CLK_SET_RATE_PARENT,
1870 .ops = &clk_branch2_ops,
1871 },
1872 },
1873};
1874
1875static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
1876 .halt_reg = 0x17604,
1877 .halt_check = BRANCH_HALT_VOTED,
1878 .clkr = {
1879 .enable_reg = 0x5200c,
1880 .enable_mask = BIT(14),
1881 .hw.init = &(const struct clk_init_data) {
1882 .name = "gcc_qupv3_wrap0_s4_clk",
1883 .parent_hws = (const struct clk_hw*[]) {
1884 &gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
1885 },
1886 .num_parents = 1,
1887 .flags = CLK_SET_RATE_PARENT,
1888 .ops = &clk_branch2_ops,
1889 },
1890 },
1891};
1892
1893static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
1894 .halt_reg = 0x17734,
1895 .halt_check = BRANCH_HALT_VOTED,
1896 .clkr = {
1897 .enable_reg = 0x5200c,
1898 .enable_mask = BIT(15),
1899 .hw.init = &(const struct clk_init_data) {
1900 .name = "gcc_qupv3_wrap0_s5_clk",
1901 .parent_hws = (const struct clk_hw*[]) {
1902 &gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
1903 },
1904 .num_parents = 1,
1905 .flags = CLK_SET_RATE_PARENT,
1906 .ops = &clk_branch2_ops,
1907 },
1908 },
1909};
1910
1911static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
1912 .halt_reg = 0x18014,
1913 .halt_check = BRANCH_HALT_VOTED,
1914 .clkr = {
1915 .enable_reg = 0x5200c,
1916 .enable_mask = BIT(18),
1917 .hw.init = &(const struct clk_init_data) {
1918 .name = "gcc_qupv3_wrap1_core_2x_clk",
1919 .ops = &clk_branch2_ops,
1920 },
1921 },
1922};
1923
1924static struct clk_branch gcc_qupv3_wrap1_core_clk = {
1925 .halt_reg = 0x1800c,
1926 .halt_check = BRANCH_HALT_VOTED,
1927 .clkr = {
1928 .enable_reg = 0x5200c,
1929 .enable_mask = BIT(19),
1930 .hw.init = &(const struct clk_init_data) {
1931 .name = "gcc_qupv3_wrap1_core_clk",
1932 .ops = &clk_branch2_ops,
1933 },
1934 },
1935};
1936
1937static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
1938 .halt_reg = 0x18144,
1939 .halt_check = BRANCH_HALT_VOTED,
1940 .clkr = {
1941 .enable_reg = 0x5200c,
1942 .enable_mask = BIT(22),
1943 .hw.init = &(const struct clk_init_data) {
1944 .name = "gcc_qupv3_wrap1_s0_clk",
1945 .parent_hws = (const struct clk_hw*[]) {
1946 &gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
1947 },
1948 .num_parents = 1,
1949 .flags = CLK_SET_RATE_PARENT,
1950 .ops = &clk_branch2_ops,
1951 },
1952 },
1953};
1954
1955static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
1956 .halt_reg = 0x18274,
1957 .halt_check = BRANCH_HALT_VOTED,
1958 .clkr = {
1959 .enable_reg = 0x5200c,
1960 .enable_mask = BIT(23),
1961 .hw.init = &(const struct clk_init_data) {
1962 .name = "gcc_qupv3_wrap1_s1_clk",
1963 .parent_hws = (const struct clk_hw*[]) {
1964 &gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
1965 },
1966 .num_parents = 1,
1967 .flags = CLK_SET_RATE_PARENT,
1968 .ops = &clk_branch2_ops,
1969 },
1970 },
1971};
1972
1973static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
1974 .halt_reg = 0x183a4,
1975 .halt_check = BRANCH_HALT_VOTED,
1976 .clkr = {
1977 .enable_reg = 0x5200c,
1978 .enable_mask = BIT(24),
1979 .hw.init = &(const struct clk_init_data) {
1980 .name = "gcc_qupv3_wrap1_s2_clk",
1981 .parent_hws = (const struct clk_hw*[]) {
1982 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
1983 },
1984 .num_parents = 1,
1985 .flags = CLK_SET_RATE_PARENT,
1986 .ops = &clk_branch2_ops,
1987 },
1988 },
1989};
1990
1991static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
1992 .halt_reg = 0x184d4,
1993 .halt_check = BRANCH_HALT_VOTED,
1994 .clkr = {
1995 .enable_reg = 0x5200c,
1996 .enable_mask = BIT(25),
1997 .hw.init = &(const struct clk_init_data) {
1998 .name = "gcc_qupv3_wrap1_s3_clk",
1999 .parent_hws = (const struct clk_hw*[]) {
2000 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
2001 },
2002 .num_parents = 1,
2003 .flags = CLK_SET_RATE_PARENT,
2004 .ops = &clk_branch2_ops,
2005 },
2006 },
2007};
2008
2009static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
2010 .halt_reg = 0x18604,
2011 .halt_check = BRANCH_HALT_VOTED,
2012 .clkr = {
2013 .enable_reg = 0x5200c,
2014 .enable_mask = BIT(26),
2015 .hw.init = &(const struct clk_init_data) {
2016 .name = "gcc_qupv3_wrap1_s4_clk",
2017 .parent_hws = (const struct clk_hw*[]) {
2018 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
2019 },
2020 .num_parents = 1,
2021 .flags = CLK_SET_RATE_PARENT,
2022 .ops = &clk_branch2_ops,
2023 },
2024 },
2025};
2026
2027static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
2028 .halt_reg = 0x18734,
2029 .halt_check = BRANCH_HALT_VOTED,
2030 .clkr = {
2031 .enable_reg = 0x5200c,
2032 .enable_mask = BIT(27),
2033 .hw.init = &(const struct clk_init_data) {
2034 .name = "gcc_qupv3_wrap1_s5_clk",
2035 .parent_hws = (const struct clk_hw*[]) {
2036 &gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
2037 },
2038 .num_parents = 1,
2039 .flags = CLK_SET_RATE_PARENT,
2040 .ops = &clk_branch2_ops,
2041 },
2042 },
2043};
2044
2045static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
2046 .halt_reg = 0x17004,
2047 .halt_check = BRANCH_HALT_VOTED,
2048 .clkr = {
2049 .enable_reg = 0x5200c,
2050 .enable_mask = BIT(6),
2051 .hw.init = &(const struct clk_init_data) {
2052 .name = "gcc_qupv3_wrap_0_m_ahb_clk",
2053 .ops = &clk_branch2_ops,
2054 },
2055 },
2056};
2057
2058static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
2059 .halt_reg = 0x17008,
2060 .halt_check = BRANCH_HALT_VOTED,
2061 .hwcg_reg = 0x17008,
2062 .hwcg_bit = 1,
2063 .clkr = {
2064 .enable_reg = 0x5200c,
2065 .enable_mask = BIT(7),
2066 .hw.init = &(const struct clk_init_data) {
2067 .name = "gcc_qupv3_wrap_0_s_ahb_clk",
2068 .ops = &clk_branch2_ops,
2069 },
2070 },
2071};
2072
2073static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
2074 .halt_reg = 0x18004,
2075 .halt_check = BRANCH_HALT_VOTED,
2076 .clkr = {
2077 .enable_reg = 0x5200c,
2078 .enable_mask = BIT(20),
2079 .hw.init = &(const struct clk_init_data) {
2080 .name = "gcc_qupv3_wrap_1_m_ahb_clk",
2081 .ops = &clk_branch2_ops,
2082 },
2083 },
2084};
2085
2086static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
2087 .halt_reg = 0x18008,
2088 .halt_check = BRANCH_HALT_VOTED,
2089 .hwcg_reg = 0x18008,
2090 .hwcg_bit = 1,
2091 .clkr = {
2092 .enable_reg = 0x5200c,
2093 .enable_mask = BIT(21),
2094 .hw.init = &(const struct clk_init_data) {
2095 .name = "gcc_qupv3_wrap_1_s_ahb_clk",
2096 .ops = &clk_branch2_ops,
2097 },
2098 },
2099};
2100
2101static struct clk_branch gcc_rx1_usb2_clkref_clk = {
2102 .halt_reg = 0x8c030,
2103 .halt_check = BRANCH_HALT,
2104 .clkr = {
2105 .enable_reg = 0x8c030,
2106 .enable_mask = BIT(0),
2107 .hw.init = &(const struct clk_init_data) {
2108 .name = "gcc_rx1_usb2_clkref_clk",
2109 .ops = &clk_branch2_ops,
2110 },
2111 },
2112};
2113
2114static struct clk_branch gcc_rx3_usb2_clkref_clk = {
2115 .halt_reg = 0x8c038,
2116 .halt_check = BRANCH_HALT_VOTED,
2117 .clkr = {
2118 .enable_reg = 0x8c038,
2119 .enable_mask = BIT(0),
2120 .hw.init = &(const struct clk_init_data) {
2121 .name = "gcc_rx3_usb2_clkref_clk",
2122 .ops = &clk_branch2_ops,
2123 },
2124 },
2125};
2126
2127static struct clk_branch gcc_sdcc1_ahb_clk = {
2128 .halt_reg = 0x12008,
2129 .halt_check = BRANCH_HALT,
2130 .clkr = {
2131 .enable_reg = 0x12008,
2132 .enable_mask = BIT(0),
2133 .hw.init = &(const struct clk_init_data) {
2134 .name = "gcc_sdcc1_ahb_clk",
2135 .ops = &clk_branch2_ops,
2136 },
2137 },
2138};
2139
2140static struct clk_branch gcc_sdcc1_apps_clk = {
2141 .halt_reg = 0x12004,
2142 .halt_check = BRANCH_HALT,
2143 .clkr = {
2144 .enable_reg = 0x12004,
2145 .enable_mask = BIT(0),
2146 .hw.init = &(const struct clk_init_data) {
2147 .name = "gcc_sdcc1_apps_clk",
2148 .parent_hws = (const struct clk_hw*[]) {
2149 &gcc_sdcc1_apps_clk_src.clkr.hw,
2150 },
2151 .num_parents = 1,
2152 .flags = CLK_SET_RATE_PARENT,
2153 .ops = &clk_branch2_ops,
2154 },
2155 },
2156};
2157
2158static struct clk_branch gcc_sdcc1_ice_core_clk = {
2159 .halt_reg = 0x1200c,
2160 .halt_check = BRANCH_HALT,
2161 .clkr = {
2162 .enable_reg = 0x1200c,
2163 .enable_mask = BIT(0),
2164 .hw.init = &(const struct clk_init_data) {
2165 .name = "gcc_sdcc1_ice_core_clk",
2166 .parent_hws = (const struct clk_hw*[]) {
2167 &gcc_sdcc1_ice_core_clk_src.clkr.hw,
2168 },
2169 .num_parents = 1,
2170 .flags = CLK_SET_RATE_PARENT,
2171 .ops = &clk_branch2_ops,
2172 },
2173 },
2174};
2175
2176static struct clk_branch gcc_sdcc2_ahb_clk = {
2177 .halt_reg = 0x14008,
2178 .halt_check = BRANCH_HALT,
2179 .clkr = {
2180 .enable_reg = 0x14008,
2181 .enable_mask = BIT(0),
2182 .hw.init = &(const struct clk_init_data) {
2183 .name = "gcc_sdcc2_ahb_clk",
2184 .ops = &clk_branch2_ops,
2185 },
2186 },
2187};
2188
2189static struct clk_branch gcc_sdcc2_apps_clk = {
2190 .halt_reg = 0x14004,
2191 .halt_check = BRANCH_HALT,
2192 .clkr = {
2193 .enable_reg = 0x14004,
2194 .enable_mask = BIT(0),
2195 .hw.init = &(const struct clk_init_data) {
2196 .name = "gcc_sdcc2_apps_clk",
2197 .parent_hws = (const struct clk_hw*[]) {
2198 &gcc_sdcc2_apps_clk_src.clkr.hw,
2199 },
2200 .num_parents = 1,
2201 .flags = CLK_SET_RATE_PARENT,
2202 .ops = &clk_branch2_ops,
2203 },
2204 },
2205};
2206
2207static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
2208 .halt_reg = 0x4819c,
2209 .halt_check = BRANCH_HALT_VOTED,
2210 .clkr = {
2211 .enable_reg = 0x52004,
2212 .enable_mask = BIT(0),
2213 .hw.init = &(struct clk_init_data) {
2214 .name = "gcc_sys_noc_cpuss_ahb_clk",
2215 .parent_data = &(const struct clk_parent_data) {
2216 .hw = &gcc_cpuss_ahb_clk_src.clkr.hw,
2217 },
2218 .num_parents = 1,
2219 .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
2220 .ops = &clk_branch2_ops,
2221 },
2222 },
2223};
2224
2225static struct clk_branch gcc_ufs_card_clkref_clk = {
2226 .halt_reg = 0x8c004,
2227 .halt_check = BRANCH_HALT_VOTED,
2228 .clkr = {
2229 .enable_reg = 0x8c004,
2230 .enable_mask = BIT(0),
2231 .hw.init = &(const struct clk_init_data) {
2232 .name = "gcc_ufs_card_clkref_clk",
2233 .ops = &clk_branch2_ops,
2234 },
2235 },
2236};
2237
2238static struct clk_branch gcc_ufs_mem_clkref_clk = {
2239 .halt_reg = 0x8c000,
2240 .halt_check = BRANCH_HALT,
2241 .clkr = {
2242 .enable_reg = 0x8c000,
2243 .enable_mask = BIT(0),
2244 .hw.init = &(const struct clk_init_data) {
2245 .name = "gcc_ufs_mem_clkref_clk",
2246 .ops = &clk_branch2_ops,
2247 },
2248 },
2249};
2250
2251static struct clk_branch gcc_ufs_phy_ahb_clk = {
2252 .halt_reg = 0x77014,
2253 .halt_check = BRANCH_HALT_VOTED,
2254 .hwcg_reg = 0x77014,
2255 .hwcg_bit = 1,
2256 .clkr = {
2257 .enable_reg = 0x77014,
2258 .enable_mask = BIT(0),
2259 .hw.init = &(const struct clk_init_data) {
2260 .name = "gcc_ufs_phy_ahb_clk",
2261 .ops = &clk_branch2_ops,
2262 },
2263 },
2264};
2265
2266static struct clk_branch gcc_ufs_phy_axi_clk = {
2267 .halt_reg = 0x77010,
2268 .halt_check = BRANCH_HALT,
2269 .hwcg_reg = 0x77010,
2270 .hwcg_bit = 1,
2271 .clkr = {
2272 .enable_reg = 0x77010,
2273 .enable_mask = BIT(0),
2274 .hw.init = &(const struct clk_init_data) {
2275 .name = "gcc_ufs_phy_axi_clk",
2276 .parent_hws = (const struct clk_hw*[]) {
2277 &gcc_ufs_phy_axi_clk_src.clkr.hw,
2278 },
2279 .num_parents = 1,
2280 .flags = CLK_SET_RATE_PARENT,
2281 .ops = &clk_branch2_ops,
2282 },
2283 },
2284};
2285
2286static struct clk_branch gcc_ufs_phy_ice_core_clk = {
2287 .halt_reg = 0x77044,
2288 .halt_check = BRANCH_HALT,
2289 .hwcg_reg = 0x77044,
2290 .hwcg_bit = 1,
2291 .clkr = {
2292 .enable_reg = 0x77044,
2293 .enable_mask = BIT(0),
2294 .hw.init = &(const struct clk_init_data) {
2295 .name = "gcc_ufs_phy_ice_core_clk",
2296 .parent_hws = (const struct clk_hw*[]) {
2297 &gcc_ufs_phy_ice_core_clk_src.clkr.hw,
2298 },
2299 .num_parents = 1,
2300 .flags = CLK_SET_RATE_PARENT,
2301 .ops = &clk_branch2_ops,
2302 },
2303 },
2304};
2305
2306static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
2307 .halt_reg = 0x77078,
2308 .halt_check = BRANCH_HALT,
2309 .hwcg_reg = 0x77078,
2310 .hwcg_bit = 1,
2311 .clkr = {
2312 .enable_reg = 0x77078,
2313 .enable_mask = BIT(0),
2314 .hw.init = &(const struct clk_init_data) {
2315 .name = "gcc_ufs_phy_phy_aux_clk",
2316 .parent_hws = (const struct clk_hw*[]) {
2317 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
2318 },
2319 .num_parents = 1,
2320 .flags = CLK_SET_RATE_PARENT,
2321 .ops = &clk_branch2_ops,
2322 },
2323 },
2324};
2325
2326static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
2327 .halt_reg = 0x7701c,
2328 .halt_check = BRANCH_HALT_DELAY,
2329 .clkr = {
2330 .enable_reg = 0x7701c,
2331 .enable_mask = BIT(0),
2332 .hw.init = &(const struct clk_init_data) {
2333 .name = "gcc_ufs_phy_rx_symbol_0_clk",
2334 .ops = &clk_branch2_ops,
2335 },
2336 },
2337};
2338
2339static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
2340 .halt_reg = 0x77018,
2341 .halt_check = BRANCH_HALT_DELAY,
2342 .clkr = {
2343 .enable_reg = 0x77018,
2344 .enable_mask = BIT(0),
2345 .hw.init = &(const struct clk_init_data) {
2346 .name = "gcc_ufs_phy_tx_symbol_0_clk",
2347 .ops = &clk_branch2_ops,
2348 },
2349 },
2350};
2351
2352static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
2353 .halt_reg = 0x77040,
2354 .halt_check = BRANCH_HALT,
2355 .hwcg_reg = 0x77040,
2356 .hwcg_bit = 1,
2357 .clkr = {
2358 .enable_reg = 0x77040,
2359 .enable_mask = BIT(0),
2360 .hw.init = &(const struct clk_init_data) {
2361 .name = "gcc_ufs_phy_unipro_core_clk",
2362 .parent_hws = (const struct clk_hw*[]) {
2363 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
2364 },
2365 .num_parents = 1,
2366 .flags = CLK_SET_RATE_PARENT,
2367 .ops = &clk_branch2_ops,
2368 },
2369 },
2370};
2371
2372static struct clk_branch gcc_usb20_sec_master_clk = {
2373 .halt_reg = 0xa6010,
2374 .halt_check = BRANCH_HALT_VOTED,
2375 .clkr = {
2376 .enable_reg = 0xa6010,
2377 .enable_mask = BIT(0),
2378 .hw.init = &(const struct clk_init_data) {
2379 .name = "gcc_usb20_sec_master_clk",
2380 .parent_hws = (const struct clk_hw*[]) {
2381 &gcc_usb20_sec_master_clk_src.clkr.hw,
2382 },
2383 .num_parents = 1,
2384 .flags = CLK_SET_RATE_PARENT,
2385 .ops = &clk_branch2_ops,
2386 },
2387 },
2388};
2389
2390static struct clk_branch gcc_usb20_sec_mock_utmi_clk = {
2391 .halt_reg = 0xa6018,
2392 .halt_check = BRANCH_HALT,
2393 .clkr = {
2394 .enable_reg = 0xa6018,
2395 .enable_mask = BIT(0),
2396 .hw.init = &(const struct clk_init_data) {
2397 .name = "gcc_usb20_sec_mock_utmi_clk",
2398 .parent_hws = (const struct clk_hw*[]) {
2399 &gcc_usb20_sec_mock_utmi_clk_src.clkr.hw,
2400 },
2401 .num_parents = 1,
2402 .flags = CLK_SET_RATE_PARENT,
2403 .ops = &clk_branch2_ops,
2404 },
2405 },
2406};
2407
2408static struct clk_branch gcc_usb20_sec_sleep_clk = {
2409 .halt_reg = 0xa6014,
2410 .halt_check = BRANCH_HALT,
2411 .clkr = {
2412 .enable_reg = 0xa6014,
2413 .enable_mask = BIT(0),
2414 .hw.init = &(const struct clk_init_data) {
2415 .name = "gcc_usb20_sec_sleep_clk",
2416 .ops = &clk_branch2_ops,
2417 },
2418 },
2419};
2420
2421static struct clk_branch gcc_usb2_prim_clkref_clk = {
2422 .halt_reg = 0x8c028,
2423 .halt_check = BRANCH_HALT_VOTED,
2424 .clkr = {
2425 .enable_reg = 0x8c028,
2426 .enable_mask = BIT(0),
2427 .hw.init = &(const struct clk_init_data) {
2428 .name = "gcc_usb2_prim_clkref_clk",
2429 .ops = &clk_branch2_ops,
2430 },
2431 },
2432};
2433
2434static struct clk_branch gcc_usb2_sec_clkref_clk = {
2435 .halt_reg = 0x8c018,
2436 .halt_check = BRANCH_HALT_VOTED,
2437 .clkr = {
2438 .enable_reg = 0x8c018,
2439 .enable_mask = BIT(0),
2440 .hw.init = &(const struct clk_init_data) {
2441 .name = "gcc_usb2_sec_clkref_clk",
2442 .ops = &clk_branch2_ops,
2443 },
2444 },
2445};
2446
2447static struct clk_branch gcc_usb2_sec_phy_aux_clk = {
2448 .halt_reg = 0xa6050,
2449 .halt_check = BRANCH_HALT,
2450 .clkr = {
2451 .enable_reg = 0xa6050,
2452 .enable_mask = BIT(0),
2453 .hw.init = &(const struct clk_init_data) {
2454 .name = "gcc_usb2_sec_phy_aux_clk",
2455 .parent_hws = (const struct clk_hw*[]) {
2456 &gcc_usb2_sec_phy_aux_clk_src.clkr.hw,
2457 },
2458 .num_parents = 1,
2459 .flags = CLK_SET_RATE_PARENT,
2460 .ops = &clk_branch2_ops,
2461 },
2462 },
2463};
2464
2465static struct clk_branch gcc_usb2_sec_phy_com_aux_clk = {
2466 .halt_reg = 0xa6054,
2467 .halt_check = BRANCH_HALT,
2468 .clkr = {
2469 .enable_reg = 0xa6054,
2470 .enable_mask = BIT(0),
2471 .hw.init = &(const struct clk_init_data) {
2472 .name = "gcc_usb2_sec_phy_com_aux_clk",
2473 .parent_hws = (const struct clk_hw*[]) {
2474 &gcc_usb2_sec_phy_aux_clk_src.clkr.hw,
2475 },
2476 .num_parents = 1,
2477 .flags = CLK_SET_RATE_PARENT,
2478 .ops = &clk_branch2_ops,
2479 },
2480 },
2481};
2482
2483static struct clk_branch gcc_usb2_sec_phy_pipe_clk = {
2484 .halt_reg = 0xa6058,
2485 .halt_check = BRANCH_HALT_SKIP,
2486 .clkr = {
2487 .enable_reg = 0xa6058,
2488 .enable_mask = BIT(0),
2489 .hw.init = &(const struct clk_init_data) {
2490 .name = "gcc_usb2_sec_phy_pipe_clk",
2491 .ops = &clk_branch2_ops,
2492 },
2493 },
2494};
2495
2496static struct clk_branch gcc_usb30_prim_master_clk = {
2497 .halt_reg = 0xf010,
2498 .halt_check = BRANCH_HALT_VOTED,
2499 .clkr = {
2500 .enable_reg = 0xf010,
2501 .enable_mask = BIT(0),
2502 .hw.init = &(const struct clk_init_data) {
2503 .name = "gcc_usb30_prim_master_clk",
2504 .parent_hws = (const struct clk_hw*[]) {
2505 &gcc_usb30_prim_master_clk_src.clkr.hw,
2506 },
2507 .num_parents = 1,
2508 .flags = CLK_SET_RATE_PARENT,
2509 .ops = &clk_branch2_ops,
2510 },
2511 },
2512};
2513
2514static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
2515 .halt_reg = 0xf018,
2516 .halt_check = BRANCH_HALT,
2517 .clkr = {
2518 .enable_reg = 0xf018,
2519 .enable_mask = BIT(0),
2520 .hw.init = &(const struct clk_init_data) {
2521 .name = "gcc_usb30_prim_mock_utmi_clk",
2522 .parent_hws = (const struct clk_hw*[]) {
2523 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
2524 },
2525 .num_parents = 1,
2526 .flags = CLK_SET_RATE_PARENT,
2527 .ops = &clk_branch2_ops,
2528 },
2529 },
2530};
2531
2532static struct clk_branch gcc_usb30_prim_sleep_clk = {
2533 .halt_reg = 0xf014,
2534 .halt_check = BRANCH_HALT,
2535 .clkr = {
2536 .enable_reg = 0xf014,
2537 .enable_mask = BIT(0),
2538 .hw.init = &(const struct clk_init_data) {
2539 .name = "gcc_usb30_prim_sleep_clk",
2540 .ops = &clk_branch2_ops,
2541 },
2542 },
2543};
2544
2545static struct clk_branch gcc_usb3_prim_clkref_clk = {
2546 .halt_reg = 0x8c014,
2547 .halt_check = BRANCH_HALT_DELAY,
2548 .clkr = {
2549 .enable_reg = 0x8c014,
2550 .enable_mask = BIT(0),
2551 .hw.init = &(const struct clk_init_data) {
2552 .name = "gcc_usb3_prim_clkref_clk",
2553 .ops = &clk_branch2_ops,
2554 },
2555 },
2556};
2557
2558static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
2559 .halt_reg = 0xf050,
2560 .halt_check = BRANCH_HALT,
2561 .clkr = {
2562 .enable_reg = 0xf050,
2563 .enable_mask = BIT(0),
2564 .hw.init = &(const struct clk_init_data) {
2565 .name = "gcc_usb3_prim_phy_aux_clk",
2566 .parent_hws = (const struct clk_hw*[]) {
2567 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
2568 },
2569 .num_parents = 1,
2570 .flags = CLK_SET_RATE_PARENT,
2571 .ops = &clk_branch2_ops,
2572 },
2573 },
2574};
2575
2576static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
2577 .halt_reg = 0xf054,
2578 .halt_check = BRANCH_HALT,
2579 .clkr = {
2580 .enable_reg = 0xf054,
2581 .enable_mask = BIT(0),
2582 .hw.init = &(const struct clk_init_data) {
2583 .name = "gcc_usb3_prim_phy_com_aux_clk",
2584 .parent_hws = (const struct clk_hw*[]) {
2585 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
2586 },
2587 .num_parents = 1,
2588 .flags = CLK_SET_RATE_PARENT,
2589 .ops = &clk_branch2_ops,
2590 },
2591 },
2592};
2593
2594static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
2595 .halt_reg = 0xf058,
2596 .halt_check = BRANCH_HALT_SKIP,
2597 .clkr = {
2598 .enable_reg = 0xf058,
2599 .enable_mask = BIT(0),
2600 .hw.init = &(const struct clk_init_data) {
2601 .name = "gcc_usb3_prim_phy_pipe_clk",
2602 .ops = &clk_branch2_ops,
2603 },
2604 },
2605};
2606
2607static struct clk_branch gcc_usb3_sec_clkref_clk = {
2608 .halt_reg = 0x8c008,
2609 .halt_check = BRANCH_HALT_DELAY,
2610 .clkr = {
2611 .enable_reg = 0x8c008,
2612 .enable_mask = BIT(0),
2613 .hw.init = &(const struct clk_init_data) {
2614 .name = "gcc_usb3_sec_clkref_clk",
2615 .ops = &clk_branch2_ops,
2616 },
2617 },
2618};
2619
2620static struct clk_branch gcc_video_axi0_clk = {
2621 .halt_reg = 0xb024,
2622 .halt_check = BRANCH_HALT_VOTED,
2623 .clkr = {
2624 .enable_reg = 0xb024,
2625 .enable_mask = BIT(0),
2626 .hw.init = &(const struct clk_init_data) {
2627 .name = "gcc_video_axi0_clk",
2628 .ops = &clk_branch2_ops,
2629 },
2630 },
2631};
2632
2633static struct clk_hw *gcc_qcs615_hws[] = {
2634 [GPLL0_OUT_AUX2_DIV] = &gpll0_out_aux2_div.hw,
2635 [GPLL3_OUT_AUX2_DIV] = &gpll3_out_aux2_div.hw,
2636};
2637
2638static struct gdsc emac_gdsc = {
2639 .gdscr = 0x6004,
2640 .en_rest_wait_val = 0x2,
2641 .en_few_wait_val = 0x2,
2642 .clk_dis_wait_val = 0x2,
2643 .pd = {
2644 .name = "emac_gdsc",
2645 },
2646 .pwrsts = PWRSTS_OFF_ON,
2647};
2648
2649static struct gdsc pcie_0_gdsc = {
2650 .gdscr = 0x6b004,
2651 .en_rest_wait_val = 0x2,
2652 .en_few_wait_val = 0x2,
2653 .clk_dis_wait_val = 0x2,
2654 .pd = {
2655 .name = "pcie_0_gdsc",
2656 },
2657 .pwrsts = PWRSTS_OFF_ON,
2658};
2659
2660static struct gdsc ufs_phy_gdsc = {
2661 .gdscr = 0x77004,
2662 .en_rest_wait_val = 0x2,
2663 .en_few_wait_val = 0x2,
2664 .clk_dis_wait_val = 0x2,
2665 .pd = {
2666 .name = "ufs_phy_gdsc",
2667 },
2668 .pwrsts = PWRSTS_OFF_ON,
2669};
2670
2671static struct gdsc usb20_sec_gdsc = {
2672 .gdscr = 0xa6004,
2673 .en_rest_wait_val = 0x2,
2674 .en_few_wait_val = 0x2,
2675 .clk_dis_wait_val = 0x2,
2676 .pd = {
2677 .name = "usb20_sec_gdsc",
2678 },
2679 .pwrsts = PWRSTS_OFF_ON,
2680};
2681
2682static struct gdsc usb30_prim_gdsc = {
2683 .gdscr = 0xf004,
2684 .en_rest_wait_val = 0x2,
2685 .en_few_wait_val = 0x2,
2686 .clk_dis_wait_val = 0x2,
2687 .pd = {
2688 .name = "usb30_prim_gdsc",
2689 },
2690 .pwrsts = PWRSTS_OFF_ON,
2691};
2692
2693static struct gdsc hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc = {
2694 .gdscr = 0x7d040,
2695 .pd = {
2696 .name = "hlos1_vote_aggre_noc_mmu_audio_tbu",
2697 },
2698 .pwrsts = PWRSTS_OFF_ON,
2699 .flags = VOTABLE,
2700};
2701
2702static struct gdsc hlos1_vote_aggre_noc_mmu_tbu1_gdsc = {
2703 .gdscr = 0x7d044,
2704 .pd = {
2705 .name = "hlos1_vote_aggre_noc_mmu_tbu1",
2706 },
2707 .pwrsts = PWRSTS_OFF_ON,
2708 .flags = VOTABLE,
2709};
2710
2711static struct gdsc hlos1_vote_aggre_noc_mmu_tbu2_gdsc = {
2712 .gdscr = 0x7d048,
2713 .pd = {
2714 .name = "hlos1_vote_aggre_noc_mmu_tbu2",
2715 },
2716 .pwrsts = PWRSTS_OFF_ON,
2717 .flags = VOTABLE,
2718};
2719
2720static struct gdsc hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc = {
2721 .gdscr = 0x7d04c,
2722 .pd = {
2723 .name = "hlos1_vote_aggre_noc_mmu_pcie_tbu",
2724 },
2725 .pwrsts = PWRSTS_OFF_ON,
2726 .flags = VOTABLE,
2727};
2728
2729static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = {
2730 .gdscr = 0x7d050,
2731 .pd = {
2732 .name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc",
2733 },
2734 .pwrsts = PWRSTS_OFF_ON,
2735 .flags = VOTABLE,
2736};
2737
2738static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf_gdsc = {
2739 .gdscr = 0x7d054,
2740 .pd = {
2741 .name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc",
2742 },
2743 .pwrsts = PWRSTS_OFF_ON,
2744 .flags = VOTABLE,
2745};
2746
2747static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = {
2748 .gdscr = 0x7d058,
2749 .pd = {
2750 .name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc",
2751 },
2752 .pwrsts = PWRSTS_OFF_ON,
2753 .flags = VOTABLE,
2754};
2755
2756static struct clk_regmap *gcc_qcs615_clocks[] = {
2757 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
2758 [GCC_AGGRE_USB2_SEC_AXI_CLK] = &gcc_aggre_usb2_sec_axi_clk.clkr,
2759 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
2760 [GCC_AHB2PHY_EAST_CLK] = &gcc_ahb2phy_east_clk.clkr,
2761 [GCC_AHB2PHY_WEST_CLK] = &gcc_ahb2phy_west_clk.clkr,
2762 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
2763 [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
2764 [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
2765 [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
2766 [GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
2767 [GCC_CFG_NOC_USB2_SEC_AXI_CLK] = &gcc_cfg_noc_usb2_sec_axi_clk.clkr,
2768 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
2769 [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,
2770 [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
2771 [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
2772 [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr,
2773 [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
2774 [GCC_EMAC_AXI_CLK] = &gcc_emac_axi_clk.clkr,
2775 [GCC_EMAC_PTP_CLK] = &gcc_emac_ptp_clk.clkr,
2776 [GCC_EMAC_PTP_CLK_SRC] = &gcc_emac_ptp_clk_src.clkr,
2777 [GCC_EMAC_RGMII_CLK] = &gcc_emac_rgmii_clk.clkr,
2778 [GCC_EMAC_RGMII_CLK_SRC] = &gcc_emac_rgmii_clk_src.clkr,
2779 [GCC_EMAC_SLV_AHB_CLK] = &gcc_emac_slv_ahb_clk.clkr,
2780 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2781 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
2782 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2783 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
2784 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2785 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
2786 [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
2787 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
2788 [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr,
2789 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
2790 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
2791 [GCC_PCIE0_PHY_REFGEN_CLK] = &gcc_pcie0_phy_refgen_clk.clkr,
2792 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
2793 [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
2794 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
2795 [GCC_PCIE_0_CLKREF_CLK] = &gcc_pcie_0_clkref_clk.clkr,
2796 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
2797 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
2798 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
2799 [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
2800 [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,
2801 [GCC_PCIE_PHY_REFGEN_CLK_SRC] = &gcc_pcie_phy_refgen_clk_src.clkr,
2802 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
2803 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
2804 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
2805 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
2806 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
2807 [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
2808 [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
2809 [GCC_QMIP_PCIE_AHB_CLK] = &gcc_qmip_pcie_ahb_clk.clkr,
2810 [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
2811 [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr,
2812 [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr,
2813 [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr,
2814 [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
2815 [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
2816 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
2817 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
2818 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
2819 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
2820 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
2821 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
2822 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
2823 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
2824 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
2825 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
2826 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
2827 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
2828 [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
2829 [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
2830 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
2831 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
2832 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
2833 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
2834 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
2835 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
2836 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
2837 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
2838 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
2839 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
2840 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
2841 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
2842 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
2843 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
2844 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
2845 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
2846 [GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr,
2847 [GCC_RX3_USB2_CLKREF_CLK] = &gcc_rx3_usb2_clkref_clk.clkr,
2848 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
2849 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
2850 [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
2851 [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
2852 [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr,
2853 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
2854 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
2855 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
2856 [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
2857 [GCC_UFS_CARD_CLKREF_CLK] = &gcc_ufs_card_clkref_clk.clkr,
2858 [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr,
2859 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
2860 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
2861 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
2862 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
2863 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
2864 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
2865 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
2866 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
2867 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
2868 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
2869 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr,
2870 [GCC_USB20_SEC_MASTER_CLK] = &gcc_usb20_sec_master_clk.clkr,
2871 [GCC_USB20_SEC_MASTER_CLK_SRC] = &gcc_usb20_sec_master_clk_src.clkr,
2872 [GCC_USB20_SEC_MOCK_UTMI_CLK] = &gcc_usb20_sec_mock_utmi_clk.clkr,
2873 [GCC_USB20_SEC_MOCK_UTMI_CLK_SRC] = &gcc_usb20_sec_mock_utmi_clk_src.clkr,
2874 [GCC_USB20_SEC_SLEEP_CLK] = &gcc_usb20_sec_sleep_clk.clkr,
2875 [GCC_USB2_PRIM_CLKREF_CLK] = &gcc_usb2_prim_clkref_clk.clkr,
2876 [GCC_USB2_SEC_CLKREF_CLK] = &gcc_usb2_sec_clkref_clk.clkr,
2877 [GCC_USB2_SEC_PHY_AUX_CLK] = &gcc_usb2_sec_phy_aux_clk.clkr,
2878 [GCC_USB2_SEC_PHY_AUX_CLK_SRC] = &gcc_usb2_sec_phy_aux_clk_src.clkr,
2879 [GCC_USB2_SEC_PHY_COM_AUX_CLK] = &gcc_usb2_sec_phy_com_aux_clk.clkr,
2880 [GCC_USB2_SEC_PHY_PIPE_CLK] = &gcc_usb2_sec_phy_pipe_clk.clkr,
2881 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
2882 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
2883 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
2884 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr,
2885 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
2886 [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
2887 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
2888 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
2889 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
2890 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
2891 [GCC_USB3_SEC_CLKREF_CLK] = &gcc_usb3_sec_clkref_clk.clkr,
2892 [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
2893 [GCC_VSENSOR_CLK_SRC] = &gcc_vsensor_clk_src.clkr,
2894 [GPLL0] = &gpll0.clkr,
2895 [GPLL3] = &gpll3.clkr,
2896 [GPLL4] = &gpll4.clkr,
2897 [GPLL6] = &gpll6.clkr,
2898 [GPLL6_OUT_MAIN] = &gpll6_out_main.clkr,
2899 [GPLL7] = &gpll7.clkr,
2900 [GPLL8] = &gpll8.clkr,
2901 [GPLL8_OUT_MAIN] = &gpll8_out_main.clkr,
2902};
2903
2904static struct gdsc *gcc_qcs615_gdscs[] = {
2905 [EMAC_GDSC] = &emac_gdsc,
2906 [PCIE_0_GDSC] = &pcie_0_gdsc,
2907 [UFS_PHY_GDSC] = &ufs_phy_gdsc,
2908 [USB20_SEC_GDSC] = &usb20_sec_gdsc,
2909 [USB30_PRIM_GDSC] = &usb30_prim_gdsc,
2910 [HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC] = &hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc,
2911 [HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC] = &hlos1_vote_aggre_noc_mmu_tbu1_gdsc,
2912 [HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC] = &hlos1_vote_aggre_noc_mmu_tbu2_gdsc,
2913 [HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC] = &hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc,
2914 [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc,
2915 [HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_sf_gdsc,
2916 [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc,
2917};
2918
2919static const struct qcom_reset_map gcc_qcs615_resets[] = {
2920 [GCC_EMAC_BCR] = { 0x6000 },
2921 [GCC_QUSB2PHY_PRIM_BCR] = { 0xd000 },
2922 [GCC_QUSB2PHY_SEC_BCR] = { 0xd004 },
2923 [GCC_USB30_PRIM_BCR] = { 0xf000 },
2924 [GCC_USB2_PHY_SEC_BCR] = { 0x50018 },
2925 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50020 },
2926 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x5001c },
2927 [GCC_PCIE_0_BCR] = { 0x6b000 },
2928 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
2929 [GCC_PCIE_PHY_BCR] = { 0x6f000 },
2930 [GCC_PCIE_PHY_COM_BCR] = { 0x6f010 },
2931 [GCC_UFS_PHY_BCR] = { 0x77000 },
2932 [GCC_USB20_SEC_BCR] = { 0xa6000 },
2933 [GCC_USB3PHY_PHY_PRIM_SP0_BCR] = { 0x50008 },
2934 [GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x50000 },
2935 [GCC_SDCC1_BCR] = { 0x12000 },
2936 [GCC_SDCC2_BCR] = { 0x14000 },
2937};
2938
2939static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
2940 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
2941 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
2942 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
2943 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
2944 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
2945 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
2946 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
2947 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
2948 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
2949 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
2950 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
2951 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
2952};
2953
2954static const struct regmap_config gcc_qcs615_regmap_config = {
2955 .reg_bits = 32,
2956 .reg_stride = 4,
2957 .val_bits = 32,
2958 .max_register = 0xa609c,
2959 .fast_io = true,
2960};
2961
2962static const struct qcom_cc_desc gcc_qcs615_desc = {
2963 .config = &gcc_qcs615_regmap_config,
2964 .clk_hws = gcc_qcs615_hws,
2965 .num_clk_hws = ARRAY_SIZE(gcc_qcs615_hws),
2966 .clks = gcc_qcs615_clocks,
2967 .num_clks = ARRAY_SIZE(gcc_qcs615_clocks),
2968 .resets = gcc_qcs615_resets,
2969 .num_resets = ARRAY_SIZE(gcc_qcs615_resets),
2970 .gdscs = gcc_qcs615_gdscs,
2971 .num_gdscs = ARRAY_SIZE(gcc_qcs615_gdscs),
2972};
2973
2974static const struct of_device_id gcc_qcs615_match_table[] = {
2975 { .compatible = "qcom,qcs615-gcc" },
2976 { }
2977};
2978MODULE_DEVICE_TABLE(of, gcc_qcs615_match_table);
2979
2980static int gcc_qcs615_probe(struct platform_device *pdev)
2981{
2982 struct regmap *regmap;
2983 int ret;
2984
2985 regmap = qcom_cc_map(pdev, desc: &gcc_qcs615_desc);
2986 if (IS_ERR(ptr: regmap))
2987 return PTR_ERR(ptr: regmap);
2988 /*
2989 * Disable the GPLL0 active input to MM blocks and GPU
2990 * via MISC registers.
2991 */
2992 regmap_update_bits(map: regmap, reg: 0x0b084, BIT(0), BIT(0));
2993 regmap_update_bits(map: regmap, reg: 0x9b000, BIT(0), BIT(0));
2994
2995 /* Keep some clocks always enabled */
2996 qcom_branch_set_clk_en(regmap, cbcr: 0xb008); /* GCC_CAMERA_AHB_CLK */
2997 qcom_branch_set_clk_en(regmap, cbcr: 0xb044); /* GCC_CAMERA_XO_CLK */
2998 qcom_branch_set_clk_en(regmap, cbcr: 0xb00c); /* GCC_DISP_AHB_CLK */
2999 qcom_branch_set_clk_en(regmap, cbcr: 0xb048); /* GCC_DISP_XO_CLK */
3000 qcom_branch_set_clk_en(regmap, cbcr: 0x71004); /* GCC_GPU_CFG_AHB_CLK */
3001 qcom_branch_set_clk_en(regmap, cbcr: 0xb004); /* GCC_VIDEO_AHB_CLK */
3002 qcom_branch_set_clk_en(regmap, cbcr: 0xb040); /* GCC_VIDEO_XO_CLK */
3003 qcom_branch_set_clk_en(regmap, cbcr: 0x480040); /* GCC_CPUSS_GNOC_CLK */
3004
3005 ret = qcom_cc_register_rcg_dfs(regmap, rcgs: gcc_dfs_clocks,
3006 ARRAY_SIZE(gcc_dfs_clocks));
3007 if (ret)
3008 return ret;
3009
3010 return qcom_cc_really_probe(dev: &pdev->dev, desc: &gcc_qcs615_desc, regmap);
3011}
3012
3013static struct platform_driver gcc_qcs615_driver = {
3014 .probe = gcc_qcs615_probe,
3015 .driver = {
3016 .name = "gcc-qcs615",
3017 .of_match_table = gcc_qcs615_match_table,
3018 },
3019};
3020
3021static int __init gcc_qcs615_init(void)
3022{
3023 return platform_driver_register(&gcc_qcs615_driver);
3024}
3025subsys_initcall(gcc_qcs615_init);
3026
3027static void __exit gcc_qcs615_exit(void)
3028{
3029 platform_driver_unregister(&gcc_qcs615_driver);
3030}
3031module_exit(gcc_qcs615_exit);
3032
3033MODULE_DESCRIPTION("QTI GCC QCS615 Driver");
3034MODULE_LICENSE("GPL");
3035

source code of linux/drivers/clk/qcom/gcc-qcs615.c