1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2023 Otto Pflüger
4 *
5 * Based on gcc-msm8953.c:
6 * Copyright 2021, The Linux Foundation. All rights reserved.
7 * with parts taken from gcc-qcs404.c:
8 * Copyright 2018, The Linux Foundation. All rights reserved.
9 * and gcc-msm8939.c:
10 * Copyright 2020 Linaro Limited
11 * adapted with data from clock-gcc-8952.c in Qualcomm's msm-4.9 release:
12 * Copyright (c) 2014-2020, The Linux Foundation. All rights reserved.
13 */
14
15#include <linux/bitops.h>
16#include <linux/clk-provider.h>
17#include <linux/err.h>
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/of.h>
21#include <linux/platform_device.h>
22#include <linux/regmap.h>
23#include <linux/reset-controller.h>
24
25#include <dt-bindings/clock/qcom,gcc-msm8917.h>
26
27#include "clk-alpha-pll.h"
28#include "clk-branch.h"
29#include "clk-pll.h"
30#include "clk-rcg.h"
31#include "common.h"
32#include "gdsc.h"
33#include "reset.h"
34
35enum {
36 DT_XO,
37 DT_SLEEP_CLK,
38 DT_DSI0PLL,
39 DT_DSI0PLL_BYTE,
40 DT_DSI1PLL,
41 DT_DSI1PLL_BYTE,
42};
43
44enum {
45 P_XO,
46 P_SLEEP_CLK,
47 P_GPLL0,
48 P_GPLL3,
49 P_GPLL4,
50 P_GPLL6,
51 P_DSI0PLL,
52 P_DSI0PLL_BYTE,
53 P_DSI1PLL,
54 P_DSI1PLL_BYTE,
55};
56
57static struct clk_alpha_pll gpll0_sleep_clk_src = {
58 .offset = 0x21000,
59 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
60 .clkr = {
61 .enable_reg = 0x45008,
62 .enable_mask = BIT(23),
63 .enable_is_inverted = true,
64 .hw.init = &(struct clk_init_data){
65 .name = "gpll0_sleep_clk_src",
66 .parent_data = &(const struct clk_parent_data) {
67 .index = DT_XO,
68 },
69 .num_parents = 1,
70 .ops = &clk_branch_simple_ops,
71 },
72 },
73};
74
75static struct clk_alpha_pll gpll0_early = {
76 .offset = 0x21000,
77 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
78 .clkr = {
79 .enable_reg = 0x45000,
80 .enable_mask = BIT(0),
81 .hw.init = &(struct clk_init_data) {
82 .name = "gpll0_early",
83 .parent_hws = (const struct clk_hw*[]){
84 &gpll0_sleep_clk_src.clkr.hw,
85 },
86 .num_parents = 1,
87 .ops = &clk_alpha_pll_fixed_ops,
88 },
89 },
90};
91
92static struct clk_alpha_pll_postdiv gpll0 = {
93 .offset = 0x21000,
94 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
95 .clkr.hw.init = &(struct clk_init_data){
96 .name = "gpll0",
97 .parent_hws = (const struct clk_hw*[]){
98 &gpll0_early.clkr.hw,
99 },
100 .num_parents = 1,
101 .ops = &clk_alpha_pll_postdiv_ro_ops,
102 },
103};
104
105static const struct pll_vco gpll3_p_vco[] = {
106 { 700000000, 1400000000, 0 },
107};
108
109static const struct pll_vco gpll3_p_vco_msm8937[] = {
110 { 525000000, 1066000000, 0 },
111};
112
113static struct alpha_pll_config gpll3_early_config = {
114 .l = 63,
115 .config_ctl_val = 0x4001055b,
116 .early_output_mask = 0,
117 .post_div_mask = GENMASK(11, 8),
118 .post_div_val = BIT(8),
119};
120
121static struct clk_alpha_pll gpll3_early = {
122 .offset = 0x22000,
123 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
124 .vco_table = gpll3_p_vco,
125 .num_vco = ARRAY_SIZE(gpll3_p_vco),
126 .flags = SUPPORTS_DYNAMIC_UPDATE,
127 .clkr = {
128 .hw.init = &(struct clk_init_data){
129 .name = "gpll3_early",
130 .parent_data = &(const struct clk_parent_data) {
131 .index = DT_XO,
132 },
133 .num_parents = 1,
134 .ops = &clk_alpha_pll_ops,
135 },
136 },
137};
138
139static struct clk_alpha_pll_postdiv gpll3 = {
140 .offset = 0x22000,
141 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
142 .clkr.hw.init = &(struct clk_init_data){
143 .name = "gpll3",
144 .parent_hws = (const struct clk_hw*[]){
145 &gpll3_early.clkr.hw,
146 },
147 .num_parents = 1,
148 .ops = &clk_alpha_pll_postdiv_ops,
149 .flags = CLK_SET_RATE_PARENT,
150 },
151};
152
153static struct clk_alpha_pll gpll4_early = {
154 .offset = 0x24000,
155 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
156 .clkr = {
157 .enable_reg = 0x45000,
158 .enable_mask = BIT(5),
159 .hw.init = &(struct clk_init_data){
160 .name = "gpll4_early",
161 .parent_data = &(const struct clk_parent_data) {
162 .index = DT_XO,
163 },
164 .num_parents = 1,
165 .ops = &clk_alpha_pll_fixed_ops,
166 },
167 },
168};
169
170static struct clk_alpha_pll_postdiv gpll4 = {
171 .offset = 0x24000,
172 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
173 .clkr.hw.init = &(struct clk_init_data){
174 .name = "gpll4",
175 .parent_hws = (const struct clk_hw*[]){
176 &gpll4_early.clkr.hw,
177 },
178 .num_parents = 1,
179 .ops = &clk_alpha_pll_postdiv_ro_ops,
180 },
181};
182
183static struct clk_pll gpll6_early = {
184 .l_reg = 0x37004,
185 .m_reg = 0x37008,
186 .n_reg = 0x3700c,
187 .config_reg = 0x37014,
188 .mode_reg = 0x37000,
189 .status_reg = 0x3701c,
190 .status_bit = 17,
191 .clkr.hw.init = &(struct clk_init_data){
192 .name = "gpll6_early",
193 .parent_data = &(const struct clk_parent_data) {
194 .index = DT_XO,
195 },
196 .num_parents = 1,
197 .ops = &clk_pll_ops,
198 },
199};
200
201static struct clk_regmap gpll6 = {
202 .enable_reg = 0x45000,
203 .enable_mask = BIT(7),
204 .hw.init = &(struct clk_init_data){
205 .name = "gpll6",
206 .parent_hws = (const struct clk_hw*[]){
207 &gpll6_early.clkr.hw,
208 },
209 .num_parents = 1,
210 .ops = &clk_pll_vote_ops,
211 },
212};
213
214static const struct parent_map gcc_xo_gpll0_map[] = {
215 { P_XO, 0 },
216 { P_GPLL0, 1 },
217};
218
219static const struct parent_map gcc_xo_gpll0_out_aux_map[] = {
220 { P_XO, 0 },
221 { P_GPLL0, 2 },
222};
223
224static const struct clk_parent_data gcc_xo_gpll0_data[] = {
225 { .index = DT_XO },
226 { .hw = &gpll0.clkr.hw },
227};
228
229static const struct parent_map gcc_xo_gpll0_gpll6_sleep_map[] = {
230 { P_XO, 0 },
231 { P_GPLL0, 1 },
232 { P_GPLL6, 2 },
233 { P_SLEEP_CLK, 6 },
234};
235
236static const struct clk_parent_data gcc_xo_gpll0_gpll6_sleep_data[] = {
237 { .index = DT_XO },
238 { .hw = &gpll0.clkr.hw },
239 { .hw = &gpll6.hw },
240 { .index = DT_SLEEP_CLK },
241};
242
243static const struct parent_map gcc_xo_gpll0_gpll6_gpll4_map[] = {
244 { P_XO, 0 },
245 { P_GPLL0, 1 },
246 { P_GPLL6, 2 },
247 { P_GPLL4, 3 },
248};
249
250static const struct clk_parent_data gcc_xo_gpll0_gpll6_gpll4_data[] = {
251 { .index = DT_XO },
252 { .hw = &gpll0.clkr.hw },
253 { .hw = &gpll6.hw },
254 { .hw = &gpll4.clkr.hw },
255};
256
257static const struct freq_tbl ftbl_apss_ahb_clk_src[] = {
258 F(19200000, P_XO, 1, 0, 0),
259 F(50000000, P_GPLL0, 16, 0, 0),
260 F(100000000, P_GPLL0, 8, 0, 0),
261 F(133330000, P_GPLL0, 6, 0, 0),
262 { }
263};
264
265static struct clk_rcg2 apss_ahb_clk_src = {
266 .cmd_rcgr = 0x46000,
267 .hid_width = 5,
268 .freq_tbl = ftbl_apss_ahb_clk_src,
269 .parent_map = gcc_xo_gpll0_map,
270 .clkr.hw.init = &(struct clk_init_data) {
271 .name = "apss_ahb_clk_src",
272 .parent_data = gcc_xo_gpll0_data,
273 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
274 .ops = &clk_rcg2_ops,
275 }
276};
277
278static const struct freq_tbl ftbl_blsp_i2c_apps_clk_src[] = {
279 F(19200000, P_XO, 1, 0, 0),
280 F(50000000, P_GPLL0, 16, 0, 0),
281 { }
282};
283
284static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
285 .cmd_rcgr = 0x0200c,
286 .hid_width = 5,
287 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
288 .parent_map = gcc_xo_gpll0_map,
289 .clkr.hw.init = &(struct clk_init_data){
290 .name = "blsp1_qup1_i2c_apps_clk_src",
291 .parent_data = gcc_xo_gpll0_data,
292 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
293 .ops = &clk_rcg2_ops,
294 },
295};
296
297static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
298 .cmd_rcgr = 0x03000,
299 .hid_width = 5,
300 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
301 .parent_map = gcc_xo_gpll0_map,
302 .clkr.hw.init = &(struct clk_init_data) {
303 .name = "blsp1_qup2_i2c_apps_clk_src",
304 .parent_data = gcc_xo_gpll0_data,
305 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
306 .ops = &clk_rcg2_ops,
307 }
308};
309
310static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
311 .cmd_rcgr = 0x04000,
312 .hid_width = 5,
313 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
314 .parent_map = gcc_xo_gpll0_map,
315 .clkr.hw.init = &(struct clk_init_data) {
316 .name = "blsp1_qup3_i2c_apps_clk_src",
317 .parent_data = gcc_xo_gpll0_data,
318 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
319 .ops = &clk_rcg2_ops,
320 }
321};
322
323static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
324 .cmd_rcgr = 0x05000,
325 .hid_width = 5,
326 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
327 .parent_map = gcc_xo_gpll0_map,
328 .clkr.hw.init = &(struct clk_init_data) {
329 .name = "blsp1_qup4_i2c_apps_clk_src",
330 .parent_data = gcc_xo_gpll0_data,
331 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
332 .ops = &clk_rcg2_ops,
333 }
334};
335
336static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
337 .cmd_rcgr = 0x0c00c,
338 .hid_width = 5,
339 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
340 .parent_map = gcc_xo_gpll0_map,
341 .clkr.hw.init = &(struct clk_init_data) {
342 .name = "blsp2_qup1_i2c_apps_clk_src",
343 .parent_data = gcc_xo_gpll0_data,
344 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
345 .ops = &clk_rcg2_ops,
346 }
347};
348
349static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
350 .cmd_rcgr = 0x0d000,
351 .hid_width = 5,
352 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
353 .parent_map = gcc_xo_gpll0_map,
354 .clkr.hw.init = &(struct clk_init_data) {
355 .name = "blsp2_qup2_i2c_apps_clk_src",
356 .parent_data = gcc_xo_gpll0_data,
357 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
358 .ops = &clk_rcg2_ops,
359 }
360};
361
362static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
363 .cmd_rcgr = 0x0f000,
364 .hid_width = 5,
365 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
366 .parent_map = gcc_xo_gpll0_map,
367 .clkr.hw.init = &(struct clk_init_data) {
368 .name = "blsp2_qup3_i2c_apps_clk_src",
369 .parent_data = gcc_xo_gpll0_data,
370 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
371 .ops = &clk_rcg2_ops,
372 }
373};
374
375static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
376 .cmd_rcgr = 0x18000,
377 .hid_width = 5,
378 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
379 .parent_map = gcc_xo_gpll0_map,
380 .clkr.hw.init = &(struct clk_init_data){
381 .name = "blsp2_qup4_i2c_apps_clk_src",
382 .parent_data = gcc_xo_gpll0_data,
383 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
384 .ops = &clk_rcg2_ops,
385 },
386};
387
388static const struct freq_tbl ftbl_blsp_spi_apps_clk_src[] = {
389 F(960000, P_XO, 10, 1, 2),
390 F(4800000, P_XO, 4, 0, 0),
391 F(9600000, P_XO, 2, 0, 0),
392 F(16000000, P_GPLL0, 10, 1, 5),
393 F(19200000, P_XO, 1, 0, 0),
394 F(25000000, P_GPLL0, 16, 1, 2),
395 F(50000000, P_GPLL0, 16, 0, 0),
396 { }
397};
398
399static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
400 .cmd_rcgr = 0x02024,
401 .mnd_width = 8,
402 .hid_width = 5,
403 .freq_tbl = ftbl_blsp_spi_apps_clk_src,
404 .parent_map = gcc_xo_gpll0_map,
405 .clkr.hw.init = &(struct clk_init_data){
406 .name = "blsp1_qup1_spi_apps_clk_src",
407 .parent_data = gcc_xo_gpll0_data,
408 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
409 .ops = &clk_rcg2_ops,
410 },
411};
412
413static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
414 .cmd_rcgr = 0x03014,
415 .hid_width = 5,
416 .mnd_width = 8,
417 .freq_tbl = ftbl_blsp_spi_apps_clk_src,
418 .parent_map = gcc_xo_gpll0_map,
419 .clkr.hw.init = &(struct clk_init_data) {
420 .name = "blsp1_qup2_spi_apps_clk_src",
421 .parent_data = gcc_xo_gpll0_data,
422 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
423 .ops = &clk_rcg2_ops,
424 }
425};
426
427static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
428 .cmd_rcgr = 0x04024,
429 .hid_width = 5,
430 .mnd_width = 8,
431 .freq_tbl = ftbl_blsp_spi_apps_clk_src,
432 .parent_map = gcc_xo_gpll0_map,
433 .clkr.hw.init = &(struct clk_init_data) {
434 .name = "blsp1_qup3_spi_apps_clk_src",
435 .parent_data = gcc_xo_gpll0_data,
436 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
437 .ops = &clk_rcg2_ops,
438 }
439};
440
441static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
442 .cmd_rcgr = 0x05024,
443 .hid_width = 5,
444 .mnd_width = 8,
445 .freq_tbl = ftbl_blsp_spi_apps_clk_src,
446 .parent_map = gcc_xo_gpll0_map,
447 .clkr.hw.init = &(struct clk_init_data) {
448 .name = "blsp1_qup4_spi_apps_clk_src",
449 .parent_data = gcc_xo_gpll0_data,
450 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
451 .ops = &clk_rcg2_ops,
452 }
453};
454
455static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
456 .cmd_rcgr = 0x0c024,
457 .hid_width = 5,
458 .mnd_width = 8,
459 .freq_tbl = ftbl_blsp_spi_apps_clk_src,
460 .parent_map = gcc_xo_gpll0_map,
461 .clkr.hw.init = &(struct clk_init_data) {
462 .name = "blsp2_qup1_spi_apps_clk_src",
463 .parent_data = gcc_xo_gpll0_data,
464 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
465 .ops = &clk_rcg2_ops,
466 }
467};
468
469static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
470 .cmd_rcgr = 0x0d014,
471 .hid_width = 5,
472 .mnd_width = 8,
473 .freq_tbl = ftbl_blsp_spi_apps_clk_src,
474 .parent_map = gcc_xo_gpll0_map,
475 .clkr.hw.init = &(struct clk_init_data) {
476 .name = "blsp2_qup2_spi_apps_clk_src",
477 .parent_data = gcc_xo_gpll0_data,
478 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
479 .ops = &clk_rcg2_ops,
480 }
481};
482
483static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
484 .cmd_rcgr = 0x0f024,
485 .hid_width = 5,
486 .mnd_width = 8,
487 .freq_tbl = ftbl_blsp_spi_apps_clk_src,
488 .parent_map = gcc_xo_gpll0_map,
489 .clkr.hw.init = &(struct clk_init_data) {
490 .name = "blsp2_qup3_spi_apps_clk_src",
491 .parent_data = gcc_xo_gpll0_data,
492 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
493 .ops = &clk_rcg2_ops,
494 }
495};
496
497static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
498 .cmd_rcgr = 0x18024,
499 .mnd_width = 8,
500 .hid_width = 5,
501 .freq_tbl = ftbl_blsp_spi_apps_clk_src,
502 .parent_map = gcc_xo_gpll0_map,
503 .clkr.hw.init = &(struct clk_init_data){
504 .name = "blsp2_qup4_spi_apps_clk_src",
505 .parent_data = gcc_xo_gpll0_data,
506 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
507 .ops = &clk_rcg2_ops,
508 },
509};
510
511static const struct freq_tbl ftbl_blsp_uart_apps_clk_src[] = {
512 F(3686400, P_GPLL0, 1, 72, 15625),
513 F(7372800, P_GPLL0, 1, 144, 15625),
514 F(14745600, P_GPLL0, 1, 288, 15625),
515 F(16000000, P_GPLL0, 10, 1, 5),
516 F(19200000, P_XO, 1, 0, 0),
517 F(24000000, P_GPLL0, 1, 3, 100),
518 F(25000000, P_GPLL0, 16, 1, 2),
519 F(32000000, P_GPLL0, 1, 1, 25),
520 F(40000000, P_GPLL0, 1, 1, 20),
521 F(46400000, P_GPLL0, 1, 29, 500),
522 F(48000000, P_GPLL0, 1, 3, 50),
523 F(51200000, P_GPLL0, 1, 8, 125),
524 F(56000000, P_GPLL0, 1, 7, 100),
525 F(58982400, P_GPLL0, 1, 1152, 15625),
526 F(60000000, P_GPLL0, 1, 3, 40),
527 F(64000000, P_GPLL0, 1, 2, 25),
528 { }
529};
530
531static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
532 .cmd_rcgr = 0x02044,
533 .hid_width = 5,
534 .mnd_width = 16,
535 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
536 .parent_map = gcc_xo_gpll0_map,
537 .clkr.hw.init = &(struct clk_init_data) {
538 .name = "blsp1_uart1_apps_clk_src",
539 .parent_data = gcc_xo_gpll0_data,
540 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
541 .ops = &clk_rcg2_ops,
542 }
543};
544
545static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
546 .cmd_rcgr = 0x03034,
547 .hid_width = 5,
548 .mnd_width = 16,
549 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
550 .parent_map = gcc_xo_gpll0_map,
551 .clkr.hw.init = &(struct clk_init_data) {
552 .name = "blsp1_uart2_apps_clk_src",
553 .parent_data = gcc_xo_gpll0_data,
554 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
555 .ops = &clk_rcg2_ops,
556 }
557};
558
559static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
560 .cmd_rcgr = 0x0c044,
561 .hid_width = 5,
562 .mnd_width = 16,
563 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
564 .parent_map = gcc_xo_gpll0_map,
565 .clkr.hw.init = &(struct clk_init_data) {
566 .name = "blsp2_uart1_apps_clk_src",
567 .parent_data = gcc_xo_gpll0_data,
568 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
569 .ops = &clk_rcg2_ops,
570 }
571};
572
573static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
574 .cmd_rcgr = 0x0d034,
575 .hid_width = 5,
576 .mnd_width = 16,
577 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
578 .parent_map = gcc_xo_gpll0_map,
579 .clkr.hw.init = &(struct clk_init_data) {
580 .name = "blsp2_uart2_apps_clk_src",
581 .parent_data = gcc_xo_gpll0_data,
582 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
583 .ops = &clk_rcg2_ops,
584 }
585};
586
587static const struct parent_map gcc_byte0_map[] = {
588 { P_XO, 0 },
589 { P_DSI0PLL_BYTE, 1 },
590 { P_DSI1PLL_BYTE, 3 },
591};
592
593static const struct parent_map gcc_byte1_map[] = {
594 { P_XO, 0 },
595 { P_DSI0PLL_BYTE, 3 },
596 { P_DSI1PLL_BYTE, 1 },
597};
598
599static const struct clk_parent_data gcc_byte_data[] = {
600 { .index = DT_XO },
601 { .index = DT_DSI0PLL_BYTE },
602 { .index = DT_DSI1PLL_BYTE },
603};
604
605static struct clk_rcg2 byte0_clk_src = {
606 .cmd_rcgr = 0x4d044,
607 .hid_width = 5,
608 .parent_map = gcc_byte0_map,
609 .clkr.hw.init = &(struct clk_init_data) {
610 .name = "byte0_clk_src",
611 .parent_data = gcc_byte_data,
612 .num_parents = ARRAY_SIZE(gcc_byte_data),
613 .ops = &clk_byte2_ops,
614 .flags = CLK_SET_RATE_PARENT,
615 }
616};
617
618static struct clk_rcg2 byte1_clk_src = {
619 .cmd_rcgr = 0x4d0b0,
620 .hid_width = 5,
621 .parent_map = gcc_byte1_map,
622 .clkr.hw.init = &(struct clk_init_data){
623 .name = "byte1_clk_src",
624 .parent_data = gcc_byte_data,
625 .num_parents = ARRAY_SIZE(gcc_byte_data),
626 .ops = &clk_byte2_ops,
627 .flags = CLK_SET_RATE_PARENT,
628 },
629};
630
631static const struct freq_tbl ftbl_camss_gp_clk_src[] = {
632 F(100000000, P_GPLL0, 8, 0, 0),
633 F(160000000, P_GPLL0, 5, 0, 0),
634 F(200000000, P_GPLL0, 4, 0, 0),
635 { }
636};
637
638static struct clk_rcg2 camss_gp0_clk_src = {
639 .cmd_rcgr = 0x54000,
640 .hid_width = 5,
641 .mnd_width = 8,
642 .freq_tbl = ftbl_camss_gp_clk_src,
643 .parent_map = gcc_xo_gpll0_gpll6_sleep_map,
644 .clkr.hw.init = &(struct clk_init_data) {
645 .name = "camss_gp0_clk_src",
646 .parent_data = gcc_xo_gpll0_gpll6_sleep_data,
647 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_sleep_data),
648 .ops = &clk_rcg2_ops,
649 }
650};
651
652static struct clk_rcg2 camss_gp1_clk_src = {
653 .cmd_rcgr = 0x55000,
654 .hid_width = 5,
655 .mnd_width = 8,
656 .freq_tbl = ftbl_camss_gp_clk_src,
657 .parent_map = gcc_xo_gpll0_gpll6_sleep_map,
658 .clkr.hw.init = &(struct clk_init_data) {
659 .name = "camss_gp1_clk_src",
660 .parent_data = gcc_xo_gpll0_gpll6_sleep_data,
661 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_sleep_data),
662 .ops = &clk_rcg2_ops,
663 }
664};
665
666static const struct freq_tbl ftbl_camss_top_ahb_clk_src[] = {
667 F(40000000, P_GPLL0, 10, 1, 2),
668 F(61540000, P_GPLL0, 13, 0, 0),
669 F(80000000, P_GPLL0, 10, 0, 0),
670 { }
671};
672
673static struct clk_rcg2 camss_top_ahb_clk_src = {
674 .cmd_rcgr = 0x5a000,
675 .hid_width = 5,
676 .freq_tbl = ftbl_camss_top_ahb_clk_src,
677 .parent_map = gcc_xo_gpll0_map,
678 .clkr.hw.init = &(struct clk_init_data) {
679 .name = "camss_top_ahb_clk_src",
680 .parent_data = gcc_xo_gpll0_data,
681 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
682 .ops = &clk_rcg2_ops,
683 }
684};
685
686static const struct freq_tbl ftbl_cci_clk_src[] = {
687 F(19200000, P_XO, 1, 0, 0),
688 F(37500000, P_GPLL0, 1, 3, 64),
689 { }
690};
691
692static struct clk_rcg2 cci_clk_src = {
693 .cmd_rcgr = 0x51000,
694 .hid_width = 5,
695 .mnd_width = 8,
696 .freq_tbl = ftbl_cci_clk_src,
697 .parent_map = gcc_xo_gpll0_out_aux_map,
698 .clkr.hw.init = &(struct clk_init_data) {
699 .name = "cci_clk_src",
700 .parent_data = gcc_xo_gpll0_data,
701 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
702 .ops = &clk_rcg2_ops,
703 }
704};
705
706static const struct parent_map gcc_cpp_map[] = {
707 { P_XO, 0 },
708 { P_GPLL0, 1 },
709 { P_GPLL6, 3 },
710};
711
712static const struct clk_parent_data gcc_cpp_data[] = {
713 { .index = DT_XO },
714 { .hw = &gpll0.clkr.hw },
715 { .hw = &gpll6.hw },
716};
717
718static const struct freq_tbl ftbl_cpp_clk_src[] = {
719 F(133330000, P_GPLL0, 6, 0, 0),
720 F(160000000, P_GPLL0, 5, 0, 0),
721 F(266670000, P_GPLL0, 3, 0, 0),
722 F(308570000, P_GPLL0, 3.5, 0, 0),
723 F(320000000, P_GPLL0, 2.5, 0, 0),
724 F(360000000, P_GPLL6, 3, 0, 0),
725 { }
726};
727
728static const struct freq_tbl ftbl_cpp_clk_src_msm8937[] = {
729 F(133330000, P_GPLL0, 6, 0, 0),
730 F(160000000, P_GPLL0, 5, 0, 0),
731 F(200000000, P_GPLL0, 5, 0, 0),
732 F(266666667, P_GPLL0, 3, 0, 0),
733 F(308570000, P_GPLL6, 3.5, 0, 0),
734 F(320000000, P_GPLL0, 2.5, 0, 0),
735 F(360000000, P_GPLL6, 3, 0, 0),
736 { }
737};
738
739static struct clk_rcg2 cpp_clk_src = {
740 .cmd_rcgr = 0x58018,
741 .hid_width = 5,
742 .freq_tbl = ftbl_cpp_clk_src,
743 .parent_map = gcc_cpp_map,
744 .clkr.hw.init = &(struct clk_init_data) {
745 .name = "cpp_clk_src",
746 .parent_data = gcc_cpp_data,
747 .num_parents = ARRAY_SIZE(gcc_cpp_data),
748 .ops = &clk_rcg2_ops,
749 }
750};
751
752static struct clk_init_data vcodec0_clk_src_init_msm8937 = {
753 .name = "vcodec0_clk_src",
754 .parent_data = gcc_cpp_data,
755 .num_parents = ARRAY_SIZE(gcc_cpp_data),
756 .ops = &clk_rcg2_ops,
757};
758
759static const struct freq_tbl ftbl_crypto_clk_src[] = {
760 F(50000000, P_GPLL0, 16, 0, 0),
761 F(80000000, P_GPLL0, 10, 0, 0),
762 F(100000000, P_GPLL0, 8, 0, 0),
763 F(160000000, P_GPLL0, 5, 0, 0),
764 { }
765};
766
767static struct clk_rcg2 crypto_clk_src = {
768 .cmd_rcgr = 0x16004,
769 .hid_width = 5,
770 .freq_tbl = ftbl_crypto_clk_src,
771 .parent_map = gcc_xo_gpll0_map,
772 .clkr.hw.init = &(struct clk_init_data) {
773 .name = "crypto_clk_src",
774 .parent_data = gcc_xo_gpll0_data,
775 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
776 .ops = &clk_rcg2_ops,
777 }
778};
779
780static const struct freq_tbl ftbl_csi_clk_src[] = {
781 F(100000000, P_GPLL0, 8, 0, 0),
782 F(160000000, P_GPLL0, 5, 0, 0),
783 F(200000000, P_GPLL0, 4, 0, 0),
784 { }
785};
786
787static struct clk_rcg2 csi0_clk_src = {
788 .cmd_rcgr = 0x4e020,
789 .hid_width = 5,
790 .freq_tbl = ftbl_csi_clk_src,
791 .parent_map = gcc_xo_gpll0_map,
792 .clkr.hw.init = &(struct clk_init_data) {
793 .name = "csi0_clk_src",
794 .parent_data = gcc_xo_gpll0_data,
795 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
796 .ops = &clk_rcg2_ops,
797 }
798};
799
800static struct clk_rcg2 csi1_clk_src = {
801 .cmd_rcgr = 0x4f020,
802 .hid_width = 5,
803 .freq_tbl = ftbl_csi_clk_src,
804 .parent_map = gcc_xo_gpll0_map,
805 .clkr.hw.init = &(struct clk_init_data) {
806 .name = "csi1_clk_src",
807 .parent_data = gcc_xo_gpll0_data,
808 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
809 .ops = &clk_rcg2_ops,
810 }
811};
812
813static struct clk_rcg2 csi2_clk_src = {
814 .cmd_rcgr = 0x3c020,
815 .hid_width = 5,
816 .freq_tbl = ftbl_csi_clk_src,
817 .parent_map = gcc_xo_gpll0_map,
818 .clkr.hw.init = &(struct clk_init_data) {
819 .name = "csi2_clk_src",
820 .parent_data = gcc_xo_gpll0_data,
821 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
822 .ops = &clk_rcg2_ops,
823 }
824};
825
826static const struct freq_tbl ftbl_csi_phytimer_clk_src[] = {
827 F(100000000, P_GPLL0, 8, 0, 0),
828 F(160000000, P_GPLL0, 5, 0, 0),
829 F(200000000, P_GPLL0, 4, 0, 0),
830 F(266670000, P_GPLL0, 3, 0, 0),
831 { }
832};
833
834static const struct freq_tbl ftbl_csi_phytimer_clk_src_msm8937[] = {
835 F(100000000, P_GPLL0, 8, 0, 0),
836 F(160000000, P_GPLL0, 5, 0, 0),
837 F(200000000, P_GPLL0, 4, 0, 0),
838 { }
839};
840
841static struct clk_rcg2 csi0phytimer_clk_src = {
842 .cmd_rcgr = 0x4e000,
843 .hid_width = 5,
844 .freq_tbl = ftbl_csi_phytimer_clk_src,
845 .parent_map = gcc_xo_gpll0_map,
846 .clkr.hw.init = &(struct clk_init_data) {
847 .name = "csi0phytimer_clk_src",
848 .parent_data = gcc_xo_gpll0_data,
849 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
850 .ops = &clk_rcg2_ops,
851 }
852};
853
854static struct clk_rcg2 csi1phytimer_clk_src = {
855 .cmd_rcgr = 0x4f000,
856 .hid_width = 5,
857 .freq_tbl = ftbl_csi_phytimer_clk_src,
858 .parent_map = gcc_xo_gpll0_map,
859 .clkr.hw.init = &(struct clk_init_data) {
860 .name = "csi1phytimer_clk_src",
861 .parent_data = gcc_xo_gpll0_data,
862 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
863 .ops = &clk_rcg2_ops,
864 }
865};
866
867static const struct freq_tbl ftbl_esc0_1_clk_src[] = {
868 F(19200000, P_XO, 1, 0, 0),
869 { }
870};
871
872static struct clk_rcg2 esc0_clk_src = {
873 .cmd_rcgr = 0x4d05c,
874 .hid_width = 5,
875 .freq_tbl = ftbl_esc0_1_clk_src,
876 .parent_map = gcc_xo_gpll0_out_aux_map,
877 .clkr.hw.init = &(struct clk_init_data) {
878 .name = "esc0_clk_src",
879 .parent_data = gcc_xo_gpll0_data,
880 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
881 .ops = &clk_rcg2_ops,
882 }
883};
884
885static struct clk_rcg2 esc1_clk_src = {
886 .cmd_rcgr = 0x4d0a8,
887 .hid_width = 5,
888 .freq_tbl = ftbl_esc0_1_clk_src,
889 .parent_map = gcc_xo_gpll0_out_aux_map,
890 .clkr.hw.init = &(struct clk_init_data){
891 .name = "esc1_clk_src",
892 .parent_data = gcc_xo_gpll0_data,
893 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
894 .ops = &clk_rcg2_ops,
895 },
896};
897
898static const struct parent_map gcc_gfx3d_map[] = {
899 { P_XO, 0 },
900 { P_GPLL0, 1 },
901 { P_GPLL3, 2 },
902 { P_GPLL6, 3 },
903};
904
905static const struct parent_map gcc_gfx3d_map_qm215[] = {
906 { P_XO, 0 },
907 { P_GPLL0, 5 },
908 { P_GPLL3, 2 },
909 { P_GPLL6, 6 },
910};
911
912static const struct clk_parent_data gcc_gfx3d_data[] = {
913 { .index = DT_XO },
914 { .hw = &gpll0.clkr.hw },
915 { .hw = &gpll3.clkr.hw },
916 { .hw = &gpll6.hw },
917};
918
919static const struct freq_tbl ftbl_gfx3d_clk_src[] = {
920 F(19200000, P_XO, 1, 0, 0),
921 F(50000000, P_GPLL0, 16, 0, 0),
922 F(80000000, P_GPLL0, 10, 0, 0),
923 F(100000000, P_GPLL0, 8, 0, 0),
924 F(160000000, P_GPLL0, 5, 0, 0),
925 F(200000000, P_GPLL0, 4, 0, 0),
926 F(228570000, P_GPLL0, 3.5, 0, 0),
927 F(240000000, P_GPLL6, 4.5, 0, 0),
928 F(266670000, P_GPLL0, 3, 0, 0),
929 F(270000000, P_GPLL6, 4, 0, 0),
930 F(320000000, P_GPLL0, 2.5, 0, 0),
931 F(400000000, P_GPLL0, 2, 0, 0),
932 F(465000000, P_GPLL3, 1, 0, 0),
933 F(484800000, P_GPLL3, 1, 0, 0),
934 F(500000000, P_GPLL3, 1, 0, 0),
935 F(523200000, P_GPLL3, 1, 0, 0),
936 F(550000000, P_GPLL3, 1, 0, 0),
937 F(598000000, P_GPLL3, 1, 0, 0),
938 { }
939};
940
941static const struct freq_tbl ftbl_gfx3d_clk_src_msm8937[] = {
942 F(19200000, P_XO, 1, 0, 0),
943 F(50000000, P_GPLL0, 16, 0, 0),
944 F(80000000, P_GPLL0, 10, 0, 0),
945 F(100000000, P_GPLL0, 8, 0, 0),
946 F(160000000, P_GPLL0, 5, 0, 0),
947 F(200000000, P_GPLL0, 4, 0, 0),
948 F(216000000, P_GPLL6, 5, 0, 0),
949 F(228570000, P_GPLL0, 3.5, 0, 0),
950 F(240000000, P_GPLL6, 4.5, 0, 0),
951 F(266670000, P_GPLL0, 3, 0, 0),
952 F(300000000, P_GPLL3, 1, 0, 0),
953 F(320000000, P_GPLL0, 2.5, 0, 0),
954 F(375000000, P_GPLL3, 1, 0, 0),
955 F(400000000, P_GPLL0, 2, 0, 0),
956 F(450000000, P_GPLL3, 1, 0, 0),
957 { }
958};
959
960static struct clk_rcg2 gfx3d_clk_src = {
961 .cmd_rcgr = 0x59000,
962 .hid_width = 5,
963 .freq_tbl = ftbl_gfx3d_clk_src,
964 .parent_map = gcc_gfx3d_map,
965 .clkr.hw.init = &(struct clk_init_data) {
966 .name = "gfx3d_clk_src",
967 .parent_data = gcc_gfx3d_data,
968 .num_parents = ARRAY_SIZE(gcc_gfx3d_data),
969 .ops = &clk_rcg2_ops,
970 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
971 }
972};
973
974static const struct freq_tbl ftbl_gp_clk_src[] = {
975 F(19200000, P_XO, 1, 0, 0),
976 { }
977};
978
979static struct clk_rcg2 gp1_clk_src = {
980 .cmd_rcgr = 0x08004,
981 .hid_width = 5,
982 .mnd_width = 8,
983 .freq_tbl = ftbl_gp_clk_src,
984 .parent_map = gcc_xo_gpll0_gpll6_sleep_map,
985 .clkr.hw.init = &(struct clk_init_data) {
986 .name = "gp1_clk_src",
987 .parent_data = gcc_xo_gpll0_gpll6_sleep_data,
988 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_sleep_data),
989 .ops = &clk_rcg2_ops,
990 }
991};
992
993static struct clk_rcg2 gp2_clk_src = {
994 .cmd_rcgr = 0x09004,
995 .hid_width = 5,
996 .mnd_width = 8,
997 .freq_tbl = ftbl_gp_clk_src,
998 .parent_map = gcc_xo_gpll0_gpll6_sleep_map,
999 .clkr.hw.init = &(struct clk_init_data) {
1000 .name = "gp2_clk_src",
1001 .parent_data = gcc_xo_gpll0_gpll6_sleep_data,
1002 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_sleep_data),
1003 .ops = &clk_rcg2_ops,
1004 }
1005};
1006
1007static struct clk_rcg2 gp3_clk_src = {
1008 .cmd_rcgr = 0x0a004,
1009 .hid_width = 5,
1010 .mnd_width = 8,
1011 .freq_tbl = ftbl_gp_clk_src,
1012 .parent_map = gcc_xo_gpll0_gpll6_sleep_map,
1013 .clkr.hw.init = &(struct clk_init_data) {
1014 .name = "gp3_clk_src",
1015 .parent_data = gcc_xo_gpll0_gpll6_sleep_data,
1016 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_sleep_data),
1017 .ops = &clk_rcg2_ops,
1018 }
1019};
1020
1021static const struct freq_tbl ftbl_jpeg0_clk_src[] = {
1022 F(133330000, P_GPLL0, 6, 0, 0),
1023 F(266670000, P_GPLL0, 3, 0, 0),
1024 F(320000000, P_GPLL0, 2.5, 0, 0),
1025 { }
1026};
1027
1028static struct clk_rcg2 jpeg0_clk_src = {
1029 .cmd_rcgr = 0x57000,
1030 .hid_width = 5,
1031 .freq_tbl = ftbl_jpeg0_clk_src,
1032 .parent_map = gcc_xo_gpll0_map,
1033 .clkr.hw.init = &(struct clk_init_data) {
1034 .name = "jpeg0_clk_src",
1035 .parent_data = gcc_xo_gpll0_data,
1036 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
1037 .ops = &clk_rcg2_ops,
1038 }
1039};
1040
1041static const struct freq_tbl ftbl_mclk_clk_src[] = {
1042 F(19200000, P_XO, 1, 0, 0),
1043 F(24000000, P_GPLL6, 1, 1, 45),
1044 F(66667000, P_GPLL0, 12, 0, 0),
1045 { }
1046};
1047
1048static struct clk_rcg2 mclk0_clk_src = {
1049 .cmd_rcgr = 0x52000,
1050 .hid_width = 5,
1051 .mnd_width = 8,
1052 .freq_tbl = ftbl_mclk_clk_src,
1053 .parent_map = gcc_xo_gpll0_gpll6_sleep_map,
1054 .clkr.hw.init = &(struct clk_init_data) {
1055 .name = "mclk0_clk_src",
1056 .parent_data = gcc_xo_gpll0_gpll6_sleep_data,
1057 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_sleep_data),
1058 .ops = &clk_rcg2_ops,
1059 }
1060};
1061
1062static struct clk_rcg2 mclk1_clk_src = {
1063 .cmd_rcgr = 0x53000,
1064 .hid_width = 5,
1065 .mnd_width = 8,
1066 .freq_tbl = ftbl_mclk_clk_src,
1067 .parent_map = gcc_xo_gpll0_gpll6_sleep_map,
1068 .clkr.hw.init = &(struct clk_init_data) {
1069 .name = "mclk1_clk_src",
1070 .parent_data = gcc_xo_gpll0_gpll6_sleep_data,
1071 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_sleep_data),
1072 .ops = &clk_rcg2_ops,
1073 }
1074};
1075
1076static struct clk_rcg2 mclk2_clk_src = {
1077 .cmd_rcgr = 0x5c000,
1078 .hid_width = 5,
1079 .mnd_width = 8,
1080 .freq_tbl = ftbl_mclk_clk_src,
1081 .parent_map = gcc_xo_gpll0_gpll6_sleep_map,
1082 .clkr.hw.init = &(struct clk_init_data) {
1083 .name = "mclk2_clk_src",
1084 .parent_data = gcc_xo_gpll0_gpll6_sleep_data,
1085 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_sleep_data),
1086 .ops = &clk_rcg2_ops,
1087 }
1088};
1089
1090static const struct freq_tbl ftbl_mdp_clk_src[] = {
1091 F(50000000, P_GPLL0, 16, 0, 0),
1092 F(80000000, P_GPLL0, 10, 0, 0),
1093 F(100000000, P_GPLL0, 8, 0, 0),
1094 F(145450000, P_GPLL0, 5.5, 0, 0),
1095 F(160000000, P_GPLL0, 5, 0, 0),
1096 F(177780000, P_GPLL0, 4.5, 0, 0),
1097 F(200000000, P_GPLL0, 4, 0, 0),
1098 F(266670000, P_GPLL0, 3, 0, 0),
1099 F(320000000, P_GPLL0, 2.5, 0, 0),
1100 { }
1101};
1102
1103static struct clk_rcg2 mdp_clk_src = {
1104 .cmd_rcgr = 0x4d014,
1105 .hid_width = 5,
1106 .freq_tbl = ftbl_mdp_clk_src,
1107 .parent_map = gcc_xo_gpll0_map,
1108 .clkr.hw.init = &(struct clk_init_data) {
1109 .name = "mdp_clk_src",
1110 .parent_data = gcc_xo_gpll0_data,
1111 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
1112 .ops = &clk_rcg2_ops,
1113 }
1114};
1115
1116static const struct parent_map gcc_pclk0_map[] = {
1117 { P_XO, 0 },
1118 { P_DSI0PLL, 1 },
1119 { P_DSI1PLL, 3 },
1120};
1121
1122static const struct parent_map gcc_pclk1_map[] = {
1123 { P_XO, 0 },
1124 { P_DSI0PLL, 3 },
1125 { P_DSI1PLL, 1 },
1126};
1127
1128static const struct clk_parent_data gcc_pclk_data[] = {
1129 { .index = DT_XO },
1130 { .index = DT_DSI0PLL },
1131 { .index = DT_DSI1PLL },
1132};
1133
1134static struct clk_rcg2 pclk0_clk_src = {
1135 .cmd_rcgr = 0x4d000,
1136 .hid_width = 5,
1137 .mnd_width = 8,
1138 .parent_map = gcc_pclk0_map,
1139 .clkr.hw.init = &(struct clk_init_data) {
1140 .name = "pclk0_clk_src",
1141 .parent_data = gcc_pclk_data,
1142 .num_parents = ARRAY_SIZE(gcc_pclk_data),
1143 .ops = &clk_pixel_ops,
1144 .flags = CLK_SET_RATE_PARENT,
1145 }
1146};
1147
1148static struct clk_rcg2 pclk1_clk_src = {
1149 .cmd_rcgr = 0x4d0b8,
1150 .hid_width = 5,
1151 .mnd_width = 8,
1152 .parent_map = gcc_pclk1_map,
1153 .clkr.hw.init = &(struct clk_init_data){
1154 .name = "pclk1_clk_src",
1155 .parent_data = gcc_pclk_data,
1156 .num_parents = ARRAY_SIZE(gcc_pclk_data),
1157 .ops = &clk_pixel_ops,
1158 .flags = CLK_SET_RATE_PARENT,
1159 },
1160};
1161
1162static const struct freq_tbl ftbl_pdm2_clk_src[] = {
1163 F(64000000, P_GPLL0, 12.5, 0, 0),
1164 { }
1165};
1166
1167static struct clk_rcg2 pdm2_clk_src = {
1168 .cmd_rcgr = 0x44010,
1169 .hid_width = 5,
1170 .freq_tbl = ftbl_pdm2_clk_src,
1171 .parent_map = gcc_xo_gpll0_map,
1172 .clkr.hw.init = &(struct clk_init_data) {
1173 .name = "pdm2_clk_src",
1174 .parent_data = gcc_xo_gpll0_data,
1175 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
1176 .ops = &clk_rcg2_ops,
1177 }
1178};
1179
1180static const struct freq_tbl ftbl_sdcc1_ice_core_clk_src[] = {
1181 F(100000000, P_GPLL0, 8, 0, 0),
1182 F(200000000, P_GPLL0, 4, 0, 0),
1183 { }
1184};
1185
1186static struct clk_rcg2 sdcc1_ice_core_clk_src = {
1187 .cmd_rcgr = 0x5d000,
1188 .hid_width = 5,
1189 .freq_tbl = ftbl_sdcc1_ice_core_clk_src,
1190 .parent_map = gcc_xo_gpll0_map,
1191 .clkr.hw.init = &(struct clk_init_data) {
1192 .name = "sdcc1_ice_core_clk_src",
1193 .parent_data = gcc_xo_gpll0_data,
1194 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
1195 .ops = &clk_rcg2_ops,
1196 }
1197};
1198
1199static const struct parent_map gcc_sdcc1_apps_map[] = {
1200 { P_XO, 0 },
1201 { P_GPLL0, 1 },
1202 { P_GPLL4, 2 },
1203};
1204
1205static const struct clk_parent_data gcc_sdcc1_apss_data[] = {
1206 { .index = DT_XO },
1207 { .hw = &gpll0.clkr.hw },
1208 { .hw = &gpll4.clkr.hw },
1209};
1210
1211static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
1212 F(144000, P_XO, 16, 3, 25),
1213 F(400000, P_XO, 12, 1, 4),
1214 F(20000000, P_GPLL0, 10, 1, 4),
1215 F(25000000, P_GPLL0, 16, 1, 2),
1216 F(50000000, P_GPLL0, 16, 0, 0),
1217 F(100000000, P_GPLL0, 8, 0, 0),
1218 F(177770000, P_GPLL0, 4.5, 0, 0),
1219 F(192000000, P_GPLL4, 6, 0, 0),
1220 F(200000000, P_GPLL0, 4, 0, 0),
1221 F(384000000, P_GPLL4, 3, 0, 0),
1222 { }
1223};
1224
1225static struct clk_rcg2 sdcc1_apps_clk_src = {
1226 .cmd_rcgr = 0x42004,
1227 .hid_width = 5,
1228 .mnd_width = 8,
1229 .freq_tbl = ftbl_sdcc1_apps_clk_src,
1230 .parent_map = gcc_sdcc1_apps_map,
1231 .clkr.hw.init = &(struct clk_init_data) {
1232 .name = "sdcc1_apps_clk_src",
1233 .parent_data = gcc_sdcc1_apss_data,
1234 .num_parents = ARRAY_SIZE(gcc_sdcc1_apss_data),
1235 .ops = &clk_rcg2_floor_ops,
1236 }
1237};
1238
1239static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = {
1240 F(144000, P_XO, 16, 3, 25),
1241 F(400000, P_XO, 12, 1, 4),
1242 F(20000000, P_GPLL0, 10, 1, 4),
1243 F(25000000, P_GPLL0, 16, 1, 2),
1244 F(50000000, P_GPLL0, 16, 0, 0),
1245 F(100000000, P_GPLL0, 8, 0, 0),
1246 F(177770000, P_GPLL0, 4.5, 0, 0),
1247 F(200000000, P_GPLL0, 4, 0, 0),
1248 { }
1249};
1250
1251static struct clk_rcg2 sdcc2_apps_clk_src = {
1252 .cmd_rcgr = 0x43004,
1253 .hid_width = 5,
1254 .mnd_width = 8,
1255 .freq_tbl = ftbl_sdcc2_apps_clk_src,
1256 .parent_map = gcc_xo_gpll0_map,
1257 .clkr.hw.init = &(struct clk_init_data) {
1258 .name = "sdcc2_apps_clk_src",
1259 .parent_data = gcc_xo_gpll0_data,
1260 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
1261 .ops = &clk_rcg2_floor_ops,
1262 }
1263};
1264
1265static const struct freq_tbl ftbl_usb_hs_system_clk_src[] = {
1266 F(80000000, P_GPLL0, 10, 0, 0),
1267 F(100000000, P_GPLL0, 8, 0, 0),
1268 F(133330000, P_GPLL0, 6, 0, 0),
1269 F(177780000, P_GPLL0, 4.5, 0, 0),
1270 { }
1271};
1272
1273static const struct freq_tbl ftbl_usb_hs_system_clk_src_msm8937[] = {
1274 F(57142857, P_GPLL0, 14, 0, 0),
1275 F(100000000, P_GPLL0, 8, 0, 0),
1276 F(133333333, P_GPLL0, 6, 0, 0),
1277 F(177777778, P_GPLL0, 4.5, 0, 0),
1278 { }
1279};
1280
1281static struct clk_rcg2 usb_hs_system_clk_src = {
1282 .cmd_rcgr = 0x41010,
1283 .hid_width = 5,
1284 .parent_map = gcc_xo_gpll0_map,
1285 .freq_tbl = ftbl_usb_hs_system_clk_src,
1286 .clkr.hw.init = &(struct clk_init_data){
1287 .name = "usb_hs_system_clk_src",
1288 .parent_data = gcc_xo_gpll0_data,
1289 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
1290 .ops = &clk_rcg2_ops,
1291 },
1292};
1293
1294static const struct freq_tbl ftbl_vcodec0_clk_src[] = {
1295 F(133330000, P_GPLL0, 6, 0, 0),
1296 F(180000000, P_GPLL6, 6, 0, 0),
1297 F(228570000, P_GPLL0, 3.5, 0, 0),
1298 F(266670000, P_GPLL0, 3, 0, 0),
1299 F(308570000, P_GPLL6, 3.5, 0, 0),
1300 F(329140000, P_GPLL4, 3.5, 0, 0),
1301 F(360000000, P_GPLL6, 3, 0, 0),
1302 { }
1303};
1304
1305static const struct freq_tbl ftbl_vcodec0_clk_src_msm8937[] = {
1306 F(166150000, P_GPLL6, 6.5, 0, 0),
1307 F(240000000, P_GPLL6, 4.5, 0, 0),
1308 F(308571428, P_GPLL6, 3.5, 0, 0),
1309 F(320000000, P_GPLL0, 2.5, 0, 0),
1310 F(360000000, P_GPLL6, 3, 0, 0),
1311 { }
1312};
1313
1314static struct clk_rcg2 vcodec0_clk_src = {
1315 .cmd_rcgr = 0x4c000,
1316 .hid_width = 5,
1317 .freq_tbl = ftbl_vcodec0_clk_src,
1318 .parent_map = gcc_xo_gpll0_gpll6_gpll4_map,
1319 .clkr.hw.init = &(struct clk_init_data) {
1320 .name = "vcodec0_clk_src",
1321 .parent_data = gcc_xo_gpll0_gpll6_gpll4_data,
1322 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll4_data),
1323 .ops = &clk_rcg2_ops,
1324 }
1325};
1326
1327static const struct freq_tbl ftbl_vfe_clk_src[] = {
1328 F(50000000, P_GPLL0, 16, 0, 0),
1329 F(80000000, P_GPLL0, 10, 0, 0),
1330 F(100000000, P_GPLL0, 8, 0, 0),
1331 F(133330000, P_GPLL0, 6, 0, 0),
1332 F(160000000, P_GPLL0, 5, 0, 0),
1333 F(200000000, P_GPLL0, 4, 0, 0),
1334 F(266670000, P_GPLL0, 3, 0, 0),
1335 F(308570000, P_GPLL6, 3.5, 0, 0),
1336 F(320000000, P_GPLL0, 2.5, 0, 0),
1337 F(329140000, P_GPLL4, 3.5, 0, 0),
1338 F(360000000, P_GPLL6, 3, 0, 0),
1339 { }
1340};
1341
1342static const struct freq_tbl ftbl_vfe_clk_src_msm8937[] = {
1343 F(50000000, P_GPLL0, 16, 0, 0),
1344 F(80000000, P_GPLL0, 10, 0, 0),
1345 F(100000000, P_GPLL0, 8, 0, 0),
1346 F(133333333, P_GPLL0, 6, 0, 0),
1347 F(160000000, P_GPLL0, 5, 0, 0),
1348 F(177777778, P_GPLL0, 4.5, 0, 0),
1349 F(200000000, P_GPLL0, 4, 0, 0),
1350 F(266666667, P_GPLL0, 3, 0, 0),
1351 F(308571428, P_GPLL6, 3.5, 0, 0),
1352 F(320000000, P_GPLL0, 2.5, 0, 0),
1353 F(360000000, P_GPLL6, 3, 0, 0),
1354 F(400000000, P_GPLL0, 2, 0, 0),
1355 F(432000000, P_GPLL6, 2.5, 0, 0),
1356 { }
1357};
1358
1359static struct clk_rcg2 vfe0_clk_src = {
1360 .cmd_rcgr = 0x58000,
1361 .hid_width = 5,
1362 .freq_tbl = ftbl_vfe_clk_src,
1363 .parent_map = gcc_xo_gpll0_gpll6_gpll4_map,
1364 .clkr.hw.init = &(struct clk_init_data) {
1365 .name = "vfe0_clk_src",
1366 .parent_data = gcc_xo_gpll0_gpll6_gpll4_data,
1367 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll4_data),
1368 .ops = &clk_rcg2_ops,
1369 }
1370};
1371
1372static struct clk_rcg2 vfe1_clk_src = {
1373 .cmd_rcgr = 0x58054,
1374 .hid_width = 5,
1375 .freq_tbl = ftbl_vfe_clk_src,
1376 .parent_map = gcc_xo_gpll0_gpll6_gpll4_map,
1377 .clkr.hw.init = &(struct clk_init_data) {
1378 .name = "vfe1_clk_src",
1379 .parent_data = gcc_xo_gpll0_gpll6_gpll4_data,
1380 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll4_data),
1381 .ops = &clk_rcg2_ops,
1382 }
1383};
1384
1385static const struct freq_tbl ftbl_vsync_clk_src[] = {
1386 F(19200000, P_XO, 1, 0, 0),
1387 { }
1388};
1389
1390static struct clk_rcg2 vsync_clk_src = {
1391 .cmd_rcgr = 0x4d02c,
1392 .hid_width = 5,
1393 .freq_tbl = ftbl_vsync_clk_src,
1394 .parent_map = gcc_xo_gpll0_out_aux_map,
1395 .clkr.hw.init = &(struct clk_init_data) {
1396 .name = "vsync_clk_src",
1397 .parent_data = gcc_xo_gpll0_data,
1398 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),
1399 .ops = &clk_rcg2_ops,
1400 }
1401};
1402
1403static struct clk_branch gcc_apss_tcu_clk = {
1404 .halt_reg = 0x12018,
1405 .halt_check = BRANCH_HALT_VOTED,
1406 .clkr = {
1407 .enable_reg = 0x4500c,
1408 .enable_mask = BIT(1),
1409 .hw.init = &(struct clk_init_data) {
1410 .name = "gcc_apss_tcu_clk",
1411 .ops = &clk_branch2_ops,
1412 }
1413 }
1414};
1415
1416static struct clk_branch gcc_bimc_gfx_clk = {
1417 .halt_reg = 0x59034,
1418 .halt_check = BRANCH_HALT,
1419 .clkr = {
1420 .enable_reg = 0x59034,
1421 .enable_mask = BIT(0),
1422 .hw.init = &(struct clk_init_data) {
1423 .name = "gcc_bimc_gfx_clk",
1424 .ops = &clk_branch2_ops,
1425 }
1426 }
1427};
1428
1429static struct clk_branch gcc_bimc_gpu_clk = {
1430 .halt_reg = 0x59030,
1431 .halt_check = BRANCH_HALT,
1432 .clkr = {
1433 .enable_reg = 0x59030,
1434 .enable_mask = BIT(0),
1435 .hw.init = &(struct clk_init_data) {
1436 .name = "gcc_bimc_gpu_clk",
1437 .ops = &clk_branch2_ops,
1438 }
1439 }
1440};
1441
1442static struct clk_branch gcc_blsp1_ahb_clk = {
1443 .halt_reg = 0x01008,
1444 .halt_check = BRANCH_HALT_VOTED,
1445 .clkr = {
1446 .enable_reg = 0x45004,
1447 .enable_mask = BIT(10),
1448 .hw.init = &(struct clk_init_data) {
1449 .name = "gcc_blsp1_ahb_clk",
1450 .ops = &clk_branch2_ops,
1451 }
1452 }
1453};
1454
1455static struct clk_branch gcc_blsp2_ahb_clk = {
1456 .halt_reg = 0x0b008,
1457 .halt_check = BRANCH_HALT_VOTED,
1458 .clkr = {
1459 .enable_reg = 0x45004,
1460 .enable_mask = BIT(20),
1461 .hw.init = &(struct clk_init_data) {
1462 .name = "gcc_blsp2_ahb_clk",
1463 .ops = &clk_branch2_ops,
1464 }
1465 }
1466};
1467
1468static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1469 .halt_reg = 0x02008,
1470 .halt_check = BRANCH_HALT,
1471 .clkr = {
1472 .enable_reg = 0x02008,
1473 .enable_mask = BIT(0),
1474 .hw.init = &(struct clk_init_data){
1475 .name = "gcc_blsp1_qup1_i2c_apps_clk",
1476 .parent_hws = (const struct clk_hw*[]){
1477 &blsp1_qup1_i2c_apps_clk_src.clkr.hw,
1478 },
1479 .num_parents = 1,
1480 .ops = &clk_branch2_ops,
1481 .flags = CLK_SET_RATE_PARENT,
1482 },
1483 },
1484};
1485
1486static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1487 .halt_reg = 0x03010,
1488 .halt_check = BRANCH_HALT,
1489 .clkr = {
1490 .enable_reg = 0x03010,
1491 .enable_mask = BIT(0),
1492 .hw.init = &(struct clk_init_data) {
1493 .name = "gcc_blsp1_qup2_i2c_apps_clk",
1494 .parent_hws = (const struct clk_hw*[]){
1495 &blsp1_qup2_i2c_apps_clk_src.clkr.hw,
1496 },
1497 .num_parents = 1,
1498 .ops = &clk_branch2_ops,
1499 .flags = CLK_SET_RATE_PARENT,
1500 }
1501 }
1502};
1503
1504static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1505 .halt_reg = 0x04020,
1506 .halt_check = BRANCH_HALT,
1507 .clkr = {
1508 .enable_reg = 0x04020,
1509 .enable_mask = BIT(0),
1510 .hw.init = &(struct clk_init_data) {
1511 .name = "gcc_blsp1_qup3_i2c_apps_clk",
1512 .parent_hws = (const struct clk_hw*[]){
1513 &blsp1_qup3_i2c_apps_clk_src.clkr.hw,
1514 },
1515 .num_parents = 1,
1516 .ops = &clk_branch2_ops,
1517 .flags = CLK_SET_RATE_PARENT,
1518 }
1519 }
1520};
1521
1522static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1523 .halt_reg = 0x05020,
1524 .halt_check = BRANCH_HALT,
1525 .clkr = {
1526 .enable_reg = 0x05020,
1527 .enable_mask = BIT(0),
1528 .hw.init = &(struct clk_init_data) {
1529 .name = "gcc_blsp1_qup4_i2c_apps_clk",
1530 .parent_hws = (const struct clk_hw*[]){
1531 &blsp1_qup4_i2c_apps_clk_src.clkr.hw,
1532 },
1533 .num_parents = 1,
1534 .ops = &clk_branch2_ops,
1535 .flags = CLK_SET_RATE_PARENT,
1536 }
1537 }
1538};
1539
1540static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
1541 .halt_reg = 0x0c008,
1542 .halt_check = BRANCH_HALT,
1543 .clkr = {
1544 .enable_reg = 0x0c008,
1545 .enable_mask = BIT(0),
1546 .hw.init = &(struct clk_init_data) {
1547 .name = "gcc_blsp2_qup1_i2c_apps_clk",
1548 .parent_hws = (const struct clk_hw*[]){
1549 &blsp2_qup1_i2c_apps_clk_src.clkr.hw,
1550 },
1551 .num_parents = 1,
1552 .ops = &clk_branch2_ops,
1553 .flags = CLK_SET_RATE_PARENT,
1554 }
1555 }
1556};
1557
1558static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
1559 .halt_reg = 0x0d010,
1560 .halt_check = BRANCH_HALT,
1561 .clkr = {
1562 .enable_reg = 0x0d010,
1563 .enable_mask = BIT(0),
1564 .hw.init = &(struct clk_init_data) {
1565 .name = "gcc_blsp2_qup2_i2c_apps_clk",
1566 .parent_hws = (const struct clk_hw*[]){
1567 &blsp2_qup2_i2c_apps_clk_src.clkr.hw,
1568 },
1569 .num_parents = 1,
1570 .ops = &clk_branch2_ops,
1571 .flags = CLK_SET_RATE_PARENT,
1572 }
1573 }
1574};
1575
1576static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
1577 .halt_reg = 0x0f020,
1578 .halt_check = BRANCH_HALT,
1579 .clkr = {
1580 .enable_reg = 0x0f020,
1581 .enable_mask = BIT(0),
1582 .hw.init = &(struct clk_init_data) {
1583 .name = "gcc_blsp2_qup3_i2c_apps_clk",
1584 .parent_hws = (const struct clk_hw*[]){
1585 &blsp2_qup3_i2c_apps_clk_src.clkr.hw,
1586 },
1587 .num_parents = 1,
1588 .ops = &clk_branch2_ops,
1589 .flags = CLK_SET_RATE_PARENT,
1590 }
1591 }
1592};
1593
1594static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
1595 .halt_reg = 0x18020,
1596 .halt_check = BRANCH_HALT,
1597 .clkr = {
1598 .enable_reg = 0x18020,
1599 .enable_mask = BIT(0),
1600 .hw.init = &(struct clk_init_data){
1601 .name = "gcc_blsp2_qup4_i2c_apps_clk",
1602 .parent_hws = (const struct clk_hw*[]){
1603 &blsp2_qup4_i2c_apps_clk_src.clkr.hw,
1604 },
1605 .num_parents = 1,
1606 .ops = &clk_branch2_ops,
1607 .flags = CLK_SET_RATE_PARENT,
1608 },
1609 },
1610};
1611
1612static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1613 .halt_reg = 0x02004,
1614 .halt_check = BRANCH_HALT,
1615 .clkr = {
1616 .enable_reg = 0x02004,
1617 .enable_mask = BIT(0),
1618 .hw.init = &(struct clk_init_data){
1619 .name = "gcc_blsp1_qup1_spi_apps_clk",
1620 .parent_hws = (const struct clk_hw*[]){
1621 &blsp1_qup1_spi_apps_clk_src.clkr.hw,
1622 },
1623 .num_parents = 1,
1624 .ops = &clk_branch2_ops,
1625 .flags = CLK_SET_RATE_PARENT,
1626 },
1627 },
1628};
1629
1630static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1631 .halt_reg = 0x0300c,
1632 .halt_check = BRANCH_HALT,
1633 .clkr = {
1634 .enable_reg = 0x0300c,
1635 .enable_mask = BIT(0),
1636 .hw.init = &(struct clk_init_data) {
1637 .name = "gcc_blsp1_qup2_spi_apps_clk",
1638 .parent_hws = (const struct clk_hw*[]){
1639 &blsp1_qup2_spi_apps_clk_src.clkr.hw,
1640 },
1641 .num_parents = 1,
1642 .ops = &clk_branch2_ops,
1643 .flags = CLK_SET_RATE_PARENT,
1644 }
1645 }
1646};
1647
1648static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1649 .halt_reg = 0x0401c,
1650 .halt_check = BRANCH_HALT,
1651 .clkr = {
1652 .enable_reg = 0x0401c,
1653 .enable_mask = BIT(0),
1654 .hw.init = &(struct clk_init_data) {
1655 .name = "gcc_blsp1_qup3_spi_apps_clk",
1656 .parent_hws = (const struct clk_hw*[]){
1657 &blsp1_qup3_spi_apps_clk_src.clkr.hw,
1658 },
1659 .num_parents = 1,
1660 .ops = &clk_branch2_ops,
1661 .flags = CLK_SET_RATE_PARENT,
1662 }
1663 }
1664};
1665
1666static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1667 .halt_reg = 0x0501c,
1668 .halt_check = BRANCH_HALT,
1669 .clkr = {
1670 .enable_reg = 0x0501c,
1671 .enable_mask = BIT(0),
1672 .hw.init = &(struct clk_init_data) {
1673 .name = "gcc_blsp1_qup4_spi_apps_clk",
1674 .parent_hws = (const struct clk_hw*[]){
1675 &blsp1_qup4_spi_apps_clk_src.clkr.hw,
1676 },
1677 .num_parents = 1,
1678 .ops = &clk_branch2_ops,
1679 .flags = CLK_SET_RATE_PARENT,
1680 }
1681 }
1682};
1683
1684static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
1685 .halt_reg = 0x0c004,
1686 .halt_check = BRANCH_HALT,
1687 .clkr = {
1688 .enable_reg = 0x0c004,
1689 .enable_mask = BIT(0),
1690 .hw.init = &(struct clk_init_data) {
1691 .name = "gcc_blsp2_qup1_spi_apps_clk",
1692 .parent_hws = (const struct clk_hw*[]){
1693 &blsp2_qup1_spi_apps_clk_src.clkr.hw,
1694 },
1695 .num_parents = 1,
1696 .ops = &clk_branch2_ops,
1697 .flags = CLK_SET_RATE_PARENT,
1698 }
1699 }
1700};
1701
1702static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
1703 .halt_reg = 0x0d00c,
1704 .halt_check = BRANCH_HALT,
1705 .clkr = {
1706 .enable_reg = 0x0d00c,
1707 .enable_mask = BIT(0),
1708 .hw.init = &(struct clk_init_data) {
1709 .name = "gcc_blsp2_qup2_spi_apps_clk",
1710 .parent_hws = (const struct clk_hw*[]){
1711 &blsp2_qup2_spi_apps_clk_src.clkr.hw,
1712 },
1713 .num_parents = 1,
1714 .ops = &clk_branch2_ops,
1715 .flags = CLK_SET_RATE_PARENT,
1716 }
1717 }
1718};
1719
1720static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
1721 .halt_reg = 0x0f01c,
1722 .halt_check = BRANCH_HALT,
1723 .clkr = {
1724 .enable_reg = 0x0f01c,
1725 .enable_mask = BIT(0),
1726 .hw.init = &(struct clk_init_data) {
1727 .name = "gcc_blsp2_qup3_spi_apps_clk",
1728 .parent_hws = (const struct clk_hw*[]){
1729 &blsp2_qup3_spi_apps_clk_src.clkr.hw,
1730 },
1731 .num_parents = 1,
1732 .ops = &clk_branch2_ops,
1733 .flags = CLK_SET_RATE_PARENT,
1734 }
1735 }
1736};
1737
1738static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
1739 .halt_reg = 0x1801c,
1740 .halt_check = BRANCH_HALT,
1741 .clkr = {
1742 .enable_reg = 0x1801c,
1743 .enable_mask = BIT(0),
1744 .hw.init = &(struct clk_init_data){
1745 .name = "gcc_blsp2_qup4_spi_apps_clk",
1746 .parent_hws = (const struct clk_hw*[]){
1747 &blsp2_qup4_spi_apps_clk_src.clkr.hw,
1748 },
1749 .num_parents = 1,
1750 .ops = &clk_branch2_ops,
1751 .flags = CLK_SET_RATE_PARENT,
1752 },
1753 },
1754};
1755
1756static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1757 .halt_reg = 0x0203c,
1758 .halt_check = BRANCH_HALT,
1759 .clkr = {
1760 .enable_reg = 0x0203c,
1761 .enable_mask = BIT(0),
1762 .hw.init = &(struct clk_init_data) {
1763 .name = "gcc_blsp1_uart1_apps_clk",
1764 .parent_hws = (const struct clk_hw*[]){
1765 &blsp1_uart1_apps_clk_src.clkr.hw,
1766 },
1767 .num_parents = 1,
1768 .ops = &clk_branch2_ops,
1769 .flags = CLK_SET_RATE_PARENT,
1770 }
1771 }
1772};
1773
1774static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1775 .halt_reg = 0x0302c,
1776 .halt_check = BRANCH_HALT,
1777 .clkr = {
1778 .enable_reg = 0x0302c,
1779 .enable_mask = BIT(0),
1780 .hw.init = &(struct clk_init_data) {
1781 .name = "gcc_blsp1_uart2_apps_clk",
1782 .parent_hws = (const struct clk_hw*[]){
1783 &blsp1_uart2_apps_clk_src.clkr.hw,
1784 },
1785 .num_parents = 1,
1786 .ops = &clk_branch2_ops,
1787 .flags = CLK_SET_RATE_PARENT,
1788 }
1789 }
1790};
1791
1792static struct clk_branch gcc_blsp2_uart1_apps_clk = {
1793 .halt_reg = 0x0c03c,
1794 .halt_check = BRANCH_HALT,
1795 .clkr = {
1796 .enable_reg = 0x0c03c,
1797 .enable_mask = BIT(0),
1798 .hw.init = &(struct clk_init_data) {
1799 .name = "gcc_blsp2_uart1_apps_clk",
1800 .parent_hws = (const struct clk_hw*[]){
1801 &blsp2_uart1_apps_clk_src.clkr.hw,
1802 },
1803 .num_parents = 1,
1804 .ops = &clk_branch2_ops,
1805 .flags = CLK_SET_RATE_PARENT,
1806 }
1807 }
1808};
1809
1810static struct clk_branch gcc_blsp2_uart2_apps_clk = {
1811 .halt_reg = 0x0d02c,
1812 .halt_check = BRANCH_HALT,
1813 .clkr = {
1814 .enable_reg = 0x0d02c,
1815 .enable_mask = BIT(0),
1816 .hw.init = &(struct clk_init_data) {
1817 .name = "gcc_blsp2_uart2_apps_clk",
1818 .parent_hws = (const struct clk_hw*[]){
1819 &blsp2_uart2_apps_clk_src.clkr.hw,
1820 },
1821 .num_parents = 1,
1822 .ops = &clk_branch2_ops,
1823 .flags = CLK_SET_RATE_PARENT,
1824 }
1825 }
1826};
1827
1828static struct clk_branch gcc_boot_rom_ahb_clk = {
1829 .halt_reg = 0x1300c,
1830 .halt_check = BRANCH_HALT_VOTED,
1831 .clkr = {
1832 .enable_reg = 0x45004,
1833 .enable_mask = BIT(7),
1834 .hw.init = &(struct clk_init_data) {
1835 .name = "gcc_boot_rom_ahb_clk",
1836 .ops = &clk_branch2_ops,
1837 }
1838 }
1839};
1840
1841static struct clk_branch gcc_camss_ahb_clk = {
1842 .halt_reg = 0x56004,
1843 .halt_check = BRANCH_HALT,
1844 .clkr = {
1845 .enable_reg = 0x56004,
1846 .enable_mask = BIT(0),
1847 .hw.init = &(struct clk_init_data) {
1848 .name = "gcc_camss_ahb_clk",
1849 .ops = &clk_branch2_ops,
1850 }
1851 }
1852};
1853
1854static struct clk_branch gcc_camss_cci_ahb_clk = {
1855 .halt_reg = 0x5101c,
1856 .halt_check = BRANCH_HALT,
1857 .clkr = {
1858 .enable_reg = 0x5101c,
1859 .enable_mask = BIT(0),
1860 .hw.init = &(struct clk_init_data) {
1861 .name = "gcc_camss_cci_ahb_clk",
1862 .parent_hws = (const struct clk_hw*[]){
1863 &camss_top_ahb_clk_src.clkr.hw,
1864 },
1865 .num_parents = 1,
1866 .ops = &clk_branch2_ops,
1867 .flags = CLK_SET_RATE_PARENT,
1868 }
1869 }
1870};
1871
1872static struct clk_branch gcc_camss_cci_clk = {
1873 .halt_reg = 0x51018,
1874 .halt_check = BRANCH_HALT,
1875 .clkr = {
1876 .enable_reg = 0x51018,
1877 .enable_mask = BIT(0),
1878 .hw.init = &(struct clk_init_data) {
1879 .name = "gcc_camss_cci_clk",
1880 .parent_hws = (const struct clk_hw*[]){
1881 &cci_clk_src.clkr.hw,
1882 },
1883 .num_parents = 1,
1884 .ops = &clk_branch2_ops,
1885 .flags = CLK_SET_RATE_PARENT,
1886 }
1887 }
1888};
1889
1890static struct clk_branch gcc_camss_cpp_ahb_clk = {
1891 .halt_reg = 0x58040,
1892 .halt_check = BRANCH_HALT,
1893 .clkr = {
1894 .enable_reg = 0x58040,
1895 .enable_mask = BIT(0),
1896 .hw.init = &(struct clk_init_data) {
1897 .name = "gcc_camss_cpp_ahb_clk",
1898 .parent_hws = (const struct clk_hw*[]){
1899 &camss_top_ahb_clk_src.clkr.hw,
1900 },
1901 .num_parents = 1,
1902 .ops = &clk_branch2_ops,
1903 .flags = CLK_SET_RATE_PARENT,
1904 }
1905 }
1906};
1907
1908static struct clk_branch gcc_camss_cpp_clk = {
1909 .halt_reg = 0x5803c,
1910 .halt_check = BRANCH_HALT,
1911 .clkr = {
1912 .enable_reg = 0x5803c,
1913 .enable_mask = BIT(0),
1914 .hw.init = &(struct clk_init_data) {
1915 .name = "gcc_camss_cpp_clk",
1916 .parent_hws = (const struct clk_hw*[]){
1917 &cpp_clk_src.clkr.hw,
1918 },
1919 .num_parents = 1,
1920 .ops = &clk_branch2_ops,
1921 .flags = CLK_SET_RATE_PARENT,
1922 }
1923 }
1924};
1925
1926static struct clk_branch gcc_camss_csi0_ahb_clk = {
1927 .halt_reg = 0x4e040,
1928 .halt_check = BRANCH_HALT,
1929 .clkr = {
1930 .enable_reg = 0x4e040,
1931 .enable_mask = BIT(0),
1932 .hw.init = &(struct clk_init_data) {
1933 .name = "gcc_camss_csi0_ahb_clk",
1934 .parent_hws = (const struct clk_hw*[]){
1935 &camss_top_ahb_clk_src.clkr.hw,
1936 },
1937 .num_parents = 1,
1938 .ops = &clk_branch2_ops,
1939 .flags = CLK_SET_RATE_PARENT,
1940 }
1941 }
1942};
1943
1944static struct clk_branch gcc_camss_csi1_ahb_clk = {
1945 .halt_reg = 0x4f040,
1946 .halt_check = BRANCH_HALT,
1947 .clkr = {
1948 .enable_reg = 0x4f040,
1949 .enable_mask = BIT(0),
1950 .hw.init = &(struct clk_init_data) {
1951 .name = "gcc_camss_csi1_ahb_clk",
1952 .parent_hws = (const struct clk_hw*[]){
1953 &camss_top_ahb_clk_src.clkr.hw,
1954 },
1955 .num_parents = 1,
1956 .ops = &clk_branch2_ops,
1957 .flags = CLK_SET_RATE_PARENT,
1958 }
1959 }
1960};
1961
1962static struct clk_branch gcc_camss_csi2_ahb_clk = {
1963 .halt_reg = 0x3c040,
1964 .halt_check = BRANCH_HALT,
1965 .clkr = {
1966 .enable_reg = 0x3c040,
1967 .enable_mask = BIT(0),
1968 .hw.init = &(struct clk_init_data) {
1969 .name = "gcc_camss_csi2_ahb_clk",
1970 .parent_hws = (const struct clk_hw*[]){
1971 &camss_top_ahb_clk_src.clkr.hw,
1972 },
1973 .num_parents = 1,
1974 .ops = &clk_branch2_ops,
1975 .flags = CLK_SET_RATE_PARENT,
1976 }
1977 }
1978};
1979
1980static struct clk_branch gcc_camss_csi0_clk = {
1981 .halt_reg = 0x4e03c,
1982 .halt_check = BRANCH_HALT,
1983 .clkr = {
1984 .enable_reg = 0x4e03c,
1985 .enable_mask = BIT(0),
1986 .hw.init = &(struct clk_init_data) {
1987 .name = "gcc_camss_csi0_clk",
1988 .parent_hws = (const struct clk_hw*[]){
1989 &csi0_clk_src.clkr.hw,
1990 },
1991 .num_parents = 1,
1992 .ops = &clk_branch2_ops,
1993 .flags = CLK_SET_RATE_PARENT,
1994 }
1995 }
1996};
1997
1998static struct clk_branch gcc_camss_csi1_clk = {
1999 .halt_reg = 0x4f03c,
2000 .halt_check = BRANCH_HALT,
2001 .clkr = {
2002 .enable_reg = 0x4f03c,
2003 .enable_mask = BIT(0),
2004 .hw.init = &(struct clk_init_data) {
2005 .name = "gcc_camss_csi1_clk",
2006 .parent_hws = (const struct clk_hw*[]){
2007 &csi1_clk_src.clkr.hw,
2008 },
2009 .num_parents = 1,
2010 .ops = &clk_branch2_ops,
2011 .flags = CLK_SET_RATE_PARENT,
2012 }
2013 }
2014};
2015
2016static struct clk_branch gcc_camss_csi2_clk = {
2017 .halt_reg = 0x3c03c,
2018 .halt_check = BRANCH_HALT,
2019 .clkr = {
2020 .enable_reg = 0x3c03c,
2021 .enable_mask = BIT(0),
2022 .hw.init = &(struct clk_init_data) {
2023 .name = "gcc_camss_csi2_clk",
2024 .parent_hws = (const struct clk_hw*[]){
2025 &csi2_clk_src.clkr.hw,
2026 },
2027 .num_parents = 1,
2028 .ops = &clk_branch2_ops,
2029 .flags = CLK_SET_RATE_PARENT,
2030 }
2031 }
2032};
2033
2034static struct clk_branch gcc_camss_csi0phy_clk = {
2035 .halt_reg = 0x4e048,
2036 .halt_check = BRANCH_HALT,
2037 .clkr = {
2038 .enable_reg = 0x4e048,
2039 .enable_mask = BIT(0),
2040 .hw.init = &(struct clk_init_data) {
2041 .name = "gcc_camss_csi0phy_clk",
2042 .parent_hws = (const struct clk_hw*[]){
2043 &csi0_clk_src.clkr.hw,
2044 },
2045 .num_parents = 1,
2046 .ops = &clk_branch2_ops,
2047 .flags = CLK_SET_RATE_PARENT,
2048 }
2049 }
2050};
2051
2052static struct clk_branch gcc_camss_csi1phy_clk = {
2053 .halt_reg = 0x4f048,
2054 .halt_check = BRANCH_HALT,
2055 .clkr = {
2056 .enable_reg = 0x4f048,
2057 .enable_mask = BIT(0),
2058 .hw.init = &(struct clk_init_data) {
2059 .name = "gcc_camss_csi1phy_clk",
2060 .parent_hws = (const struct clk_hw*[]){
2061 &csi1_clk_src.clkr.hw,
2062 },
2063 .num_parents = 1,
2064 .ops = &clk_branch2_ops,
2065 .flags = CLK_SET_RATE_PARENT,
2066 }
2067 }
2068};
2069
2070static struct clk_branch gcc_camss_csi2phy_clk = {
2071 .halt_reg = 0x3c048,
2072 .halt_check = BRANCH_HALT,
2073 .clkr = {
2074 .enable_reg = 0x3c048,
2075 .enable_mask = BIT(0),
2076 .hw.init = &(struct clk_init_data) {
2077 .name = "gcc_camss_csi2phy_clk",
2078 .parent_hws = (const struct clk_hw*[]){
2079 &csi2_clk_src.clkr.hw,
2080 },
2081 .num_parents = 1,
2082 .ops = &clk_branch2_ops,
2083 .flags = CLK_SET_RATE_PARENT,
2084 }
2085 }
2086};
2087
2088static struct clk_branch gcc_camss_csi0phytimer_clk = {
2089 .halt_reg = 0x4e01c,
2090 .halt_check = BRANCH_HALT,
2091 .clkr = {
2092 .enable_reg = 0x4e01c,
2093 .enable_mask = BIT(0),
2094 .hw.init = &(struct clk_init_data) {
2095 .name = "gcc_camss_csi0phytimer_clk",
2096 .parent_hws = (const struct clk_hw*[]){
2097 &csi0phytimer_clk_src.clkr.hw,
2098 },
2099 .num_parents = 1,
2100 .ops = &clk_branch2_ops,
2101 .flags = CLK_SET_RATE_PARENT,
2102 }
2103 }
2104};
2105
2106static struct clk_branch gcc_camss_csi1phytimer_clk = {
2107 .halt_reg = 0x4f01c,
2108 .halt_check = BRANCH_HALT,
2109 .clkr = {
2110 .enable_reg = 0x4f01c,
2111 .enable_mask = BIT(0),
2112 .hw.init = &(struct clk_init_data) {
2113 .name = "gcc_camss_csi1phytimer_clk",
2114 .parent_hws = (const struct clk_hw*[]){
2115 &csi1phytimer_clk_src.clkr.hw,
2116 },
2117 .num_parents = 1,
2118 .ops = &clk_branch2_ops,
2119 .flags = CLK_SET_RATE_PARENT,
2120 }
2121 }
2122};
2123
2124static struct clk_branch gcc_camss_csi0pix_clk = {
2125 .halt_reg = 0x4e058,
2126 .halt_check = BRANCH_HALT,
2127 .clkr = {
2128 .enable_reg = 0x4e058,
2129 .enable_mask = BIT(0),
2130 .hw.init = &(struct clk_init_data) {
2131 .name = "gcc_camss_csi0pix_clk",
2132 .parent_hws = (const struct clk_hw*[]){
2133 &csi0_clk_src.clkr.hw,
2134 },
2135 .num_parents = 1,
2136 .ops = &clk_branch2_ops,
2137 .flags = CLK_SET_RATE_PARENT,
2138 }
2139 }
2140};
2141
2142static struct clk_branch gcc_camss_csi1pix_clk = {
2143 .halt_reg = 0x4f058,
2144 .halt_check = BRANCH_HALT,
2145 .clkr = {
2146 .enable_reg = 0x4f058,
2147 .enable_mask = BIT(0),
2148 .hw.init = &(struct clk_init_data) {
2149 .name = "gcc_camss_csi1pix_clk",
2150 .parent_hws = (const struct clk_hw*[]){
2151 &csi1_clk_src.clkr.hw,
2152 },
2153 .num_parents = 1,
2154 .ops = &clk_branch2_ops,
2155 .flags = CLK_SET_RATE_PARENT,
2156 }
2157 }
2158};
2159
2160static struct clk_branch gcc_camss_csi2pix_clk = {
2161 .halt_reg = 0x3c058,
2162 .halt_check = BRANCH_HALT,
2163 .clkr = {
2164 .enable_reg = 0x3c058,
2165 .enable_mask = BIT(0),
2166 .hw.init = &(struct clk_init_data) {
2167 .name = "gcc_camss_csi2pix_clk",
2168 .parent_hws = (const struct clk_hw*[]){
2169 &csi2_clk_src.clkr.hw,
2170 },
2171 .num_parents = 1,
2172 .ops = &clk_branch2_ops,
2173 .flags = CLK_SET_RATE_PARENT,
2174 }
2175 }
2176};
2177
2178static struct clk_branch gcc_camss_csi0rdi_clk = {
2179 .halt_reg = 0x4e050,
2180 .halt_check = BRANCH_HALT,
2181 .clkr = {
2182 .enable_reg = 0x4e050,
2183 .enable_mask = BIT(0),
2184 .hw.init = &(struct clk_init_data) {
2185 .name = "gcc_camss_csi0rdi_clk",
2186 .parent_hws = (const struct clk_hw*[]){
2187 &csi0_clk_src.clkr.hw,
2188 },
2189 .num_parents = 1,
2190 .ops = &clk_branch2_ops,
2191 .flags = CLK_SET_RATE_PARENT,
2192 }
2193 }
2194};
2195
2196static struct clk_branch gcc_camss_csi1rdi_clk = {
2197 .halt_reg = 0x4f050,
2198 .halt_check = BRANCH_HALT,
2199 .clkr = {
2200 .enable_reg = 0x4f050,
2201 .enable_mask = BIT(0),
2202 .hw.init = &(struct clk_init_data) {
2203 .name = "gcc_camss_csi1rdi_clk",
2204 .parent_hws = (const struct clk_hw*[]){
2205 &csi1_clk_src.clkr.hw,
2206 },
2207 .num_parents = 1,
2208 .ops = &clk_branch2_ops,
2209 .flags = CLK_SET_RATE_PARENT,
2210 }
2211 }
2212};
2213
2214static struct clk_branch gcc_camss_csi2rdi_clk = {
2215 .halt_reg = 0x3c050,
2216 .halt_check = BRANCH_HALT,
2217 .clkr = {
2218 .enable_reg = 0x3c050,
2219 .enable_mask = BIT(0),
2220 .hw.init = &(struct clk_init_data) {
2221 .name = "gcc_camss_csi2rdi_clk",
2222 .parent_hws = (const struct clk_hw*[]){
2223 &csi2_clk_src.clkr.hw,
2224 },
2225 .num_parents = 1,
2226 .ops = &clk_branch2_ops,
2227 .flags = CLK_SET_RATE_PARENT,
2228 }
2229 }
2230};
2231
2232static struct clk_branch gcc_camss_csi_vfe0_clk = {
2233 .halt_reg = 0x58050,
2234 .halt_check = BRANCH_HALT,
2235 .clkr = {
2236 .enable_reg = 0x58050,
2237 .enable_mask = BIT(0),
2238 .hw.init = &(struct clk_init_data) {
2239 .name = "gcc_camss_csi_vfe0_clk",
2240 .parent_hws = (const struct clk_hw*[]){
2241 &vfe0_clk_src.clkr.hw,
2242 },
2243 .num_parents = 1,
2244 .ops = &clk_branch2_ops,
2245 .flags = CLK_SET_RATE_PARENT,
2246 }
2247 }
2248};
2249
2250static struct clk_branch gcc_camss_csi_vfe1_clk = {
2251 .halt_reg = 0x58074,
2252 .halt_check = BRANCH_HALT,
2253 .clkr = {
2254 .enable_reg = 0x58074,
2255 .enable_mask = BIT(0),
2256 .hw.init = &(struct clk_init_data) {
2257 .name = "gcc_camss_csi_vfe1_clk",
2258 .parent_hws = (const struct clk_hw*[]){
2259 &vfe1_clk_src.clkr.hw,
2260 },
2261 .num_parents = 1,
2262 .ops = &clk_branch2_ops,
2263 .flags = CLK_SET_RATE_PARENT,
2264 }
2265 }
2266};
2267
2268static struct clk_branch gcc_camss_gp0_clk = {
2269 .halt_reg = 0x54018,
2270 .halt_check = BRANCH_HALT,
2271 .clkr = {
2272 .enable_reg = 0x54018,
2273 .enable_mask = BIT(0),
2274 .hw.init = &(struct clk_init_data) {
2275 .name = "gcc_camss_gp0_clk",
2276 .parent_hws = (const struct clk_hw*[]){
2277 &camss_gp0_clk_src.clkr.hw,
2278 },
2279 .num_parents = 1,
2280 .ops = &clk_branch2_ops,
2281 .flags = CLK_SET_RATE_PARENT,
2282 }
2283 }
2284};
2285
2286static struct clk_branch gcc_camss_gp1_clk = {
2287 .halt_reg = 0x55018,
2288 .halt_check = BRANCH_HALT,
2289 .clkr = {
2290 .enable_reg = 0x55018,
2291 .enable_mask = BIT(0),
2292 .hw.init = &(struct clk_init_data) {
2293 .name = "gcc_camss_gp1_clk",
2294 .parent_hws = (const struct clk_hw*[]){
2295 &camss_gp1_clk_src.clkr.hw,
2296 },
2297 .num_parents = 1,
2298 .ops = &clk_branch2_ops,
2299 .flags = CLK_SET_RATE_PARENT,
2300 }
2301 }
2302};
2303
2304static struct clk_branch gcc_camss_ispif_ahb_clk = {
2305 .halt_reg = 0x50004,
2306 .halt_check = BRANCH_HALT,
2307 .clkr = {
2308 .enable_reg = 0x50004,
2309 .enable_mask = BIT(0),
2310 .hw.init = &(struct clk_init_data) {
2311 .name = "gcc_camss_ispif_ahb_clk",
2312 .parent_hws = (const struct clk_hw*[]){
2313 &camss_top_ahb_clk_src.clkr.hw,
2314 },
2315 .num_parents = 1,
2316 .ops = &clk_branch2_ops,
2317 .flags = CLK_SET_RATE_PARENT,
2318 }
2319 }
2320};
2321
2322static struct clk_branch gcc_camss_jpeg0_clk = {
2323 .halt_reg = 0x57020,
2324 .halt_check = BRANCH_HALT,
2325 .clkr = {
2326 .enable_reg = 0x57020,
2327 .enable_mask = BIT(0),
2328 .hw.init = &(struct clk_init_data) {
2329 .name = "gcc_camss_jpeg0_clk",
2330 .parent_hws = (const struct clk_hw*[]){
2331 &jpeg0_clk_src.clkr.hw,
2332 },
2333 .num_parents = 1,
2334 .ops = &clk_branch2_ops,
2335 .flags = CLK_SET_RATE_PARENT,
2336 }
2337 }
2338};
2339
2340static struct clk_branch gcc_camss_jpeg_ahb_clk = {
2341 .halt_reg = 0x57024,
2342 .halt_check = BRANCH_HALT,
2343 .clkr = {
2344 .enable_reg = 0x57024,
2345 .enable_mask = BIT(0),
2346 .hw.init = &(struct clk_init_data) {
2347 .name = "gcc_camss_jpeg_ahb_clk",
2348 .parent_hws = (const struct clk_hw*[]){
2349 &camss_top_ahb_clk_src.clkr.hw,
2350 },
2351 .num_parents = 1,
2352 .ops = &clk_branch2_ops,
2353 .flags = CLK_SET_RATE_PARENT,
2354 }
2355 }
2356};
2357
2358static struct clk_branch gcc_camss_jpeg_axi_clk = {
2359 .halt_reg = 0x57028,
2360 .halt_check = BRANCH_HALT,
2361 .clkr = {
2362 .enable_reg = 0x57028,
2363 .enable_mask = BIT(0),
2364 .hw.init = &(struct clk_init_data) {
2365 .name = "gcc_camss_jpeg_axi_clk",
2366 .ops = &clk_branch2_ops,
2367 }
2368 }
2369};
2370
2371static struct clk_branch gcc_camss_mclk0_clk = {
2372 .halt_reg = 0x52018,
2373 .halt_check = BRANCH_HALT,
2374 .clkr = {
2375 .enable_reg = 0x52018,
2376 .enable_mask = BIT(0),
2377 .hw.init = &(struct clk_init_data) {
2378 .name = "gcc_camss_mclk0_clk",
2379 .parent_hws = (const struct clk_hw*[]){
2380 &mclk0_clk_src.clkr.hw,
2381 },
2382 .num_parents = 1,
2383 .ops = &clk_branch2_ops,
2384 .flags = CLK_SET_RATE_PARENT,
2385 }
2386 }
2387};
2388
2389static struct clk_branch gcc_camss_mclk1_clk = {
2390 .halt_reg = 0x53018,
2391 .halt_check = BRANCH_HALT,
2392 .clkr = {
2393 .enable_reg = 0x53018,
2394 .enable_mask = BIT(0),
2395 .hw.init = &(struct clk_init_data) {
2396 .name = "gcc_camss_mclk1_clk",
2397 .parent_hws = (const struct clk_hw*[]){
2398 &mclk1_clk_src.clkr.hw,
2399 },
2400 .num_parents = 1,
2401 .ops = &clk_branch2_ops,
2402 .flags = CLK_SET_RATE_PARENT,
2403 }
2404 }
2405};
2406
2407static struct clk_branch gcc_camss_mclk2_clk = {
2408 .halt_reg = 0x5c018,
2409 .halt_check = BRANCH_HALT,
2410 .clkr = {
2411 .enable_reg = 0x5c018,
2412 .enable_mask = BIT(0),
2413 .hw.init = &(struct clk_init_data) {
2414 .name = "gcc_camss_mclk2_clk",
2415 .parent_hws = (const struct clk_hw*[]){
2416 &mclk2_clk_src.clkr.hw,
2417 },
2418 .num_parents = 1,
2419 .ops = &clk_branch2_ops,
2420 .flags = CLK_SET_RATE_PARENT,
2421 }
2422 }
2423};
2424
2425static struct clk_branch gcc_camss_micro_ahb_clk = {
2426 .halt_reg = 0x5600c,
2427 .halt_check = BRANCH_HALT,
2428 .clkr = {
2429 .enable_reg = 0x5600c,
2430 .enable_mask = BIT(0),
2431 .hw.init = &(struct clk_init_data) {
2432 .name = "gcc_camss_micro_ahb_clk",
2433 .parent_hws = (const struct clk_hw*[]){
2434 &camss_top_ahb_clk_src.clkr.hw,
2435 },
2436 .num_parents = 1,
2437 .ops = &clk_branch2_ops,
2438 .flags = CLK_SET_RATE_PARENT,
2439 }
2440 }
2441};
2442
2443static struct clk_branch gcc_camss_top_ahb_clk = {
2444 .halt_reg = 0x5a014,
2445 .halt_check = BRANCH_HALT,
2446 .clkr = {
2447 .enable_reg = 0x5a014,
2448 .enable_mask = BIT(0),
2449 .hw.init = &(struct clk_init_data) {
2450 .name = "gcc_camss_top_ahb_clk",
2451 .parent_hws = (const struct clk_hw*[]){
2452 &camss_top_ahb_clk_src.clkr.hw,
2453 },
2454 .num_parents = 1,
2455 .ops = &clk_branch2_ops,
2456 .flags = CLK_SET_RATE_PARENT,
2457 }
2458 }
2459};
2460
2461static struct clk_branch gcc_camss_vfe0_ahb_clk = {
2462 .halt_reg = 0x58044,
2463 .halt_check = BRANCH_HALT,
2464 .clkr = {
2465 .enable_reg = 0x58044,
2466 .enable_mask = BIT(0),
2467 .hw.init = &(struct clk_init_data) {
2468 .name = "gcc_camss_vfe0_ahb_clk",
2469 .parent_hws = (const struct clk_hw*[]){
2470 &camss_top_ahb_clk_src.clkr.hw,
2471 },
2472 .num_parents = 1,
2473 .ops = &clk_branch2_ops,
2474 .flags = CLK_SET_RATE_PARENT,
2475 }
2476 }
2477};
2478
2479static struct clk_branch gcc_camss_vfe0_axi_clk = {
2480 .halt_reg = 0x58048,
2481 .halt_check = BRANCH_HALT,
2482 .clkr = {
2483 .enable_reg = 0x58048,
2484 .enable_mask = BIT(0),
2485 .hw.init = &(struct clk_init_data) {
2486 .name = "gcc_camss_vfe0_axi_clk",
2487 .ops = &clk_branch2_ops,
2488 }
2489 }
2490};
2491
2492static struct clk_branch gcc_camss_vfe0_clk = {
2493 .halt_reg = 0x58038,
2494 .halt_check = BRANCH_HALT,
2495 .clkr = {
2496 .enable_reg = 0x58038,
2497 .enable_mask = BIT(0),
2498 .hw.init = &(struct clk_init_data) {
2499 .name = "gcc_camss_vfe0_clk",
2500 .parent_hws = (const struct clk_hw*[]){
2501 &vfe0_clk_src.clkr.hw,
2502 },
2503 .num_parents = 1,
2504 .ops = &clk_branch2_ops,
2505 .flags = CLK_SET_RATE_PARENT,
2506 }
2507 }
2508};
2509
2510static struct clk_branch gcc_camss_vfe1_ahb_clk = {
2511 .halt_reg = 0x58060,
2512 .halt_check = BRANCH_HALT,
2513 .clkr = {
2514 .enable_reg = 0x58060,
2515 .enable_mask = BIT(0),
2516 .hw.init = &(struct clk_init_data) {
2517 .name = "gcc_camss_vfe1_ahb_clk",
2518 .parent_hws = (const struct clk_hw*[]){
2519 &camss_top_ahb_clk_src.clkr.hw,
2520 },
2521 .num_parents = 1,
2522 .ops = &clk_branch2_ops,
2523 .flags = CLK_SET_RATE_PARENT,
2524 }
2525 }
2526};
2527
2528static struct clk_branch gcc_camss_vfe1_axi_clk = {
2529 .halt_reg = 0x58068,
2530 .halt_check = BRANCH_HALT,
2531 .clkr = {
2532 .enable_reg = 0x58068,
2533 .enable_mask = BIT(0),
2534 .hw.init = &(struct clk_init_data) {
2535 .name = "gcc_camss_vfe1_axi_clk",
2536 .ops = &clk_branch2_ops,
2537 }
2538 }
2539};
2540
2541static struct clk_branch gcc_camss_vfe1_clk = {
2542 .halt_reg = 0x5805c,
2543 .halt_check = BRANCH_HALT,
2544 .clkr = {
2545 .enable_reg = 0x5805c,
2546 .enable_mask = BIT(0),
2547 .hw.init = &(struct clk_init_data) {
2548 .name = "gcc_camss_vfe1_clk",
2549 .parent_hws = (const struct clk_hw*[]){
2550 &vfe1_clk_src.clkr.hw,
2551 },
2552 .num_parents = 1,
2553 .ops = &clk_branch2_ops,
2554 .flags = CLK_SET_RATE_PARENT,
2555 }
2556 }
2557};
2558
2559static struct clk_branch gcc_cpp_tbu_clk = {
2560 .halt_reg = 0x12040,
2561 .halt_check = BRANCH_HALT_VOTED,
2562 .clkr = {
2563 .enable_reg = 0x4500c,
2564 .enable_mask = BIT(14),
2565 .hw.init = &(struct clk_init_data) {
2566 .name = "gcc_cpp_tbu_clk",
2567 .ops = &clk_branch2_ops,
2568 }
2569 }
2570};
2571
2572static struct clk_branch gcc_crypto_ahb_clk = {
2573 .halt_reg = 0x16024,
2574 .halt_check = BRANCH_HALT_VOTED,
2575 .clkr = {
2576 .enable_reg = 0x45004,
2577 .enable_mask = BIT(0),
2578 .hw.init = &(struct clk_init_data) {
2579 .name = "gcc_crypto_ahb_clk",
2580 .ops = &clk_branch2_ops,
2581 }
2582 }
2583};
2584
2585static struct clk_branch gcc_crypto_axi_clk = {
2586 .halt_reg = 0x16020,
2587 .halt_check = BRANCH_HALT_VOTED,
2588 .clkr = {
2589 .enable_reg = 0x45004,
2590 .enable_mask = BIT(1),
2591 .hw.init = &(struct clk_init_data) {
2592 .name = "gcc_crypto_axi_clk",
2593 .ops = &clk_branch2_ops,
2594 }
2595 }
2596};
2597
2598static struct clk_branch gcc_crypto_clk = {
2599 .halt_reg = 0x1601c,
2600 .halt_check = BRANCH_HALT_VOTED,
2601 .clkr = {
2602 .enable_reg = 0x45004,
2603 .enable_mask = BIT(2),
2604 .hw.init = &(struct clk_init_data) {
2605 .name = "gcc_crypto_clk",
2606 .parent_hws = (const struct clk_hw*[]){
2607 &crypto_clk_src.clkr.hw,
2608 },
2609 .num_parents = 1,
2610 .ops = &clk_branch2_ops,
2611 .flags = CLK_SET_RATE_PARENT,
2612 }
2613 }
2614};
2615
2616static struct clk_branch gcc_dcc_clk = {
2617 .halt_reg = 0x77004,
2618 .halt_check = BRANCH_HALT,
2619 .clkr = {
2620 .enable_reg = 0x77004,
2621 .enable_mask = BIT(0),
2622 .hw.init = &(struct clk_init_data) {
2623 .name = "gcc_dcc_clk",
2624 .ops = &clk_branch2_ops,
2625 }
2626 }
2627};
2628
2629static struct clk_branch gcc_gfx_tbu_clk = {
2630 .halt_reg = 0x12010,
2631 .halt_check = BRANCH_HALT_VOTED,
2632 .clkr = {
2633 .enable_reg = 0x4500c,
2634 .enable_mask = BIT(3),
2635 .hw.init = &(struct clk_init_data){
2636 .name = "gcc_gfx_tbu_clk",
2637 .ops = &clk_branch2_ops,
2638 },
2639 },
2640};
2641
2642static struct clk_branch gcc_gfx_tcu_clk = {
2643 .halt_reg = 0x12020,
2644 .halt_check = BRANCH_HALT_VOTED,
2645 .clkr = {
2646 .enable_reg = 0x4500c,
2647 .enable_mask = BIT(2),
2648 .hw.init = &(struct clk_init_data){
2649 .name = "gcc_gfx_tcu_clk",
2650 .ops = &clk_branch2_ops,
2651 },
2652 },
2653};
2654
2655static struct clk_branch gcc_gtcu_ahb_clk = {
2656 .halt_reg = 0x12044,
2657 .halt_check = BRANCH_HALT_VOTED,
2658 .clkr = {
2659 .enable_reg = 0x4500c,
2660 .enable_mask = BIT(13),
2661 .hw.init = &(struct clk_init_data){
2662 .name = "gcc_gtcu_ahb_clk",
2663 .ops = &clk_branch2_ops,
2664 },
2665 },
2666};
2667
2668static struct clk_branch gcc_gp1_clk = {
2669 .halt_reg = 0x08000,
2670 .halt_check = BRANCH_HALT,
2671 .clkr = {
2672 .enable_reg = 0x08000,
2673 .enable_mask = BIT(0),
2674 .hw.init = &(struct clk_init_data) {
2675 .name = "gcc_gp1_clk",
2676 .parent_hws = (const struct clk_hw*[]){
2677 &gp1_clk_src.clkr.hw,
2678 },
2679 .num_parents = 1,
2680 .ops = &clk_branch2_ops,
2681 .flags = CLK_SET_RATE_PARENT,
2682 }
2683 }
2684};
2685
2686static struct clk_branch gcc_gp2_clk = {
2687 .halt_reg = 0x09000,
2688 .halt_check = BRANCH_HALT,
2689 .clkr = {
2690 .enable_reg = 0x09000,
2691 .enable_mask = BIT(0),
2692 .hw.init = &(struct clk_init_data) {
2693 .name = "gcc_gp2_clk",
2694 .parent_hws = (const struct clk_hw*[]){
2695 &gp2_clk_src.clkr.hw,
2696 },
2697 .num_parents = 1,
2698 .ops = &clk_branch2_ops,
2699 .flags = CLK_SET_RATE_PARENT,
2700 }
2701 }
2702};
2703
2704static struct clk_branch gcc_gp3_clk = {
2705 .halt_reg = 0x0a000,
2706 .halt_check = BRANCH_HALT,
2707 .clkr = {
2708 .enable_reg = 0x0a000,
2709 .enable_mask = BIT(0),
2710 .hw.init = &(struct clk_init_data) {
2711 .name = "gcc_gp3_clk",
2712 .parent_hws = (const struct clk_hw*[]){
2713 &gp3_clk_src.clkr.hw,
2714 },
2715 .num_parents = 1,
2716 .ops = &clk_branch2_ops,
2717 .flags = CLK_SET_RATE_PARENT,
2718 }
2719 }
2720};
2721
2722static struct clk_branch gcc_jpeg_tbu_clk = {
2723 .halt_reg = 0x12034,
2724 .halt_check = BRANCH_HALT_VOTED,
2725 .clkr = {
2726 .enable_reg = 0x4500c,
2727 .enable_mask = BIT(10),
2728 .hw.init = &(struct clk_init_data) {
2729 .name = "gcc_jpeg_tbu_clk",
2730 .ops = &clk_branch2_ops,
2731 }
2732 }
2733};
2734
2735static struct clk_branch gcc_mdp_tbu_clk = {
2736 .halt_reg = 0x1201c,
2737 .halt_check = BRANCH_HALT_VOTED,
2738 .clkr = {
2739 .enable_reg = 0x4500c,
2740 .enable_mask = BIT(4),
2741 .hw.init = &(struct clk_init_data) {
2742 .name = "gcc_mdp_tbu_clk",
2743 .ops = &clk_branch2_ops,
2744 }
2745 }
2746};
2747
2748static struct clk_branch gcc_mdss_ahb_clk = {
2749 .halt_reg = 0x4d07c,
2750 .halt_check = BRANCH_HALT,
2751 .clkr = {
2752 .enable_reg = 0x4d07c,
2753 .enable_mask = BIT(0),
2754 .hw.init = &(struct clk_init_data) {
2755 .name = "gcc_mdss_ahb_clk",
2756 .ops = &clk_branch2_ops,
2757 }
2758 }
2759};
2760
2761static struct clk_branch gcc_mdss_axi_clk = {
2762 .halt_reg = 0x4d080,
2763 .halt_check = BRANCH_HALT,
2764 .clkr = {
2765 .enable_reg = 0x4d080,
2766 .enable_mask = BIT(0),
2767 .hw.init = &(struct clk_init_data) {
2768 .name = "gcc_mdss_axi_clk",
2769 .ops = &clk_branch2_ops,
2770 }
2771 }
2772};
2773
2774static struct clk_branch gcc_mdss_byte0_clk = {
2775 .halt_reg = 0x4d094,
2776 .halt_check = BRANCH_HALT,
2777 .clkr = {
2778 .enable_reg = 0x4d094,
2779 .enable_mask = BIT(0),
2780 .hw.init = &(struct clk_init_data) {
2781 .name = "gcc_mdss_byte0_clk",
2782 .parent_hws = (const struct clk_hw*[]){
2783 &byte0_clk_src.clkr.hw,
2784 },
2785 .num_parents = 1,
2786 .ops = &clk_branch2_ops,
2787 .flags = CLK_SET_RATE_PARENT,
2788 }
2789 }
2790};
2791
2792static struct clk_branch gcc_mdss_byte1_clk = {
2793 .halt_reg = 0x4d0a0,
2794 .halt_check = BRANCH_HALT,
2795 .clkr = {
2796 .enable_reg = 0x4d0a0,
2797 .enable_mask = BIT(0),
2798 .hw.init = &(struct clk_init_data){
2799 .name = "gcc_mdss_byte1_clk",
2800 .parent_hws = (const struct clk_hw*[]){
2801 &byte1_clk_src.clkr.hw,
2802 },
2803 .num_parents = 1,
2804 .ops = &clk_branch2_ops,
2805 .flags = CLK_SET_RATE_PARENT,
2806 },
2807 },
2808};
2809
2810static struct clk_branch gcc_mdss_esc0_clk = {
2811 .halt_reg = 0x4d098,
2812 .halt_check = BRANCH_HALT,
2813 .clkr = {
2814 .enable_reg = 0x4d098,
2815 .enable_mask = BIT(0),
2816 .hw.init = &(struct clk_init_data) {
2817 .name = "gcc_mdss_esc0_clk",
2818 .parent_hws = (const struct clk_hw*[]){
2819 &esc0_clk_src.clkr.hw,
2820 },
2821 .num_parents = 1,
2822 .ops = &clk_branch2_ops,
2823 .flags = CLK_SET_RATE_PARENT,
2824 }
2825 }
2826};
2827
2828static struct clk_branch gcc_mdss_esc1_clk = {
2829 .halt_reg = 0x4d09c,
2830 .halt_check = BRANCH_HALT,
2831 .clkr = {
2832 .enable_reg = 0x4d09c,
2833 .enable_mask = BIT(0),
2834 .hw.init = &(struct clk_init_data){
2835 .name = "gcc_mdss_esc1_clk",
2836 .parent_hws = (const struct clk_hw*[]){
2837 &esc1_clk_src.clkr.hw,
2838 },
2839 .num_parents = 1,
2840 .ops = &clk_branch2_ops,
2841 .flags = CLK_SET_RATE_PARENT,
2842 },
2843 },
2844};
2845
2846static struct clk_branch gcc_mdss_mdp_clk = {
2847 .halt_reg = 0x4d088,
2848 .halt_check = BRANCH_HALT,
2849 .clkr = {
2850 .enable_reg = 0x4d088,
2851 .enable_mask = BIT(0),
2852 .hw.init = &(struct clk_init_data) {
2853 .name = "gcc_mdss_mdp_clk",
2854 .parent_hws = (const struct clk_hw*[]){
2855 &mdp_clk_src.clkr.hw,
2856 },
2857 .num_parents = 1,
2858 .ops = &clk_branch2_ops,
2859 .flags = CLK_SET_RATE_PARENT,
2860 }
2861 }
2862};
2863
2864static struct clk_branch gcc_mdss_pclk0_clk = {
2865 .halt_reg = 0x4d084,
2866 .halt_check = BRANCH_HALT,
2867 .clkr = {
2868 .enable_reg = 0x4d084,
2869 .enable_mask = BIT(0),
2870 .hw.init = &(struct clk_init_data) {
2871 .name = "gcc_mdss_pclk0_clk",
2872 .parent_hws = (const struct clk_hw*[]){
2873 &pclk0_clk_src.clkr.hw,
2874 },
2875 .num_parents = 1,
2876 .ops = &clk_branch2_ops,
2877 .flags = CLK_SET_RATE_PARENT,
2878 }
2879 }
2880};
2881
2882static struct clk_branch gcc_mdss_pclk1_clk = {
2883 .halt_reg = 0x4d0a4,
2884 .halt_check = BRANCH_HALT,
2885 .clkr = {
2886 .enable_reg = 0x4d0a4,
2887 .enable_mask = BIT(0),
2888 .hw.init = &(struct clk_init_data){
2889 .name = "gcc_mdss_pclk1_clk",
2890 .parent_hws = (const struct clk_hw*[]){
2891 &pclk1_clk_src.clkr.hw,
2892 },
2893 .num_parents = 1,
2894 .ops = &clk_branch2_ops,
2895 .flags = CLK_SET_RATE_PARENT,
2896 },
2897 },
2898};
2899
2900static struct clk_branch gcc_mdss_vsync_clk = {
2901 .halt_reg = 0x4d090,
2902 .halt_check = BRANCH_HALT,
2903 .clkr = {
2904 .enable_reg = 0x4d090,
2905 .enable_mask = BIT(0),
2906 .hw.init = &(struct clk_init_data) {
2907 .name = "gcc_mdss_vsync_clk",
2908 .parent_hws = (const struct clk_hw*[]){
2909 &vsync_clk_src.clkr.hw,
2910 },
2911 .num_parents = 1,
2912 .ops = &clk_branch2_ops,
2913 .flags = CLK_SET_RATE_PARENT,
2914 }
2915 }
2916};
2917
2918static struct clk_branch gcc_mss_cfg_ahb_clk = {
2919 .halt_reg = 0x49000,
2920 .halt_check = BRANCH_HALT,
2921 .clkr = {
2922 .enable_reg = 0x49000,
2923 .enable_mask = BIT(0),
2924 .hw.init = &(struct clk_init_data) {
2925 .name = "gcc_mss_cfg_ahb_clk",
2926 .ops = &clk_branch2_ops,
2927 }
2928 }
2929};
2930
2931static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
2932 .halt_reg = 0x49004,
2933 .halt_check = BRANCH_HALT,
2934 .clkr = {
2935 .enable_reg = 0x49004,
2936 .enable_mask = BIT(0),
2937 .hw.init = &(struct clk_init_data) {
2938 .name = "gcc_mss_q6_bimc_axi_clk",
2939 .ops = &clk_branch2_ops,
2940 }
2941 }
2942};
2943
2944static struct clk_branch gcc_oxili_ahb_clk = {
2945 .halt_reg = 0x59028,
2946 .halt_check = BRANCH_HALT,
2947 .clkr = {
2948 .enable_reg = 0x59028,
2949 .enable_mask = BIT(0),
2950 .hw.init = &(struct clk_init_data) {
2951 .name = "gcc_oxili_ahb_clk",
2952 .ops = &clk_branch2_ops,
2953 }
2954 }
2955};
2956
2957static struct clk_branch gcc_oxili_aon_clk = {
2958 .halt_reg = 0x5904c,
2959 .halt_check = BRANCH_HALT,
2960 .clkr = {
2961 .enable_reg = 0x5904c,
2962 .enable_mask = BIT(0),
2963 .hw.init = &(struct clk_init_data){
2964 .name = "gcc_oxili_aon_clk",
2965 .parent_hws = (const struct clk_hw*[]){
2966 &gfx3d_clk_src.clkr.hw,
2967 },
2968 .num_parents = 1,
2969 .ops = &clk_branch2_ops,
2970 .flags = CLK_SET_RATE_PARENT,
2971 },
2972 },
2973};
2974
2975static struct clk_branch gcc_oxili_gfx3d_clk = {
2976 .halt_reg = 0x59020,
2977 .halt_check = BRANCH_HALT,
2978 .clkr = {
2979 .enable_reg = 0x59020,
2980 .enable_mask = BIT(0),
2981 .hw.init = &(struct clk_init_data) {
2982 .name = "gcc_oxili_gfx3d_clk",
2983 .parent_hws = (const struct clk_hw*[]){
2984 &gfx3d_clk_src.clkr.hw,
2985 },
2986 .num_parents = 1,
2987 .ops = &clk_branch2_ops,
2988 .flags = CLK_SET_RATE_PARENT,
2989 }
2990 }
2991};
2992
2993static struct clk_branch gcc_oxili_timer_clk = {
2994 .halt_reg = 0x59040,
2995 .halt_check = BRANCH_HALT,
2996 .clkr = {
2997 .enable_reg = 0x59040,
2998 .enable_mask = BIT(0),
2999 .hw.init = &(struct clk_init_data){
3000 .name = "gcc_oxili_timer_clk",
3001 .ops = &clk_branch2_ops,
3002 },
3003 },
3004};
3005
3006static struct clk_branch gcc_pdm2_clk = {
3007 .halt_reg = 0x4400c,
3008 .halt_check = BRANCH_HALT,
3009 .clkr = {
3010 .enable_reg = 0x4400c,
3011 .enable_mask = BIT(0),
3012 .hw.init = &(struct clk_init_data) {
3013 .name = "gcc_pdm2_clk",
3014 .parent_hws = (const struct clk_hw*[]){
3015 &pdm2_clk_src.clkr.hw,
3016 },
3017 .num_parents = 1,
3018 .ops = &clk_branch2_ops,
3019 .flags = CLK_SET_RATE_PARENT,
3020 }
3021 }
3022};
3023
3024static struct clk_branch gcc_pdm_ahb_clk = {
3025 .halt_reg = 0x44004,
3026 .halt_check = BRANCH_HALT,
3027 .clkr = {
3028 .enable_reg = 0x44004,
3029 .enable_mask = BIT(0),
3030 .hw.init = &(struct clk_init_data) {
3031 .name = "gcc_pdm_ahb_clk",
3032 .ops = &clk_branch2_ops,
3033 }
3034 }
3035};
3036
3037static struct clk_branch gcc_prng_ahb_clk = {
3038 .halt_reg = 0x13004,
3039 .halt_check = BRANCH_HALT_VOTED,
3040 .clkr = {
3041 .enable_reg = 0x45004,
3042 .enable_mask = BIT(8),
3043 .hw.init = &(struct clk_init_data) {
3044 .name = "gcc_prng_ahb_clk",
3045 .ops = &clk_branch2_ops,
3046 }
3047 }
3048};
3049
3050static struct clk_branch gcc_qdss_dap_clk = {
3051 .halt_reg = 0x29084,
3052 .halt_check = BRANCH_HALT_VOTED,
3053 .clkr = {
3054 .enable_reg = 0x45004,
3055 .enable_mask = BIT(11),
3056 .hw.init = &(struct clk_init_data) {
3057 .name = "gcc_qdss_dap_clk",
3058 .ops = &clk_branch2_ops,
3059 }
3060 }
3061};
3062
3063static struct clk_branch gcc_sdcc1_ice_core_clk = {
3064 .halt_reg = 0x5d014,
3065 .halt_check = BRANCH_HALT,
3066 .clkr = {
3067 .enable_reg = 0x5d014,
3068 .enable_mask = BIT(0),
3069 .hw.init = &(struct clk_init_data) {
3070 .name = "gcc_sdcc1_ice_core_clk",
3071 .parent_hws = (const struct clk_hw*[]){
3072 &sdcc1_ice_core_clk_src.clkr.hw,
3073 },
3074 .num_parents = 1,
3075 .ops = &clk_branch2_ops,
3076 .flags = CLK_SET_RATE_PARENT,
3077 }
3078 }
3079};
3080
3081static struct clk_branch gcc_sdcc1_ahb_clk = {
3082 .halt_reg = 0x4201c,
3083 .halt_check = BRANCH_HALT,
3084 .clkr = {
3085 .enable_reg = 0x4201c,
3086 .enable_mask = BIT(0),
3087 .hw.init = &(struct clk_init_data) {
3088 .name = "gcc_sdcc1_ahb_clk",
3089 .ops = &clk_branch2_ops,
3090 }
3091 }
3092};
3093
3094static struct clk_branch gcc_sdcc2_ahb_clk = {
3095 .halt_reg = 0x4301c,
3096 .halt_check = BRANCH_HALT,
3097 .clkr = {
3098 .enable_reg = 0x4301c,
3099 .enable_mask = BIT(0),
3100 .hw.init = &(struct clk_init_data) {
3101 .name = "gcc_sdcc2_ahb_clk",
3102 .ops = &clk_branch2_ops,
3103 }
3104 }
3105};
3106
3107static struct clk_branch gcc_sdcc1_apps_clk = {
3108 .halt_reg = 0x42018,
3109 .halt_check = BRANCH_HALT,
3110 .clkr = {
3111 .enable_reg = 0x42018,
3112 .enable_mask = BIT(0),
3113 .hw.init = &(struct clk_init_data) {
3114 .name = "gcc_sdcc1_apps_clk",
3115 .parent_hws = (const struct clk_hw*[]){
3116 &sdcc1_apps_clk_src.clkr.hw,
3117 },
3118 .num_parents = 1,
3119 .ops = &clk_branch2_ops,
3120 .flags = CLK_SET_RATE_PARENT,
3121 }
3122 }
3123};
3124
3125static struct clk_branch gcc_sdcc2_apps_clk = {
3126 .halt_reg = 0x43018,
3127 .halt_check = BRANCH_HALT,
3128 .clkr = {
3129 .enable_reg = 0x43018,
3130 .enable_mask = BIT(0),
3131 .hw.init = &(struct clk_init_data) {
3132 .name = "gcc_sdcc2_apps_clk",
3133 .parent_hws = (const struct clk_hw*[]){
3134 &sdcc2_apps_clk_src.clkr.hw,
3135 },
3136 .num_parents = 1,
3137 .ops = &clk_branch2_ops,
3138 .flags = CLK_SET_RATE_PARENT,
3139 }
3140 }
3141};
3142
3143static struct clk_branch gcc_smmu_cfg_clk = {
3144 .halt_reg = 0x12038,
3145 .halt_check = BRANCH_HALT_VOTED,
3146 .clkr = {
3147 .enable_reg = 0x4500c,
3148 .enable_mask = BIT(12),
3149 .hw.init = &(struct clk_init_data) {
3150 .name = "gcc_smmu_cfg_clk",
3151 .ops = &clk_branch2_ops,
3152 }
3153 }
3154};
3155
3156static struct clk_branch gcc_usb2a_phy_sleep_clk = {
3157 .halt_reg = 0x4102c,
3158 .clkr = {
3159 .enable_reg = 0x4102c,
3160 .enable_mask = BIT(0),
3161 .hw.init = &(struct clk_init_data){
3162 .name = "gcc_usb2a_phy_sleep_clk",
3163 .ops = &clk_branch2_ops,
3164 },
3165 },
3166};
3167
3168static struct clk_branch gcc_usb_hs_ahb_clk = {
3169 .halt_reg = 0x41008,
3170 .clkr = {
3171 .enable_reg = 0x41008,
3172 .enable_mask = BIT(0),
3173 .hw.init = &(struct clk_init_data){
3174 .name = "gcc_usb_hs_ahb_clk",
3175 .ops = &clk_branch2_ops,
3176 },
3177 },
3178};
3179
3180static struct clk_branch gcc_usb_hs_phy_cfg_ahb_clk = {
3181 .halt_reg = 0x41030,
3182 .clkr = {
3183 .enable_reg = 0x41030,
3184 .enable_mask = BIT(0),
3185 .hw.init = &(struct clk_init_data){
3186 .name = "gcc_usb_hs_phy_cfg_ahb_clk",
3187 .ops = &clk_branch2_ops,
3188 },
3189 },
3190};
3191
3192static struct clk_branch gcc_usb_hs_system_clk = {
3193 .halt_reg = 0x41004,
3194 .clkr = {
3195 .enable_reg = 0x41004,
3196 .enable_mask = BIT(0),
3197 .hw.init = &(struct clk_init_data){
3198 .name = "gcc_usb_hs_system_clk",
3199 .parent_hws = (const struct clk_hw*[]){
3200 &usb_hs_system_clk_src.clkr.hw,
3201 },
3202 .num_parents = 1,
3203 .flags = CLK_SET_RATE_PARENT,
3204 .ops = &clk_branch2_ops,
3205 },
3206 },
3207};
3208
3209static struct clk_branch gcc_venus0_ahb_clk = {
3210 .halt_reg = 0x4c020,
3211 .halt_check = BRANCH_HALT,
3212 .clkr = {
3213 .enable_reg = 0x4c020,
3214 .enable_mask = BIT(0),
3215 .hw.init = &(struct clk_init_data) {
3216 .name = "gcc_venus0_ahb_clk",
3217 .ops = &clk_branch2_ops,
3218 }
3219 }
3220};
3221
3222static struct clk_branch gcc_venus0_axi_clk = {
3223 .halt_reg = 0x4c024,
3224 .halt_check = BRANCH_HALT,
3225 .clkr = {
3226 .enable_reg = 0x4c024,
3227 .enable_mask = BIT(0),
3228 .hw.init = &(struct clk_init_data) {
3229 .name = "gcc_venus0_axi_clk",
3230 .ops = &clk_branch2_ops,
3231 }
3232 }
3233};
3234
3235static struct clk_branch gcc_venus0_core0_vcodec0_clk = {
3236 .halt_reg = 0x4c02c,
3237 .halt_check = BRANCH_HALT,
3238 .clkr = {
3239 .enable_reg = 0x4c02c,
3240 .enable_mask = BIT(0),
3241 .hw.init = &(struct clk_init_data) {
3242 .name = "gcc_venus0_core0_vcodec0_clk",
3243 .parent_hws = (const struct clk_hw*[]){
3244 &vcodec0_clk_src.clkr.hw,
3245 },
3246 .num_parents = 1,
3247 .ops = &clk_branch2_ops,
3248 .flags = CLK_SET_RATE_PARENT,
3249 }
3250 }
3251};
3252
3253static struct clk_branch gcc_venus0_vcodec0_clk = {
3254 .halt_reg = 0x4c01c,
3255 .halt_check = BRANCH_HALT,
3256 .clkr = {
3257 .enable_reg = 0x4c01c,
3258 .enable_mask = BIT(0),
3259 .hw.init = &(struct clk_init_data) {
3260 .name = "gcc_venus0_vcodec0_clk",
3261 .parent_hws = (const struct clk_hw*[]){
3262 &vcodec0_clk_src.clkr.hw,
3263 },
3264 .num_parents = 1,
3265 .ops = &clk_branch2_ops,
3266 .flags = CLK_SET_RATE_PARENT,
3267 }
3268 }
3269};
3270
3271static struct clk_branch gcc_venus_tbu_clk = {
3272 .halt_reg = 0x12014,
3273 .halt_check = BRANCH_HALT_VOTED,
3274 .clkr = {
3275 .enable_reg = 0x4500c,
3276 .enable_mask = BIT(5),
3277 .hw.init = &(struct clk_init_data) {
3278 .name = "gcc_venus_tbu_clk",
3279 .ops = &clk_branch2_ops,
3280 }
3281 }
3282};
3283
3284static struct clk_branch gcc_vfe1_tbu_clk = {
3285 .halt_reg = 0x12090,
3286 .halt_check = BRANCH_HALT_VOTED,
3287 .clkr = {
3288 .enable_reg = 0x4500c,
3289 .enable_mask = BIT(17),
3290 .hw.init = &(struct clk_init_data) {
3291 .name = "gcc_vfe1_tbu_clk",
3292 .ops = &clk_branch2_ops,
3293 }
3294 }
3295};
3296
3297static struct clk_branch gcc_vfe_tbu_clk = {
3298 .halt_reg = 0x1203c,
3299 .halt_check = BRANCH_HALT_VOTED,
3300 .clkr = {
3301 .enable_reg = 0x4500c,
3302 .enable_mask = BIT(9),
3303 .hw.init = &(struct clk_init_data) {
3304 .name = "gcc_vfe_tbu_clk",
3305 .ops = &clk_branch2_ops,
3306 }
3307 }
3308};
3309
3310static struct gdsc venus_gdsc = {
3311 .gdscr = 0x4c018,
3312 .cxcs = (unsigned int []){ 0x4c024, 0x4c01c },
3313 .cxc_count = 2,
3314 .pd = {
3315 .name = "venus_gdsc",
3316 },
3317 .pwrsts = PWRSTS_OFF_ON,
3318};
3319
3320static struct gdsc venus_core0_gdsc = {
3321 .gdscr = 0x4c028,
3322 .cxcs = (unsigned int []){ 0x4c02c },
3323 .cxc_count = 1,
3324 .pd = {
3325 .name = "venus_core0",
3326 },
3327 .flags = HW_CTRL,
3328 .pwrsts = PWRSTS_OFF_ON,
3329};
3330
3331static struct gdsc mdss_gdsc = {
3332 .gdscr = 0x4d078,
3333 .cxcs = (unsigned int []){ 0x4d080, 0x4d088 },
3334 .cxc_count = 2,
3335 .pd = {
3336 .name = "mdss_gdsc",
3337 },
3338 .pwrsts = PWRSTS_OFF_ON,
3339};
3340
3341static struct gdsc jpeg_gdsc = {
3342 .gdscr = 0x5701c,
3343 .cxcs = (unsigned int []){ 0x57020, 0x57028 },
3344 .cxc_count = 2,
3345 .pd = {
3346 .name = "jpeg_gdsc",
3347 },
3348 .pwrsts = PWRSTS_OFF_ON,
3349};
3350
3351static struct gdsc vfe0_gdsc = {
3352 .gdscr = 0x58034,
3353 .cxcs = (unsigned int []){ 0x58038, 0x58048, 0x5600c, 0x58050 },
3354 .cxc_count = 4,
3355 .pd = {
3356 .name = "vfe0_gdsc",
3357 },
3358 .pwrsts = PWRSTS_OFF_ON,
3359};
3360
3361static struct gdsc vfe1_gdsc = {
3362 .gdscr = 0x5806c,
3363 .cxcs = (unsigned int []){ 0x5805c, 0x58068, 0x5600c, 0x58074 },
3364 .cxc_count = 4,
3365 .pd = {
3366 .name = "vfe1_gdsc",
3367 },
3368 .pwrsts = PWRSTS_OFF_ON,
3369};
3370
3371static struct gdsc oxili_gx_gdsc = {
3372 .gdscr = 0x5901c,
3373 .clamp_io_ctrl = 0x5b00c,
3374 .cxcs = (unsigned int []){ 0x59000, 0x59020 },
3375 .cxc_count = 2,
3376 .pd = {
3377 .name = "oxili_gx_gdsc",
3378 },
3379 .pwrsts = PWRSTS_OFF_ON,
3380 .flags = CLAMP_IO,
3381};
3382
3383static struct gdsc oxili_gx_gdsc_msm8937 = {
3384 .gdscr = 0x5901c,
3385 .clamp_io_ctrl = 0x5b00c,
3386 .cxcs = (unsigned int []){ 0x59000 },
3387 .cxc_count = 1,
3388 .pd = {
3389 .name = "oxili_gx_gdsc",
3390 },
3391 .pwrsts = PWRSTS_OFF_ON,
3392 .flags = CLAMP_IO,
3393};
3394
3395static struct gdsc oxili_cx_gdsc = {
3396 .gdscr = 0x59044,
3397 .cxcs = (unsigned int []){ 0x59020 },
3398 .cxc_count = 1,
3399 .pd = {
3400 .name = "oxili_cx_gdsc",
3401 },
3402 .pwrsts = PWRSTS_OFF_ON,
3403};
3404
3405static struct gdsc cpp_gdsc = {
3406 .gdscr = 0x58078,
3407 .cxcs = (unsigned int []){ 0x5803c, 0x58064 },
3408 .cxc_count = 2,
3409 .pd = {
3410 .name = "cpp_gdsc",
3411 },
3412 .flags = ALWAYS_ON,
3413 .pwrsts = PWRSTS_OFF_ON,
3414};
3415
3416static struct clk_regmap *gcc_msm8917_clocks[] = {
3417 [GPLL0] = &gpll0.clkr,
3418 [GPLL0_EARLY] = &gpll0_early.clkr,
3419 [GPLL0_SLEEP_CLK_SRC] = &gpll0_sleep_clk_src.clkr,
3420 [GPLL3] = &gpll3.clkr,
3421 [GPLL3_EARLY] = &gpll3_early.clkr,
3422 [GPLL4] = &gpll4.clkr,
3423 [GPLL4_EARLY] = &gpll4_early.clkr,
3424 [GPLL6] = &gpll6,
3425 [GPLL6_EARLY] = &gpll6_early.clkr,
3426 [APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
3427 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
3428 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
3429 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
3430 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
3431 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
3432 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
3433 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
3434 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
3435 [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
3436 [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
3437 [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
3438 [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
3439 [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
3440 [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
3441 [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
3442 [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
3443 [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
3444 [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
3445 [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
3446 [CAMSS_TOP_AHB_CLK_SRC] = &camss_top_ahb_clk_src.clkr,
3447 [CCI_CLK_SRC] = &cci_clk_src.clkr,
3448 [CPP_CLK_SRC] = &cpp_clk_src.clkr,
3449 [CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
3450 [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
3451 [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
3452 [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
3453 [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
3454 [CSI2_CLK_SRC] = &csi2_clk_src.clkr,
3455 [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
3456 [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
3457 [GP1_CLK_SRC] = &gp1_clk_src.clkr,
3458 [GP2_CLK_SRC] = &gp2_clk_src.clkr,
3459 [GP3_CLK_SRC] = &gp3_clk_src.clkr,
3460 [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
3461 [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
3462 [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
3463 [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
3464 [MDP_CLK_SRC] = &mdp_clk_src.clkr,
3465 [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
3466 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
3467 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
3468 [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
3469 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
3470 [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
3471 [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
3472 [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
3473 [VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
3474 [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
3475 [GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr,
3476 [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
3477 [GCC_BIMC_GPU_CLK] = &gcc_bimc_gpu_clk.clkr,
3478 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
3479 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
3480 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
3481 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
3482 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
3483 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
3484 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
3485 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
3486 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
3487 [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
3488 [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
3489 [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
3490 [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
3491 [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
3492 [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
3493 [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
3494 [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
3495 [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
3496 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3497 [GCC_CAMSS_AHB_CLK] = &gcc_camss_ahb_clk.clkr,
3498 [GCC_CAMSS_CCI_AHB_CLK] = &gcc_camss_cci_ahb_clk.clkr,
3499 [GCC_CAMSS_CCI_CLK] = &gcc_camss_cci_clk.clkr,
3500 [GCC_CAMSS_CPP_AHB_CLK] = &gcc_camss_cpp_ahb_clk.clkr,
3501 [GCC_CAMSS_CPP_CLK] = &gcc_camss_cpp_clk.clkr,
3502 [GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr,
3503 [GCC_CAMSS_CSI0PHY_CLK] = &gcc_camss_csi0phy_clk.clkr,
3504 [GCC_CAMSS_CSI0PIX_CLK] = &gcc_camss_csi0pix_clk.clkr,
3505 [GCC_CAMSS_CSI0RDI_CLK] = &gcc_camss_csi0rdi_clk.clkr,
3506 [GCC_CAMSS_CSI0_AHB_CLK] = &gcc_camss_csi0_ahb_clk.clkr,
3507 [GCC_CAMSS_CSI0_CLK] = &gcc_camss_csi0_clk.clkr,
3508 [GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr,
3509 [GCC_CAMSS_CSI1PHY_CLK] = &gcc_camss_csi1phy_clk.clkr,
3510 [GCC_CAMSS_CSI1PIX_CLK] = &gcc_camss_csi1pix_clk.clkr,
3511 [GCC_CAMSS_CSI1RDI_CLK] = &gcc_camss_csi1rdi_clk.clkr,
3512 [GCC_CAMSS_CSI1_AHB_CLK] = &gcc_camss_csi1_ahb_clk.clkr,
3513 [GCC_CAMSS_CSI1_CLK] = &gcc_camss_csi1_clk.clkr,
3514 [GCC_CAMSS_CSI2PHY_CLK] = &gcc_camss_csi2phy_clk.clkr,
3515 [GCC_CAMSS_CSI2PIX_CLK] = &gcc_camss_csi2pix_clk.clkr,
3516 [GCC_CAMSS_CSI2RDI_CLK] = &gcc_camss_csi2rdi_clk.clkr,
3517 [GCC_CAMSS_CSI2_AHB_CLK] = &gcc_camss_csi2_ahb_clk.clkr,
3518 [GCC_CAMSS_CSI2_CLK] = &gcc_camss_csi2_clk.clkr,
3519 [GCC_CAMSS_CSI_VFE0_CLK] = &gcc_camss_csi_vfe0_clk.clkr,
3520 [GCC_CAMSS_CSI_VFE1_CLK] = &gcc_camss_csi_vfe1_clk.clkr,
3521 [GCC_CAMSS_GP0_CLK] = &gcc_camss_gp0_clk.clkr,
3522 [GCC_CAMSS_GP1_CLK] = &gcc_camss_gp1_clk.clkr,
3523 [GCC_CAMSS_ISPIF_AHB_CLK] = &gcc_camss_ispif_ahb_clk.clkr,
3524 [GCC_CAMSS_JPEG0_CLK] = &gcc_camss_jpeg0_clk.clkr,
3525 [GCC_CAMSS_JPEG_AHB_CLK] = &gcc_camss_jpeg_ahb_clk.clkr,
3526 [GCC_CAMSS_JPEG_AXI_CLK] = &gcc_camss_jpeg_axi_clk.clkr,
3527 [GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr,
3528 [GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr,
3529 [GCC_CAMSS_MCLK2_CLK] = &gcc_camss_mclk2_clk.clkr,
3530 [GCC_CAMSS_MICRO_AHB_CLK] = &gcc_camss_micro_ahb_clk.clkr,
3531 [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr,
3532 [GCC_CAMSS_VFE0_AHB_CLK] = &gcc_camss_vfe0_ahb_clk.clkr,
3533 [GCC_CAMSS_VFE0_AXI_CLK] = &gcc_camss_vfe0_axi_clk.clkr,
3534 [GCC_CAMSS_VFE0_CLK] = &gcc_camss_vfe0_clk.clkr,
3535 [GCC_CAMSS_VFE1_AHB_CLK] = &gcc_camss_vfe1_ahb_clk.clkr,
3536 [GCC_CAMSS_VFE1_AXI_CLK] = &gcc_camss_vfe1_axi_clk.clkr,
3537 [GCC_CAMSS_VFE1_CLK] = &gcc_camss_vfe1_clk.clkr,
3538 [GCC_CPP_TBU_CLK] = &gcc_cpp_tbu_clk.clkr,
3539 [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
3540 [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
3541 [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
3542 [GCC_DCC_CLK] = &gcc_dcc_clk.clkr,
3543 [GCC_GFX_TBU_CLK] = &gcc_gfx_tbu_clk.clkr,
3544 [GCC_GFX_TCU_CLK] = &gcc_gfx_tcu_clk.clkr,
3545 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3546 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3547 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3548 [GCC_GTCU_AHB_CLK] = &gcc_gtcu_ahb_clk.clkr,
3549 [GCC_JPEG_TBU_CLK] = &gcc_jpeg_tbu_clk.clkr,
3550 [GCC_MDP_TBU_CLK] = &gcc_mdp_tbu_clk.clkr,
3551 [GCC_MDSS_AHB_CLK] = &gcc_mdss_ahb_clk.clkr,
3552 [GCC_MDSS_AXI_CLK] = &gcc_mdss_axi_clk.clkr,
3553 [GCC_MDSS_BYTE0_CLK] = &gcc_mdss_byte0_clk.clkr,
3554 [GCC_MDSS_ESC0_CLK] = &gcc_mdss_esc0_clk.clkr,
3555 [GCC_MDSS_MDP_CLK] = &gcc_mdss_mdp_clk.clkr,
3556 [GCC_MDSS_PCLK0_CLK] = &gcc_mdss_pclk0_clk.clkr,
3557 [GCC_MDSS_VSYNC_CLK] = &gcc_mdss_vsync_clk.clkr,
3558 [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
3559 [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
3560 [GCC_OXILI_AHB_CLK] = &gcc_oxili_ahb_clk.clkr,
3561 [GCC_OXILI_GFX3D_CLK] = &gcc_oxili_gfx3d_clk.clkr,
3562 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3563 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3564 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3565 [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
3566 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
3567 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
3568 [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
3569 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3570 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3571 [GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr,
3572 [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
3573 [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
3574 [GCC_USB_HS_PHY_CFG_AHB_CLK] = &gcc_usb_hs_phy_cfg_ahb_clk.clkr,
3575 [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
3576 [GCC_VENUS0_AHB_CLK] = &gcc_venus0_ahb_clk.clkr,
3577 [GCC_VENUS0_AXI_CLK] = &gcc_venus0_axi_clk.clkr,
3578 [GCC_VENUS0_CORE0_VCODEC0_CLK] = &gcc_venus0_core0_vcodec0_clk.clkr,
3579 [GCC_VENUS0_VCODEC0_CLK] = &gcc_venus0_vcodec0_clk.clkr,
3580 [GCC_VENUS_TBU_CLK] = &gcc_venus_tbu_clk.clkr,
3581 [GCC_VFE1_TBU_CLK] = &gcc_vfe1_tbu_clk.clkr,
3582 [GCC_VFE_TBU_CLK] = &gcc_vfe_tbu_clk.clkr,
3583};
3584
3585static struct clk_regmap *gcc_msm8937_clocks[] = {
3586 [GPLL0] = &gpll0.clkr,
3587 [GPLL0_EARLY] = &gpll0_early.clkr,
3588 [GPLL0_SLEEP_CLK_SRC] = &gpll0_sleep_clk_src.clkr,
3589 [GPLL3] = &gpll3.clkr,
3590 [GPLL3_EARLY] = &gpll3_early.clkr,
3591 [GPLL4] = &gpll4.clkr,
3592 [GPLL4_EARLY] = &gpll4_early.clkr,
3593 [GPLL6] = &gpll6,
3594 [GPLL6_EARLY] = &gpll6_early.clkr,
3595 [APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
3596 [MSM8937_BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
3597 [MSM8937_BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
3598 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
3599 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
3600 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
3601 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
3602 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
3603 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
3604 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
3605 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
3606 [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
3607 [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
3608 [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
3609 [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
3610 [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
3611 [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
3612 [MSM8937_BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
3613 [MSM8937_BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
3614 [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
3615 [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
3616 [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
3617 [MSM8937_BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
3618 [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
3619 [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
3620 [CAMSS_TOP_AHB_CLK_SRC] = &camss_top_ahb_clk_src.clkr,
3621 [CCI_CLK_SRC] = &cci_clk_src.clkr,
3622 [CPP_CLK_SRC] = &cpp_clk_src.clkr,
3623 [CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
3624 [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
3625 [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
3626 [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
3627 [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
3628 [CSI2_CLK_SRC] = &csi2_clk_src.clkr,
3629 [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
3630 [MSM8937_ESC1_CLK_SRC] = &esc1_clk_src.clkr,
3631 [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
3632 [GP1_CLK_SRC] = &gp1_clk_src.clkr,
3633 [GP2_CLK_SRC] = &gp2_clk_src.clkr,
3634 [GP3_CLK_SRC] = &gp3_clk_src.clkr,
3635 [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
3636 [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
3637 [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
3638 [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
3639 [MDP_CLK_SRC] = &mdp_clk_src.clkr,
3640 [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
3641 [MSM8937_PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
3642 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
3643 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
3644 [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
3645 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
3646 [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
3647 [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
3648 [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
3649 [VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
3650 [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
3651 [GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr,
3652 [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
3653 [GCC_BIMC_GPU_CLK] = &gcc_bimc_gpu_clk.clkr,
3654 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
3655 [MSM8937_GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
3656 [MSM8937_GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
3657 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
3658 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
3659 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
3660 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
3661 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
3662 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
3663 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
3664 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
3665 [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
3666 [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
3667 [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
3668 [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
3669 [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
3670 [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
3671 [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
3672 [MSM8937_GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
3673 [MSM8937_GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
3674 [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
3675 [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
3676 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3677 [GCC_CAMSS_AHB_CLK] = &gcc_camss_ahb_clk.clkr,
3678 [GCC_CAMSS_CCI_AHB_CLK] = &gcc_camss_cci_ahb_clk.clkr,
3679 [GCC_CAMSS_CCI_CLK] = &gcc_camss_cci_clk.clkr,
3680 [GCC_CAMSS_CPP_AHB_CLK] = &gcc_camss_cpp_ahb_clk.clkr,
3681 [GCC_CAMSS_CPP_CLK] = &gcc_camss_cpp_clk.clkr,
3682 [GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr,
3683 [GCC_CAMSS_CSI0PHY_CLK] = &gcc_camss_csi0phy_clk.clkr,
3684 [GCC_CAMSS_CSI0PIX_CLK] = &gcc_camss_csi0pix_clk.clkr,
3685 [GCC_CAMSS_CSI0RDI_CLK] = &gcc_camss_csi0rdi_clk.clkr,
3686 [GCC_CAMSS_CSI0_AHB_CLK] = &gcc_camss_csi0_ahb_clk.clkr,
3687 [GCC_CAMSS_CSI0_CLK] = &gcc_camss_csi0_clk.clkr,
3688 [GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr,
3689 [GCC_CAMSS_CSI1PHY_CLK] = &gcc_camss_csi1phy_clk.clkr,
3690 [GCC_CAMSS_CSI1PIX_CLK] = &gcc_camss_csi1pix_clk.clkr,
3691 [GCC_CAMSS_CSI1RDI_CLK] = &gcc_camss_csi1rdi_clk.clkr,
3692 [GCC_CAMSS_CSI1_AHB_CLK] = &gcc_camss_csi1_ahb_clk.clkr,
3693 [GCC_CAMSS_CSI1_CLK] = &gcc_camss_csi1_clk.clkr,
3694 [GCC_CAMSS_CSI2PHY_CLK] = &gcc_camss_csi2phy_clk.clkr,
3695 [GCC_CAMSS_CSI2PIX_CLK] = &gcc_camss_csi2pix_clk.clkr,
3696 [GCC_CAMSS_CSI2RDI_CLK] = &gcc_camss_csi2rdi_clk.clkr,
3697 [GCC_CAMSS_CSI2_AHB_CLK] = &gcc_camss_csi2_ahb_clk.clkr,
3698 [GCC_CAMSS_CSI2_CLK] = &gcc_camss_csi2_clk.clkr,
3699 [GCC_CAMSS_CSI_VFE0_CLK] = &gcc_camss_csi_vfe0_clk.clkr,
3700 [GCC_CAMSS_CSI_VFE1_CLK] = &gcc_camss_csi_vfe1_clk.clkr,
3701 [GCC_CAMSS_GP0_CLK] = &gcc_camss_gp0_clk.clkr,
3702 [GCC_CAMSS_GP1_CLK] = &gcc_camss_gp1_clk.clkr,
3703 [GCC_CAMSS_ISPIF_AHB_CLK] = &gcc_camss_ispif_ahb_clk.clkr,
3704 [GCC_CAMSS_JPEG0_CLK] = &gcc_camss_jpeg0_clk.clkr,
3705 [GCC_CAMSS_JPEG_AHB_CLK] = &gcc_camss_jpeg_ahb_clk.clkr,
3706 [GCC_CAMSS_JPEG_AXI_CLK] = &gcc_camss_jpeg_axi_clk.clkr,
3707 [GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr,
3708 [GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr,
3709 [GCC_CAMSS_MCLK2_CLK] = &gcc_camss_mclk2_clk.clkr,
3710 [GCC_CAMSS_MICRO_AHB_CLK] = &gcc_camss_micro_ahb_clk.clkr,
3711 [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr,
3712 [GCC_CAMSS_VFE0_AHB_CLK] = &gcc_camss_vfe0_ahb_clk.clkr,
3713 [GCC_CAMSS_VFE0_AXI_CLK] = &gcc_camss_vfe0_axi_clk.clkr,
3714 [GCC_CAMSS_VFE0_CLK] = &gcc_camss_vfe0_clk.clkr,
3715 [GCC_CAMSS_VFE1_AHB_CLK] = &gcc_camss_vfe1_ahb_clk.clkr,
3716 [GCC_CAMSS_VFE1_AXI_CLK] = &gcc_camss_vfe1_axi_clk.clkr,
3717 [GCC_CAMSS_VFE1_CLK] = &gcc_camss_vfe1_clk.clkr,
3718 [GCC_CPP_TBU_CLK] = &gcc_cpp_tbu_clk.clkr,
3719 [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
3720 [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
3721 [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
3722 [GCC_DCC_CLK] = &gcc_dcc_clk.clkr,
3723 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3724 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3725 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3726 [GCC_JPEG_TBU_CLK] = &gcc_jpeg_tbu_clk.clkr,
3727 [GCC_MDP_TBU_CLK] = &gcc_mdp_tbu_clk.clkr,
3728 [GCC_MDSS_AHB_CLK] = &gcc_mdss_ahb_clk.clkr,
3729 [GCC_MDSS_AXI_CLK] = &gcc_mdss_axi_clk.clkr,
3730 [GCC_MDSS_BYTE0_CLK] = &gcc_mdss_byte0_clk.clkr,
3731 [MSM8937_GCC_MDSS_BYTE1_CLK] = &gcc_mdss_byte1_clk.clkr,
3732 [GCC_MDSS_ESC0_CLK] = &gcc_mdss_esc0_clk.clkr,
3733 [MSM8937_GCC_MDSS_ESC1_CLK] = &gcc_mdss_esc1_clk.clkr,
3734 [GCC_MDSS_MDP_CLK] = &gcc_mdss_mdp_clk.clkr,
3735 [GCC_MDSS_PCLK0_CLK] = &gcc_mdss_pclk0_clk.clkr,
3736 [MSM8937_GCC_MDSS_PCLK1_CLK] = &gcc_mdss_pclk1_clk.clkr,
3737 [GCC_MDSS_VSYNC_CLK] = &gcc_mdss_vsync_clk.clkr,
3738 [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
3739 [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
3740 [GCC_OXILI_AHB_CLK] = &gcc_oxili_ahb_clk.clkr,
3741 [MSM8937_GCC_OXILI_AON_CLK] = &gcc_oxili_aon_clk.clkr,
3742 [GCC_OXILI_GFX3D_CLK] = &gcc_oxili_gfx3d_clk.clkr,
3743 [MSM8937_GCC_OXILI_TIMER_CLK] = &gcc_oxili_timer_clk.clkr,
3744 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3745 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3746 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3747 [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
3748 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
3749 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
3750 [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
3751 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3752 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3753 [GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr,
3754 [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
3755 [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
3756 [GCC_USB_HS_PHY_CFG_AHB_CLK] = &gcc_usb_hs_phy_cfg_ahb_clk.clkr,
3757 [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
3758 [GCC_VENUS0_AHB_CLK] = &gcc_venus0_ahb_clk.clkr,
3759 [GCC_VENUS0_AXI_CLK] = &gcc_venus0_axi_clk.clkr,
3760 [GCC_VENUS0_CORE0_VCODEC0_CLK] = &gcc_venus0_core0_vcodec0_clk.clkr,
3761 [GCC_VENUS0_VCODEC0_CLK] = &gcc_venus0_vcodec0_clk.clkr,
3762 [GCC_VENUS_TBU_CLK] = &gcc_venus_tbu_clk.clkr,
3763 [GCC_VFE1_TBU_CLK] = &gcc_vfe1_tbu_clk.clkr,
3764 [GCC_VFE_TBU_CLK] = &gcc_vfe_tbu_clk.clkr,
3765};
3766
3767static const struct qcom_reset_map gcc_msm8917_resets[] = {
3768 [GCC_CAMSS_MICRO_BCR] = { 0x56008 },
3769 [GCC_MSS_BCR] = { 0x71000 },
3770 [GCC_QUSB2_PHY_BCR] = { 0x4103c },
3771 [GCC_USB_HS_BCR] = { 0x41000 },
3772 [GCC_USB2_HS_PHY_ONLY_BCR] = { 0x41034 },
3773};
3774
3775static const struct regmap_config gcc_msm8917_regmap_config = {
3776 .reg_bits = 32,
3777 .reg_stride = 4,
3778 .val_bits = 32,
3779 .max_register = 0x80000,
3780 .fast_io = true,
3781};
3782
3783static struct gdsc *gcc_msm8917_gdscs[] = {
3784 [CPP_GDSC] = &cpp_gdsc,
3785 [JPEG_GDSC] = &jpeg_gdsc,
3786 [MDSS_GDSC] = &mdss_gdsc,
3787 [OXILI_GX_GDSC] = &oxili_gx_gdsc,
3788 [VENUS_CORE0_GDSC] = &venus_core0_gdsc,
3789 [VENUS_GDSC] = &venus_gdsc,
3790 [VFE0_GDSC] = &vfe0_gdsc,
3791 [VFE1_GDSC] = &vfe1_gdsc,
3792};
3793
3794static struct gdsc *gcc_msm8937_gdscs[] = {
3795 [CPP_GDSC] = &cpp_gdsc,
3796 [JPEG_GDSC] = &jpeg_gdsc,
3797 [MDSS_GDSC] = &mdss_gdsc,
3798 [OXILI_GX_GDSC] = &oxili_gx_gdsc_msm8937,
3799 [MSM8937_OXILI_CX_GDSC] = &oxili_cx_gdsc,
3800 [VENUS_CORE0_GDSC] = &venus_core0_gdsc,
3801 [VENUS_GDSC] = &venus_gdsc,
3802 [VFE0_GDSC] = &vfe0_gdsc,
3803 [VFE1_GDSC] = &vfe1_gdsc,
3804};
3805
3806static const struct qcom_cc_desc gcc_msm8917_desc = {
3807 .config = &gcc_msm8917_regmap_config,
3808 .clks = gcc_msm8917_clocks,
3809 .num_clks = ARRAY_SIZE(gcc_msm8917_clocks),
3810 .resets = gcc_msm8917_resets,
3811 .num_resets = ARRAY_SIZE(gcc_msm8917_resets),
3812 .gdscs = gcc_msm8917_gdscs,
3813 .num_gdscs = ARRAY_SIZE(gcc_msm8917_gdscs),
3814};
3815
3816static const struct qcom_cc_desc gcc_qm215_desc = {
3817 .config = &gcc_msm8917_regmap_config,
3818 .clks = gcc_msm8917_clocks,
3819 .num_clks = ARRAY_SIZE(gcc_msm8917_clocks),
3820 .resets = gcc_msm8917_resets,
3821 .num_resets = ARRAY_SIZE(gcc_msm8917_resets),
3822 .gdscs = gcc_msm8917_gdscs,
3823 .num_gdscs = ARRAY_SIZE(gcc_msm8917_gdscs),
3824};
3825
3826static const struct qcom_cc_desc gcc_msm8937_desc = {
3827 .config = &gcc_msm8917_regmap_config,
3828 .clks = gcc_msm8937_clocks,
3829 .num_clks = ARRAY_SIZE(gcc_msm8937_clocks),
3830 .resets = gcc_msm8917_resets,
3831 .num_resets = ARRAY_SIZE(gcc_msm8917_resets),
3832 .gdscs = gcc_msm8937_gdscs,
3833 .num_gdscs = ARRAY_SIZE(gcc_msm8937_gdscs),
3834};
3835
3836static void msm8937_clock_override(void)
3837{
3838 /* GPLL3 750MHz configuration */
3839 gpll3_early_config.l = 47;
3840 gpll3_early.vco_table = gpll3_p_vco_msm8937;
3841 gpll3_early.num_vco = ARRAY_SIZE(gpll3_p_vco_msm8937);
3842
3843 /*
3844 * Set below clocks for use specific msm8937 parent map.
3845 */
3846 vcodec0_clk_src.parent_map = gcc_cpp_map;
3847 vcodec0_clk_src.clkr.hw.init = &vcodec0_clk_src_init_msm8937;
3848
3849 /*
3850 * Set below clocks for use specific msm8937 freq table.
3851 */
3852 vfe0_clk_src.freq_tbl = ftbl_vfe_clk_src_msm8937;
3853 vfe1_clk_src.freq_tbl = ftbl_vfe_clk_src_msm8937;
3854 cpp_clk_src.freq_tbl = ftbl_cpp_clk_src_msm8937;
3855 vcodec0_clk_src.freq_tbl = ftbl_vcodec0_clk_src_msm8937;
3856 csi0phytimer_clk_src.freq_tbl = ftbl_csi_phytimer_clk_src_msm8937;
3857 csi1phytimer_clk_src.freq_tbl = ftbl_csi_phytimer_clk_src_msm8937;
3858 usb_hs_system_clk_src.freq_tbl = ftbl_usb_hs_system_clk_src_msm8937;
3859}
3860
3861static int gcc_msm8917_probe(struct platform_device *pdev)
3862{
3863 struct regmap *regmap;
3864 const struct qcom_cc_desc *gcc_desc;
3865
3866 gcc_desc = of_device_get_match_data(dev: &pdev->dev);
3867
3868 if (gcc_desc == &gcc_qm215_desc) {
3869 gfx3d_clk_src.parent_map = gcc_gfx3d_map_qm215;
3870 } else if (gcc_desc == &gcc_msm8937_desc) {
3871 msm8937_clock_override();
3872 gfx3d_clk_src.freq_tbl = ftbl_gfx3d_clk_src_msm8937;
3873 }
3874
3875 regmap = qcom_cc_map(pdev, desc: gcc_desc);
3876 if (IS_ERR(ptr: regmap))
3877 return PTR_ERR(ptr: regmap);
3878
3879 clk_alpha_pll_configure(pll: &gpll3_early, regmap, config: &gpll3_early_config);
3880
3881 return qcom_cc_really_probe(dev: &pdev->dev, desc: gcc_desc, regmap);
3882}
3883
3884static const struct of_device_id gcc_msm8917_match_table[] = {
3885 { .compatible = "qcom,gcc-msm8917", .data = &gcc_msm8917_desc },
3886 { .compatible = "qcom,gcc-qm215", .data = &gcc_qm215_desc },
3887 { .compatible = "qcom,gcc-msm8937", .data = &gcc_msm8937_desc },
3888 {},
3889};
3890MODULE_DEVICE_TABLE(of, gcc_msm8917_match_table);
3891
3892static struct platform_driver gcc_msm8917_driver = {
3893 .probe = gcc_msm8917_probe,
3894 .driver = {
3895 .name = "gcc-msm8917",
3896 .of_match_table = gcc_msm8917_match_table,
3897 },
3898};
3899
3900static int __init gcc_msm8917_init(void)
3901{
3902 return platform_driver_register(&gcc_msm8917_driver);
3903}
3904core_initcall(gcc_msm8917_init);
3905
3906static void __exit gcc_msm8917_exit(void)
3907{
3908 platform_driver_unregister(&gcc_msm8917_driver);
3909}
3910module_exit(gcc_msm8917_exit);
3911
3912MODULE_DESCRIPTION("Qualcomm GCC MSM8917 Driver");
3913MODULE_LICENSE("GPL");
3914

source code of linux/drivers/clk/qcom/gcc-msm8917.c