1// SPDX-License-Identifier: GPL-2.0-only
2// Copyright (C) 2014 Broadcom Corporation
3
4#include <linux/kernel.h>
5#include <linux/err.h>
6#include <linux/clk-provider.h>
7#include <linux/io.h>
8#include <linux/of.h>
9#include <linux/clkdev.h>
10#include <linux/of_address.h>
11#include <linux/delay.h>
12
13#include "clk-iproc.h"
14
15struct iproc_asiu;
16
17struct iproc_asiu_clk {
18 struct clk_hw hw;
19 const char *name;
20 struct iproc_asiu *asiu;
21 unsigned long rate;
22 struct iproc_asiu_div div;
23 struct iproc_asiu_gate gate;
24};
25
26struct iproc_asiu {
27 void __iomem *div_base;
28 void __iomem *gate_base;
29
30 struct clk_hw_onecell_data *clk_data;
31 struct iproc_asiu_clk *clks;
32};
33
34#define to_asiu_clk(hw) container_of(hw, struct iproc_asiu_clk, hw)
35
36static int iproc_asiu_clk_enable(struct clk_hw *hw)
37{
38 struct iproc_asiu_clk *clk = to_asiu_clk(hw);
39 struct iproc_asiu *asiu = clk->asiu;
40 u32 val;
41
42 /* some clocks at the ASIU level are always enabled */
43 if (clk->gate.offset == IPROC_CLK_INVALID_OFFSET)
44 return 0;
45
46 val = readl(addr: asiu->gate_base + clk->gate.offset);
47 val |= (1 << clk->gate.en_shift);
48 writel(val, addr: asiu->gate_base + clk->gate.offset);
49
50 return 0;
51}
52
53static void iproc_asiu_clk_disable(struct clk_hw *hw)
54{
55 struct iproc_asiu_clk *clk = to_asiu_clk(hw);
56 struct iproc_asiu *asiu = clk->asiu;
57 u32 val;
58
59 /* some clocks at the ASIU level are always enabled */
60 if (clk->gate.offset == IPROC_CLK_INVALID_OFFSET)
61 return;
62
63 val = readl(addr: asiu->gate_base + clk->gate.offset);
64 val &= ~(1 << clk->gate.en_shift);
65 writel(val, addr: asiu->gate_base + clk->gate.offset);
66}
67
68static unsigned long iproc_asiu_clk_recalc_rate(struct clk_hw *hw,
69 unsigned long parent_rate)
70{
71 struct iproc_asiu_clk *clk = to_asiu_clk(hw);
72 struct iproc_asiu *asiu = clk->asiu;
73 u32 val;
74 unsigned int div_h, div_l;
75
76 if (parent_rate == 0) {
77 clk->rate = 0;
78 return 0;
79 }
80
81 /* if clock divisor is not enabled, simply return parent rate */
82 val = readl(addr: asiu->div_base + clk->div.offset);
83 if ((val & (1 << clk->div.en_shift)) == 0) {
84 clk->rate = parent_rate;
85 return parent_rate;
86 }
87
88 /* clock rate = parent rate / (high_div + 1) + (low_div + 1) */
89 div_h = (val >> clk->div.high_shift) & bit_mask(clk->div.high_width);
90 div_h++;
91 div_l = (val >> clk->div.low_shift) & bit_mask(clk->div.low_width);
92 div_l++;
93
94 clk->rate = parent_rate / (div_h + div_l);
95 pr_debug("%s: rate: %lu. parent rate: %lu div_h: %u div_l: %u\n",
96 __func__, clk->rate, parent_rate, div_h, div_l);
97
98 return clk->rate;
99}
100
101static int iproc_asiu_clk_determine_rate(struct clk_hw *hw,
102 struct clk_rate_request *req)
103{
104 unsigned int div;
105
106 if (req->rate == 0 || req->best_parent_rate == 0)
107 return -EINVAL;
108
109 if (req->rate == req->best_parent_rate)
110 return 0;
111
112 div = DIV_ROUND_CLOSEST(req->best_parent_rate, req->rate);
113 if (div < 2) {
114 req->rate = req->best_parent_rate;
115
116 return 0;
117 }
118
119 req->rate = req->best_parent_rate / div;
120
121 return 0;
122}
123
124static int iproc_asiu_clk_set_rate(struct clk_hw *hw, unsigned long rate,
125 unsigned long parent_rate)
126{
127 struct iproc_asiu_clk *clk = to_asiu_clk(hw);
128 struct iproc_asiu *asiu = clk->asiu;
129 unsigned int div, div_h, div_l;
130 u32 val;
131
132 if (rate == 0 || parent_rate == 0)
133 return -EINVAL;
134
135 /* simply disable the divisor if one wants the same rate as parent */
136 if (rate == parent_rate) {
137 val = readl(addr: asiu->div_base + clk->div.offset);
138 val &= ~(1 << clk->div.en_shift);
139 writel(val, addr: asiu->div_base + clk->div.offset);
140 return 0;
141 }
142
143 div = DIV_ROUND_CLOSEST(parent_rate, rate);
144 if (div < 2)
145 return -EINVAL;
146
147 div_h = div_l = div >> 1;
148 div_h--;
149 div_l--;
150
151 val = readl(addr: asiu->div_base + clk->div.offset);
152 val |= 1 << clk->div.en_shift;
153 if (div_h) {
154 val &= ~(bit_mask(clk->div.high_width)
155 << clk->div.high_shift);
156 val |= div_h << clk->div.high_shift;
157 } else {
158 val &= ~(bit_mask(clk->div.high_width)
159 << clk->div.high_shift);
160 }
161 if (div_l) {
162 val &= ~(bit_mask(clk->div.low_width) << clk->div.low_shift);
163 val |= div_l << clk->div.low_shift;
164 } else {
165 val &= ~(bit_mask(clk->div.low_width) << clk->div.low_shift);
166 }
167 writel(val, addr: asiu->div_base + clk->div.offset);
168
169 return 0;
170}
171
172static const struct clk_ops iproc_asiu_ops = {
173 .enable = iproc_asiu_clk_enable,
174 .disable = iproc_asiu_clk_disable,
175 .recalc_rate = iproc_asiu_clk_recalc_rate,
176 .determine_rate = iproc_asiu_clk_determine_rate,
177 .set_rate = iproc_asiu_clk_set_rate,
178};
179
180void __init iproc_asiu_setup(struct device_node *node,
181 const struct iproc_asiu_div *div,
182 const struct iproc_asiu_gate *gate,
183 unsigned int num_clks)
184{
185 int i, ret;
186 struct iproc_asiu *asiu;
187
188 if (WARN_ON(!gate || !div))
189 return;
190
191 asiu = kzalloc(sizeof(*asiu), GFP_KERNEL);
192 if (WARN_ON(!asiu))
193 return;
194
195 asiu->clk_data = kzalloc(struct_size(asiu->clk_data, hws, num_clks),
196 GFP_KERNEL);
197 if (WARN_ON(!asiu->clk_data))
198 goto err_clks;
199 asiu->clk_data->num = num_clks;
200
201 asiu->clks = kcalloc(num_clks, sizeof(*asiu->clks), GFP_KERNEL);
202 if (WARN_ON(!asiu->clks))
203 goto err_asiu_clks;
204
205 asiu->div_base = of_iomap(node, index: 0);
206 if (WARN_ON(!asiu->div_base))
207 goto err_iomap_div;
208
209 asiu->gate_base = of_iomap(node, index: 1);
210 if (WARN_ON(!asiu->gate_base))
211 goto err_iomap_gate;
212
213 for (i = 0; i < num_clks; i++) {
214 struct clk_init_data init;
215 const char *parent_name;
216 struct iproc_asiu_clk *asiu_clk;
217 const char *clk_name;
218
219 ret = of_property_read_string_index(np: node, propname: "clock-output-names",
220 index: i, output: &clk_name);
221 if (WARN_ON(ret))
222 goto err_clk_register;
223
224 asiu_clk = &asiu->clks[i];
225 asiu_clk->name = clk_name;
226 asiu_clk->asiu = asiu;
227 asiu_clk->div = div[i];
228 asiu_clk->gate = gate[i];
229 init.name = clk_name;
230 init.ops = &iproc_asiu_ops;
231 init.flags = 0;
232 parent_name = of_clk_get_parent_name(np: node, index: 0);
233 init.parent_names = (parent_name ? &parent_name : NULL);
234 init.num_parents = (parent_name ? 1 : 0);
235 asiu_clk->hw.init = &init;
236
237 ret = clk_hw_register(NULL, hw: &asiu_clk->hw);
238 if (WARN_ON(ret))
239 goto err_clk_register;
240 asiu->clk_data->hws[i] = &asiu_clk->hw;
241 }
242
243 ret = of_clk_add_hw_provider(np: node, get: of_clk_hw_onecell_get,
244 data: asiu->clk_data);
245 if (WARN_ON(ret))
246 goto err_clk_register;
247
248 return;
249
250err_clk_register:
251 while (--i >= 0)
252 clk_hw_unregister(hw: asiu->clk_data->hws[i]);
253 iounmap(addr: asiu->gate_base);
254
255err_iomap_gate:
256 iounmap(addr: asiu->div_base);
257
258err_iomap_div:
259 kfree(objp: asiu->clks);
260
261err_asiu_clks:
262 kfree(objp: asiu->clk_data);
263
264err_clks:
265 kfree(objp: asiu);
266}
267

source code of linux/drivers/clk/bcm/clk-iproc-asiu.c