1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2014 Broadcom Corporation
4 * Copyright 2014 Linaro Limited
5 */
6
7#include "clk-kona.h"
8#include "dt-bindings/clock/bcm21664.h"
9
10#define BCM21664_CCU_COMMON(_name, _capname) \
11 KONA_CCU_COMMON(BCM21664, _name, _capname)
12
13/* Root CCU */
14
15static struct peri_clk_data frac_1m_data = {
16 .gate = HW_SW_GATE(0x214, 16, 0, 1),
17 .clocks = CLOCKS("ref_crystal"),
18};
19
20static struct ccu_data root_ccu_data = {
21 BCM21664_CCU_COMMON(root, ROOT),
22 /* no policy control */
23 .kona_clks = {
24 [BCM21664_ROOT_CCU_FRAC_1M] =
25 KONA_CLK(root, frac_1m, peri),
26 [BCM21664_ROOT_CCU_CLOCK_COUNT] = LAST_KONA_CLK,
27 },
28};
29
30/* AON CCU */
31
32static struct peri_clk_data hub_timer_data = {
33 .gate = HW_SW_GATE(0x0414, 16, 0, 1),
34 .hyst = HYST(0x0414, 8, 9),
35 .clocks = CLOCKS("bbl_32k",
36 "frac_1m",
37 "dft_19_5m"),
38 .sel = SELECTOR(0x0a10, 0, 2),
39 .trig = TRIGGER(0x0a40, 4),
40};
41
42static struct ccu_data aon_ccu_data = {
43 BCM21664_CCU_COMMON(aon, AON),
44 .policy = {
45 .enable = CCU_LVM_EN(0x0034, 0),
46 .control = CCU_POLICY_CTL(0x000c, 0, 1, 2),
47 },
48 .kona_clks = {
49 [BCM21664_AON_CCU_HUB_TIMER] =
50 KONA_CLK(aon, hub_timer, peri),
51 [BCM21664_AON_CCU_CLOCK_COUNT] = LAST_KONA_CLK,
52 },
53};
54
55/* Master CCU */
56
57static struct peri_clk_data sdio1_data = {
58 .gate = HW_SW_GATE(0x0358, 18, 2, 3),
59 .clocks = CLOCKS("ref_crystal",
60 "var_52m",
61 "ref_52m",
62 "var_96m",
63 "ref_96m"),
64 .sel = SELECTOR(0x0a28, 0, 3),
65 .div = DIVIDER(0x0a28, 4, 14),
66 .trig = TRIGGER(0x0afc, 9),
67};
68
69static struct peri_clk_data sdio2_data = {
70 .gate = HW_SW_GATE(0x035c, 18, 2, 3),
71 .clocks = CLOCKS("ref_crystal",
72 "var_52m",
73 "ref_52m",
74 "var_96m",
75 "ref_96m"),
76 .sel = SELECTOR(0x0a2c, 0, 3),
77 .div = DIVIDER(0x0a2c, 4, 14),
78 .trig = TRIGGER(0x0afc, 10),
79};
80
81static struct peri_clk_data sdio3_data = {
82 .gate = HW_SW_GATE(0x0364, 18, 2, 3),
83 .clocks = CLOCKS("ref_crystal",
84 "var_52m",
85 "ref_52m",
86 "var_96m",
87 "ref_96m"),
88 .sel = SELECTOR(0x0a34, 0, 3),
89 .div = DIVIDER(0x0a34, 4, 14),
90 .trig = TRIGGER(0x0afc, 12),
91};
92
93static struct peri_clk_data sdio4_data = {
94 .gate = HW_SW_GATE(0x0360, 18, 2, 3),
95 .clocks = CLOCKS("ref_crystal",
96 "var_52m",
97 "ref_52m",
98 "var_96m",
99 "ref_96m"),
100 .sel = SELECTOR(0x0a30, 0, 3),
101 .div = DIVIDER(0x0a30, 4, 14),
102 .trig = TRIGGER(0x0afc, 11),
103};
104
105static struct peri_clk_data sdio1_sleep_data = {
106 .clocks = CLOCKS("ref_32k"), /* Verify */
107 .gate = HW_SW_GATE(0x0358, 18, 2, 3),
108};
109
110static struct peri_clk_data sdio2_sleep_data = {
111 .clocks = CLOCKS("ref_32k"), /* Verify */
112 .gate = HW_SW_GATE(0x035c, 18, 2, 3),
113};
114
115static struct peri_clk_data sdio3_sleep_data = {
116 .clocks = CLOCKS("ref_32k"), /* Verify */
117 .gate = HW_SW_GATE(0x0364, 18, 2, 3),
118};
119
120static struct peri_clk_data sdio4_sleep_data = {
121 .clocks = CLOCKS("ref_32k"), /* Verify */
122 .gate = HW_SW_GATE(0x0360, 18, 2, 3),
123};
124
125static struct ccu_data master_ccu_data = {
126 BCM21664_CCU_COMMON(master, MASTER),
127 .policy = {
128 .enable = CCU_LVM_EN(0x0034, 0),
129 .control = CCU_POLICY_CTL(0x000c, 0, 1, 2),
130 },
131 .kona_clks = {
132 [BCM21664_MASTER_CCU_SDIO1] =
133 KONA_CLK(master, sdio1, peri),
134 [BCM21664_MASTER_CCU_SDIO2] =
135 KONA_CLK(master, sdio2, peri),
136 [BCM21664_MASTER_CCU_SDIO3] =
137 KONA_CLK(master, sdio3, peri),
138 [BCM21664_MASTER_CCU_SDIO4] =
139 KONA_CLK(master, sdio4, peri),
140 [BCM21664_MASTER_CCU_SDIO1_SLEEP] =
141 KONA_CLK(master, sdio1_sleep, peri),
142 [BCM21664_MASTER_CCU_SDIO2_SLEEP] =
143 KONA_CLK(master, sdio2_sleep, peri),
144 [BCM21664_MASTER_CCU_SDIO3_SLEEP] =
145 KONA_CLK(master, sdio3_sleep, peri),
146 [BCM21664_MASTER_CCU_SDIO4_SLEEP] =
147 KONA_CLK(master, sdio4_sleep, peri),
148 [BCM21664_MASTER_CCU_CLOCK_COUNT] = LAST_KONA_CLK,
149 },
150};
151
152/* Slave CCU */
153
154static struct peri_clk_data uartb_data = {
155 .gate = HW_SW_GATE(0x0400, 18, 2, 3),
156 .clocks = CLOCKS("ref_crystal",
157 "var_156m",
158 "ref_156m"),
159 .sel = SELECTOR(0x0a10, 0, 2),
160 .div = FRAC_DIVIDER(0x0a10, 4, 12, 8),
161 .trig = TRIGGER(0x0afc, 2),
162};
163
164static struct peri_clk_data uartb2_data = {
165 .gate = HW_SW_GATE(0x0404, 18, 2, 3),
166 .clocks = CLOCKS("ref_crystal",
167 "var_156m",
168 "ref_156m"),
169 .sel = SELECTOR(0x0a14, 0, 2),
170 .div = FRAC_DIVIDER(0x0a14, 4, 12, 8),
171 .trig = TRIGGER(0x0afc, 3),
172};
173
174static struct peri_clk_data uartb3_data = {
175 .gate = HW_SW_GATE(0x0408, 18, 2, 3),
176 .clocks = CLOCKS("ref_crystal",
177 "var_156m",
178 "ref_156m"),
179 .sel = SELECTOR(0x0a18, 0, 2),
180 .div = FRAC_DIVIDER(0x0a18, 4, 12, 8),
181 .trig = TRIGGER(0x0afc, 4),
182};
183
184static struct peri_clk_data bsc1_data = {
185 .gate = HW_SW_GATE(0x0458, 18, 2, 3),
186 .clocks = CLOCKS("ref_crystal",
187 "var_104m",
188 "ref_104m",
189 "var_13m",
190 "ref_13m"),
191 .sel = SELECTOR(0x0a64, 0, 3),
192 .trig = TRIGGER(0x0afc, 23),
193};
194
195static struct peri_clk_data bsc2_data = {
196 .gate = HW_SW_GATE(0x045c, 18, 2, 3),
197 .clocks = CLOCKS("ref_crystal",
198 "var_104m",
199 "ref_104m",
200 "var_13m",
201 "ref_13m"),
202 .sel = SELECTOR(0x0a68, 0, 3),
203 .trig = TRIGGER(0x0afc, 24),
204};
205
206static struct peri_clk_data bsc3_data = {
207 .gate = HW_SW_GATE(0x0470, 18, 2, 3),
208 .clocks = CLOCKS("ref_crystal",
209 "var_104m",
210 "ref_104m",
211 "var_13m",
212 "ref_13m"),
213 .sel = SELECTOR(0x0a7c, 0, 3),
214 .trig = TRIGGER(0x0afc, 18),
215};
216
217static struct peri_clk_data bsc4_data = {
218 .gate = HW_SW_GATE(0x0474, 18, 2, 3),
219 .clocks = CLOCKS("ref_crystal",
220 "var_104m",
221 "ref_104m",
222 "var_13m",
223 "ref_13m"),
224 .sel = SELECTOR(0x0a80, 0, 3),
225 .trig = TRIGGER(0x0afc, 19),
226};
227
228static struct ccu_data slave_ccu_data = {
229 BCM21664_CCU_COMMON(slave, SLAVE),
230 .policy = {
231 .enable = CCU_LVM_EN(0x0034, 0),
232 .control = CCU_POLICY_CTL(0x000c, 0, 1, 2),
233 },
234 .kona_clks = {
235 [BCM21664_SLAVE_CCU_UARTB] =
236 KONA_CLK(slave, uartb, peri),
237 [BCM21664_SLAVE_CCU_UARTB2] =
238 KONA_CLK(slave, uartb2, peri),
239 [BCM21664_SLAVE_CCU_UARTB3] =
240 KONA_CLK(slave, uartb3, peri),
241 [BCM21664_SLAVE_CCU_BSC1] =
242 KONA_CLK(slave, bsc1, peri),
243 [BCM21664_SLAVE_CCU_BSC2] =
244 KONA_CLK(slave, bsc2, peri),
245 [BCM21664_SLAVE_CCU_BSC3] =
246 KONA_CLK(slave, bsc3, peri),
247 [BCM21664_SLAVE_CCU_BSC4] =
248 KONA_CLK(slave, bsc4, peri),
249 [BCM21664_SLAVE_CCU_CLOCK_COUNT] = LAST_KONA_CLK,
250 },
251};
252
253/* Device tree match table callback functions */
254
255static void __init kona_dt_root_ccu_setup(struct device_node *node)
256{
257 kona_dt_ccu_setup(ccu: &root_ccu_data, node);
258}
259
260static void __init kona_dt_aon_ccu_setup(struct device_node *node)
261{
262 kona_dt_ccu_setup(ccu: &aon_ccu_data, node);
263}
264
265static void __init kona_dt_master_ccu_setup(struct device_node *node)
266{
267 kona_dt_ccu_setup(ccu: &master_ccu_data, node);
268}
269
270static void __init kona_dt_slave_ccu_setup(struct device_node *node)
271{
272 kona_dt_ccu_setup(ccu: &slave_ccu_data, node);
273}
274
275CLK_OF_DECLARE(bcm21664_root_ccu, BCM21664_DT_ROOT_CCU_COMPAT,
276 kona_dt_root_ccu_setup);
277CLK_OF_DECLARE(bcm21664_aon_ccu, BCM21664_DT_AON_CCU_COMPAT,
278 kona_dt_aon_ccu_setup);
279CLK_OF_DECLARE(bcm21664_master_ccu, BCM21664_DT_MASTER_CCU_COMPAT,
280 kona_dt_master_ccu_setup);
281CLK_OF_DECLARE(bcm21664_slave_ccu, BCM21664_DT_SLAVE_CCU_COMPAT,
282 kona_dt_slave_ccu_setup);
283

source code of linux/drivers/clk/bcm/clk-bcm21664.c