1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright 2011 IBM Corporation.
4 */
5
6#include <linux/types.h>
7#include <linux/kernel.h>
8#include <linux/irq.h>
9#include <linux/irqdomain.h>
10#include <linux/smp.h>
11#include <linux/interrupt.h>
12#include <linux/init.h>
13#include <linux/cpu.h>
14#include <linux/of.h>
15#include <linux/of_address.h>
16#include <linux/spinlock.h>
17#include <linux/module.h>
18
19#include <asm/io.h>
20#include <asm/smp.h>
21#include <asm/irq.h>
22#include <asm/errno.h>
23#include <asm/xics.h>
24#include <asm/kvm_ppc.h>
25#include <asm/dbell.h>
26
27struct icp_ipl {
28 union {
29 u32 word;
30 u8 bytes[4];
31 } xirr_poll;
32 union {
33 u32 word;
34 u8 bytes[4];
35 } xirr;
36 u32 dummy;
37 union {
38 u32 word;
39 u8 bytes[4];
40 } qirr;
41 u32 link_a;
42 u32 link_b;
43 u32 link_c;
44};
45
46static struct icp_ipl __iomem *icp_native_regs[NR_CPUS];
47
48static inline unsigned int icp_native_get_xirr(void)
49{
50 int cpu = smp_processor_id();
51 unsigned int xirr;
52
53 /* Handled an interrupt latched by KVM */
54 xirr = kvmppc_get_xics_latch();
55 if (xirr)
56 return xirr;
57
58 return in_be32(&icp_native_regs[cpu]->xirr.word);
59}
60
61static inline void icp_native_set_xirr(unsigned int value)
62{
63 int cpu = smp_processor_id();
64
65 out_be32(&icp_native_regs[cpu]->xirr.word, value);
66}
67
68static inline void icp_native_set_cppr(u8 value)
69{
70 int cpu = smp_processor_id();
71
72 out_8(&icp_native_regs[cpu]->xirr.bytes[0], value);
73}
74
75static inline void icp_native_set_qirr(int n_cpu, u8 value)
76{
77 out_8(&icp_native_regs[n_cpu]->qirr.bytes[0], value);
78}
79
80static void icp_native_set_cpu_priority(unsigned char cppr)
81{
82 xics_set_base_cppr(cppr);
83 icp_native_set_cppr(value: cppr);
84 iosync();
85}
86
87void icp_native_eoi(struct irq_data *d)
88{
89 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
90
91 iosync();
92 icp_native_set_xirr(value: (xics_pop_cppr() << 24) | hw_irq);
93}
94
95static void icp_native_teardown_cpu(void)
96{
97 int cpu = smp_processor_id();
98
99 /* Clear any pending IPI */
100 icp_native_set_qirr(n_cpu: cpu, value: 0xff);
101}
102
103static void icp_native_flush_ipi(void)
104{
105 /* We take the ipi irq but and never return so we
106 * need to EOI the IPI, but want to leave our priority 0
107 *
108 * should we check all the other interrupts too?
109 * should we be flagging idle loop instead?
110 * or creating some task to be scheduled?
111 */
112
113 icp_native_set_xirr(value: (0x00 << 24) | XICS_IPI);
114}
115
116static unsigned int icp_native_get_irq(void)
117{
118 unsigned int xirr = icp_native_get_xirr();
119 unsigned int vec = xirr & 0x00ffffff;
120 unsigned int irq;
121
122 if (vec == XICS_IRQ_SPURIOUS)
123 return 0;
124
125 irq = irq_find_mapping(domain: xics_host, hwirq: vec);
126 if (likely(irq)) {
127 xics_push_cppr(vec);
128 return irq;
129 }
130
131 /* We don't have a linux mapping, so have rtas mask it. */
132 xics_mask_unknown_vec(vec);
133
134 /* We might learn about it later, so EOI it */
135 icp_native_set_xirr(value: xirr);
136
137 return 0;
138}
139
140#ifdef CONFIG_SMP
141
142static void icp_native_cause_ipi(int cpu)
143{
144 kvmppc_set_host_ipi(cpu);
145 icp_native_set_qirr(n_cpu: cpu, value: IPI_PRIORITY);
146}
147
148/*
149 * Called when an interrupt is received on an off-line CPU to
150 * clear the interrupt, so that the CPU can go back to nap mode.
151 */
152void icp_native_flush_interrupt(void)
153{
154 unsigned int xirr = icp_native_get_xirr();
155 unsigned int vec = xirr & 0x00ffffff;
156
157 if (vec == XICS_IRQ_SPURIOUS)
158 return;
159 if (vec == XICS_IPI) {
160 /* Clear pending IPI */
161 int cpu = smp_processor_id();
162 kvmppc_clear_host_ipi(cpu);
163 icp_native_set_qirr(n_cpu: cpu, value: 0xff);
164 } else {
165 pr_err("XICS: hw interrupt 0x%x to offline cpu, disabling\n",
166 vec);
167 xics_mask_unknown_vec(vec);
168 }
169 /* EOI the interrupt */
170 icp_native_set_xirr(value: xirr);
171}
172
173void xics_wake_cpu(int cpu)
174{
175 icp_native_set_qirr(n_cpu: cpu, value: IPI_PRIORITY);
176}
177EXPORT_SYMBOL_GPL(xics_wake_cpu);
178
179static irqreturn_t icp_native_ipi_action(int irq, void *dev_id)
180{
181 int cpu = smp_processor_id();
182
183 kvmppc_clear_host_ipi(cpu);
184 icp_native_set_qirr(n_cpu: cpu, value: 0xff);
185
186 return smp_ipi_demux();
187}
188
189#endif /* CONFIG_SMP */
190
191static int __init icp_native_map_one_cpu(int hw_id, unsigned long addr,
192 unsigned long size)
193{
194 char *rname;
195 int i, cpu = -1;
196
197 /* This may look gross but it's good enough for now, we don't quite
198 * have a hard -> linux processor id matching.
199 */
200 for_each_possible_cpu(i) {
201 if (!cpu_present(cpu: i))
202 continue;
203 if (hw_id == get_hard_smp_processor_id(i)) {
204 cpu = i;
205 break;
206 }
207 }
208
209 /* Fail, skip that CPU. Don't print, it's normal, some XICS come up
210 * with way more entries in there than you have CPUs
211 */
212 if (cpu == -1)
213 return 0;
214
215 rname = kasprintf(GFP_KERNEL, fmt: "CPU %d [0x%x] Interrupt Presentation",
216 cpu, hw_id);
217
218 if (!rname)
219 return -ENOMEM;
220 if (!request_mem_region(addr, size, rname)) {
221 pr_warn("icp_native: Could not reserve ICP MMIO for CPU %d, interrupt server #0x%x\n",
222 cpu, hw_id);
223 return -EBUSY;
224 }
225
226 icp_native_regs[cpu] = ioremap(offset: addr, size);
227 kvmppc_set_xics_phys(cpu, addr);
228 if (!icp_native_regs[cpu]) {
229 pr_warn("icp_native: Failed ioremap for CPU %d, interrupt server #0x%x, addr %#lx\n",
230 cpu, hw_id, addr);
231 release_mem_region(addr, size);
232 return -ENOMEM;
233 }
234 return 0;
235}
236
237static int __init icp_native_init_one_node(struct device_node *np,
238 unsigned int *indx)
239{
240 unsigned int ilen;
241 const __be32 *ireg;
242 int i;
243 int num_reg;
244 int num_servers = 0;
245
246 /* This code does the theorically broken assumption that the interrupt
247 * server numbers are the same as the hard CPU numbers.
248 * This happens to be the case so far but we are playing with fire...
249 * should be fixed one of these days. -BenH.
250 */
251 ireg = of_get_property(node: np, name: "ibm,interrupt-server-ranges", lenp: &ilen);
252
253 /* Do that ever happen ? we'll know soon enough... but even good'old
254 * f80 does have that property ..
255 */
256 WARN_ON((ireg == NULL) || (ilen != 2*sizeof(u32)));
257
258 if (ireg) {
259 *indx = of_read_number(cell: ireg, size: 1);
260 if (ilen >= 2*sizeof(u32))
261 num_servers = of_read_number(cell: ireg + 1, size: 1);
262 }
263
264 num_reg = of_address_count(np);
265 if (num_servers && (num_servers != num_reg)) {
266 pr_err("icp_native: ICP reg len (%d) != num servers (%d)",
267 num_reg, num_servers);
268 return -1;
269 }
270
271 for (i = 0; i < num_reg; i++) {
272 struct resource r;
273 int err;
274
275 err = of_address_to_resource(dev: np, index: i, r: &r);
276 if (err) {
277 pr_err("icp_native: Could not translate ICP MMIO"
278 " for interrupt server 0x%x (%d)\n", *indx, err);
279 return -1;
280 }
281
282 if (icp_native_map_one_cpu(hw_id: *indx, addr: r.start, size: resource_size(res: &r)))
283 return -1;
284
285 (*indx)++;
286 }
287 return 0;
288}
289
290static const struct icp_ops icp_native_ops = {
291 .get_irq = icp_native_get_irq,
292 .eoi = icp_native_eoi,
293 .set_priority = icp_native_set_cpu_priority,
294 .teardown_cpu = icp_native_teardown_cpu,
295 .flush_ipi = icp_native_flush_ipi,
296#ifdef CONFIG_SMP
297 .ipi_action = icp_native_ipi_action,
298 .cause_ipi = icp_native_cause_ipi,
299#endif
300};
301
302int __init icp_native_init(void)
303{
304 struct device_node *np;
305 u32 indx = 0;
306 int found = 0;
307
308 for_each_compatible_node(np, NULL, "ibm,ppc-xicp")
309 if (icp_native_init_one_node(np, indx: &indx) == 0)
310 found = 1;
311 if (!found) {
312 for_each_node_by_type(np,
313 "PowerPC-External-Interrupt-Presentation") {
314 if (icp_native_init_one_node(np, indx: &indx) == 0)
315 found = 1;
316 }
317 }
318
319 if (found == 0)
320 return -ENODEV;
321
322 icp_ops = &icp_native_ops;
323
324 return 0;
325}
326

source code of linux/arch/powerpc/sysdev/xics/icp-native.c