| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * Copyright (C) 2006-2007 PA Semi, Inc |
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| 4 | * |
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| 5 | * Maintained by: Olof Johansson <olof@lixom.net> |
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| 6 | */ |
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| 7 | |
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| 8 | #include <asm/processor.h> |
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| 9 | #include <asm/page.h> |
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| 10 | #include <asm/ppc_asm.h> |
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| 11 | #include <asm/cputable.h> |
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| 12 | #include <asm/cache.h> |
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| 13 | #include <asm/thread_info.h> |
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| 14 | #include <asm/asm-offsets.h> |
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| 15 | |
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| 16 | /* Power savings opcodes since not all binutils have them at this time */ |
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| 17 | #define DOZE .long 0x4c000324 |
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| 18 | #define NAP .long 0x4c000364 |
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| 19 | #define SLEEP .long 0x4c0003a4 |
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| 20 | #define RVW .long 0x4c0003e4 |
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| 21 | |
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| 22 | /* Common sequence to do before going to any of the |
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| 23 | * powersavings modes. |
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| 24 | */ |
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| 25 | |
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| 26 | #define PRE_SLEEP_SEQUENCE \ |
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| 27 | std r3,8(r1); \ |
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| 28 | ptesync ; \ |
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| 29 | ld r3,8(r1); \ |
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| 30 | 1: cmpd r3,r3; \ |
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| 31 | bne 1b |
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| 32 | |
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| 33 | _doze: |
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| 34 | PRE_SLEEP_SEQUENCE |
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| 35 | DOZE |
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| 36 | b . |
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| 37 | |
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| 38 | |
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| 39 | _GLOBAL(idle_spin) |
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| 40 | blr |
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| 41 | |
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| 42 | _GLOBAL(idle_doze) |
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| 43 | LOAD_REG_ADDR(r3, _doze) |
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| 44 | b sleep_common |
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| 45 | |
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| 46 | /* Add more modes here later */ |
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| 47 | |
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| 48 | sleep_common: |
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| 49 | mflr r0 |
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| 50 | std r0, 16(r1) |
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| 51 | stdu r1,-64(r1) |
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| 52 | #ifdef CONFIG_PPC_PASEMI_CPUFREQ |
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| 53 | std r3, 48(r1) |
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| 54 | |
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| 55 | /* Only do power savings when in astate 0 */ |
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| 56 | bl check_astate |
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| 57 | cmpwi r3,0 |
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| 58 | bne 1f |
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| 59 | |
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| 60 | ld r3, 48(r1) |
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| 61 | #endif |
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| 62 | LOAD_REG_IMMEDIATE(r6,MSR_DR|MSR_IR|MSR_ME|MSR_EE) |
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| 63 | mfmsr r4 |
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| 64 | andc r5,r4,r6 |
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| 65 | mtmsrd r5,0 |
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| 66 | |
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| 67 | mtctr r3 |
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| 68 | bctrl |
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| 69 | |
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| 70 | mtmsrd r4,0 |
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| 71 | |
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| 72 | 1: addi r1,r1,64 |
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| 73 | ld r0,16(r1) |
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| 74 | mtlr r0 |
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| 75 | blr |
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| 76 | |
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| 77 | |
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