1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Alchemy Db1550/Pb1550 board support
4 *
5 * (c) 2011 Manuel Lauss <manuel.lauss@googlemail.com>
6 */
7
8#include <linux/clk.h>
9#include <linux/dma-mapping.h>
10#include <linux/gpio.h>
11#include <linux/i2c.h>
12#include <linux/init.h>
13#include <linux/io.h>
14#include <linux/interrupt.h>
15#include <linux/mtd/mtd.h>
16#include <linux/mtd/platnand.h>
17#include <linux/platform_device.h>
18#include <linux/pm.h>
19#include <linux/spi/spi.h>
20#include <linux/spi/flash.h>
21#include <asm/bootinfo.h>
22#include <asm/mach-au1x00/au1000.h>
23#include <asm/mach-au1x00/gpio-au1000.h>
24#include <asm/mach-au1x00/au1xxx_eth.h>
25#include <asm/mach-au1x00/au1xxx_dbdma.h>
26#include <asm/mach-au1x00/au1xxx_psc.h>
27#include <asm/mach-au1x00/au1550_spi.h>
28#include <asm/mach-au1x00/au1550nd.h>
29#include <asm/mach-db1x00/bcsr.h>
30#include <prom.h>
31#include "platform.h"
32
33static void __init db1550_hw_setup(void)
34{
35 void __iomem *base;
36 unsigned long v;
37
38 /* complete pin setup: assign GPIO16 to PSC0_SYNC1 (SPI cs# line)
39 * as well as PSC1_SYNC for AC97 on PB1550.
40 */
41 v = alchemy_rdsys(AU1000_SYS_PINFUNC);
42 alchemy_wrsys(v | 1 | SYS_PF_PSC1_S1, AU1000_SYS_PINFUNC);
43
44 /* reset the AC97 codec now, the reset time in the psc-ac97 driver
45 * is apparently too short although it's ridiculous as it is.
46 */
47 base = (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR);
48 __raw_writel(val: PSC_SEL_CLK_SERCLK | PSC_SEL_PS_AC97MODE,
49 addr: base + PSC_SEL_OFFSET);
50 __raw_writel(val: PSC_CTRL_DISABLE, addr: base + PSC_CTRL_OFFSET);
51 wmb();
52 __raw_writel(val: PSC_AC97RST_RST, addr: base + PSC_AC97RST_OFFSET);
53 wmb();
54}
55
56int __init db1550_board_setup(void)
57{
58 unsigned short whoami;
59
60 bcsr_init(DB1550_BCSR_PHYS_ADDR,
61 DB1550_BCSR_PHYS_ADDR + DB1550_BCSR_HEXLED_OFS);
62
63 whoami = bcsr_read(BCSR_WHOAMI); /* PB1550 hexled offset differs */
64 switch (BCSR_WHOAMI_BOARD(whoami)) {
65 case BCSR_WHOAMI_PB1550_SDR:
66 case BCSR_WHOAMI_PB1550_DDR:
67 bcsr_init(PB1550_BCSR_PHYS_ADDR,
68 PB1550_BCSR_PHYS_ADDR + PB1550_BCSR_HEXLED_OFS);
69 break;
70 case BCSR_WHOAMI_DB1550:
71 break;
72 default:
73 return -ENODEV;
74 }
75
76 pr_info("Alchemy/AMD %s Board, CPLD Rev %d Board-ID %d " \
77 "Daughtercard ID %d\n", get_system_type(),
78 (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf);
79
80 db1550_hw_setup();
81 return 0;
82}
83
84/*****************************************************************************/
85
86static u64 au1550_all_dmamask = DMA_BIT_MASK(32);
87
88static struct mtd_partition db1550_spiflash_parts[] = {
89 {
90 .name = "spi_flash",
91 .offset = 0,
92 .size = MTDPART_SIZ_FULL,
93 },
94};
95
96static struct flash_platform_data db1550_spiflash_data = {
97 .name = "s25fl010",
98 .parts = db1550_spiflash_parts,
99 .nr_parts = ARRAY_SIZE(db1550_spiflash_parts),
100 .type = "m25p10",
101};
102
103static struct spi_board_info db1550_spi_devs[] __initdata = {
104 {
105 /* TI TMP121AIDBVR temp sensor */
106 .modalias = "tmp121",
107 .max_speed_hz = 2400000,
108 .bus_num = 0,
109 .chip_select = 0,
110 .mode = SPI_MODE_0,
111 },
112 {
113 /* Spansion S25FL001D0FMA SPI flash */
114 .modalias = "m25p80",
115 .max_speed_hz = 2400000,
116 .bus_num = 0,
117 .chip_select = 1,
118 .mode = SPI_MODE_0,
119 .platform_data = &db1550_spiflash_data,
120 },
121};
122
123static struct i2c_board_info db1550_i2c_devs[] __initdata = {
124 { I2C_BOARD_INFO("24c04", 0x52),}, /* AT24C04-10 I2C eeprom */
125 { I2C_BOARD_INFO("ne1619", 0x2d),}, /* adm1025-compat hwmon */
126 { I2C_BOARD_INFO("wm8731", 0x1b),}, /* I2S audio codec WM8731 */
127};
128
129/**********************************************************************/
130
131static void au1550_nand_cmd_ctrl(struct nand_chip *this, int cmd,
132 unsigned int ctrl)
133{
134 unsigned long ioaddr = (unsigned long)this->legacy.IO_ADDR_W;
135
136 ioaddr &= 0xffffff00;
137
138 if (ctrl & NAND_CLE) {
139 ioaddr += MEM_STNAND_CMD;
140 } else if (ctrl & NAND_ALE) {
141 ioaddr += MEM_STNAND_ADDR;
142 } else {
143 /* assume we want to r/w real data by default */
144 ioaddr += MEM_STNAND_DATA;
145 }
146 this->legacy.IO_ADDR_R = this->legacy.IO_ADDR_W = (void __iomem *)ioaddr;
147 if (cmd != NAND_CMD_NONE) {
148 __raw_writeb(val: cmd, addr: this->legacy.IO_ADDR_W);
149 wmb();
150 }
151}
152
153static int au1550_nand_device_ready(struct nand_chip *this)
154{
155 return alchemy_rdsmem(AU1000_MEM_STSTAT) & 1;
156}
157
158static struct mtd_partition db1550_nand_parts[] = {
159 {
160 .name = "NAND FS 0",
161 .offset = 0,
162 .size = 8 * 1024 * 1024,
163 },
164 {
165 .name = "NAND FS 1",
166 .offset = MTDPART_OFS_APPEND,
167 .size = MTDPART_SIZ_FULL
168 },
169};
170
171struct platform_nand_data db1550_nand_platdata = {
172 .chip = {
173 .nr_chips = 1,
174 .chip_offset = 0,
175 .nr_partitions = ARRAY_SIZE(db1550_nand_parts),
176 .partitions = db1550_nand_parts,
177 .chip_delay = 20,
178 },
179 .ctrl = {
180 .dev_ready = au1550_nand_device_ready,
181 .cmd_ctrl = au1550_nand_cmd_ctrl,
182 },
183};
184
185static struct resource db1550_nand_res[] = {
186 [0] = {
187 .start = 0x20000000,
188 .end = 0x200000ff,
189 .flags = IORESOURCE_MEM,
190 },
191};
192
193static struct platform_device db1550_nand_dev = {
194 .name = "gen_nand",
195 .num_resources = ARRAY_SIZE(db1550_nand_res),
196 .resource = db1550_nand_res,
197 .id = -1,
198 .dev = {
199 .platform_data = &db1550_nand_platdata,
200 }
201};
202
203static struct au1550nd_platdata pb1550_nand_pd = {
204 .parts = db1550_nand_parts,
205 .num_parts = ARRAY_SIZE(db1550_nand_parts),
206 .devwidth = 0, /* x8 NAND default, needs fixing up */
207};
208
209static struct platform_device pb1550_nand_dev = {
210 .name = "au1550-nand",
211 .id = -1,
212 .resource = db1550_nand_res,
213 .num_resources = ARRAY_SIZE(db1550_nand_res),
214 .dev = {
215 .platform_data = &pb1550_nand_pd,
216 },
217};
218
219static void __init pb1550_nand_setup(void)
220{
221 int boot_swapboot = (alchemy_rdsmem(AU1000_MEM_STSTAT) & (0x7 << 1)) |
222 ((bcsr_read(BCSR_STATUS) >> 6) & 0x1);
223
224 gpio_direction_input(gpio: 206); /* de-assert NAND CS# */
225 switch (boot_swapboot) {
226 case 0: case 2: case 8: case 0xC: case 0xD:
227 /* x16 NAND Flash */
228 pb1550_nand_pd.devwidth = 1;
229 fallthrough;
230 case 1: case 3: case 9: case 0xE: case 0xF:
231 /* x8 NAND, already set up */
232 platform_device_register(&pb1550_nand_dev);
233 }
234}
235
236/**********************************************************************/
237
238static struct resource au1550_psc0_res[] = {
239 [0] = {
240 .start = AU1550_PSC0_PHYS_ADDR,
241 .end = AU1550_PSC0_PHYS_ADDR + 0xfff,
242 .flags = IORESOURCE_MEM,
243 },
244 [1] = {
245 .start = AU1550_PSC0_INT,
246 .end = AU1550_PSC0_INT,
247 .flags = IORESOURCE_IRQ,
248 },
249 [2] = {
250 .start = AU1550_DSCR_CMD0_PSC0_TX,
251 .end = AU1550_DSCR_CMD0_PSC0_TX,
252 .flags = IORESOURCE_DMA,
253 },
254 [3] = {
255 .start = AU1550_DSCR_CMD0_PSC0_RX,
256 .end = AU1550_DSCR_CMD0_PSC0_RX,
257 .flags = IORESOURCE_DMA,
258 },
259};
260
261static void db1550_spi_cs_en(struct au1550_spi_info *spi, int cs, int pol)
262{
263 if (cs)
264 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SPISEL);
265 else
266 bcsr_mod(BCSR_BOARD, BCSR_BOARD_SPISEL, 0);
267}
268
269static struct au1550_spi_info db1550_spi_platdata = {
270 .mainclk_hz = 48000000, /* PSC0 clock: max. 2.4MHz SPI clk */
271 .num_chipselect = 2,
272 .activate_cs = db1550_spi_cs_en,
273};
274
275
276static struct platform_device db1550_spi_dev = {
277 .dev = {
278 .dma_mask = &au1550_all_dmamask,
279 .coherent_dma_mask = DMA_BIT_MASK(32),
280 .platform_data = &db1550_spi_platdata,
281 },
282 .name = "au1550-spi",
283 .id = 0, /* bus number */
284 .num_resources = ARRAY_SIZE(au1550_psc0_res),
285 .resource = au1550_psc0_res,
286};
287
288/**********************************************************************/
289
290static struct resource au1550_psc1_res[] = {
291 [0] = {
292 .start = AU1550_PSC1_PHYS_ADDR,
293 .end = AU1550_PSC1_PHYS_ADDR + 0xfff,
294 .flags = IORESOURCE_MEM,
295 },
296 [1] = {
297 .start = AU1550_PSC1_INT,
298 .end = AU1550_PSC1_INT,
299 .flags = IORESOURCE_IRQ,
300 },
301 [2] = {
302 .start = AU1550_DSCR_CMD0_PSC1_TX,
303 .end = AU1550_DSCR_CMD0_PSC1_TX,
304 .flags = IORESOURCE_DMA,
305 },
306 [3] = {
307 .start = AU1550_DSCR_CMD0_PSC1_RX,
308 .end = AU1550_DSCR_CMD0_PSC1_RX,
309 .flags = IORESOURCE_DMA,
310 },
311};
312
313static struct platform_device db1550_ac97_dev = {
314 .name = "au1xpsc_ac97",
315 .id = 1, /* PSC ID */
316 .num_resources = ARRAY_SIZE(au1550_psc1_res),
317 .resource = au1550_psc1_res,
318};
319
320
321static struct resource au1550_psc2_res[] = {
322 [0] = {
323 .start = AU1550_PSC2_PHYS_ADDR,
324 .end = AU1550_PSC2_PHYS_ADDR + 0xfff,
325 .flags = IORESOURCE_MEM,
326 },
327 [1] = {
328 .start = AU1550_PSC2_INT,
329 .end = AU1550_PSC2_INT,
330 .flags = IORESOURCE_IRQ,
331 },
332 [2] = {
333 .start = AU1550_DSCR_CMD0_PSC2_TX,
334 .end = AU1550_DSCR_CMD0_PSC2_TX,
335 .flags = IORESOURCE_DMA,
336 },
337 [3] = {
338 .start = AU1550_DSCR_CMD0_PSC2_RX,
339 .end = AU1550_DSCR_CMD0_PSC2_RX,
340 .flags = IORESOURCE_DMA,
341 },
342};
343
344static struct platform_device db1550_i2c_dev = {
345 .name = "au1xpsc_smbus",
346 .id = 0, /* bus number */
347 .num_resources = ARRAY_SIZE(au1550_psc2_res),
348 .resource = au1550_psc2_res,
349};
350
351/**********************************************************************/
352
353static struct resource au1550_psc3_res[] = {
354 [0] = {
355 .start = AU1550_PSC3_PHYS_ADDR,
356 .end = AU1550_PSC3_PHYS_ADDR + 0xfff,
357 .flags = IORESOURCE_MEM,
358 },
359 [1] = {
360 .start = AU1550_PSC3_INT,
361 .end = AU1550_PSC3_INT,
362 .flags = IORESOURCE_IRQ,
363 },
364 [2] = {
365 .start = AU1550_DSCR_CMD0_PSC3_TX,
366 .end = AU1550_DSCR_CMD0_PSC3_TX,
367 .flags = IORESOURCE_DMA,
368 },
369 [3] = {
370 .start = AU1550_DSCR_CMD0_PSC3_RX,
371 .end = AU1550_DSCR_CMD0_PSC3_RX,
372 .flags = IORESOURCE_DMA,
373 },
374};
375
376static struct platform_device db1550_i2s_dev = {
377 .name = "au1xpsc_i2s",
378 .id = 3, /* PSC ID */
379 .num_resources = ARRAY_SIZE(au1550_psc3_res),
380 .resource = au1550_psc3_res,
381};
382
383/**********************************************************************/
384
385static struct platform_device db1550_stac_dev = {
386 .name = "ac97-codec",
387 .id = 1, /* on PSC1 */
388};
389
390static struct platform_device db1550_ac97dma_dev = {
391 .name = "au1xpsc-pcm",
392 .id = 1, /* on PSC3 */
393};
394
395static struct platform_device db1550_i2sdma_dev = {
396 .name = "au1xpsc-pcm",
397 .id = 3, /* on PSC3 */
398};
399
400static struct platform_device db1550_sndac97_dev = {
401 .name = "db1550-ac97",
402 .dev = {
403 .dma_mask = &au1550_all_dmamask,
404 .coherent_dma_mask = DMA_BIT_MASK(32),
405 },
406};
407
408static struct platform_device db1550_sndi2s_dev = {
409 .name = "db1550-i2s",
410 .dev = {
411 .dma_mask = &au1550_all_dmamask,
412 .coherent_dma_mask = DMA_BIT_MASK(32),
413 },
414};
415
416/**********************************************************************/
417
418static int db1550_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
419{
420 if ((slot < 11) || (slot > 13) || pin == 0)
421 return -1;
422 if (slot == 11)
423 return (pin == 1) ? AU1550_PCI_INTC : 0xff;
424 if (slot == 12) {
425 switch (pin) {
426 case 1: return AU1550_PCI_INTB;
427 case 2: return AU1550_PCI_INTC;
428 case 3: return AU1550_PCI_INTD;
429 case 4: return AU1550_PCI_INTA;
430 }
431 }
432 if (slot == 13) {
433 switch (pin) {
434 case 1: return AU1550_PCI_INTA;
435 case 2: return AU1550_PCI_INTB;
436 case 3: return AU1550_PCI_INTC;
437 case 4: return AU1550_PCI_INTD;
438 }
439 }
440 return -1;
441}
442
443static int pb1550_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
444{
445 if ((slot < 12) || (slot > 13) || pin == 0)
446 return -1;
447 if (slot == 12) {
448 switch (pin) {
449 case 1: return AU1500_PCI_INTB;
450 case 2: return AU1500_PCI_INTC;
451 case 3: return AU1500_PCI_INTD;
452 case 4: return AU1500_PCI_INTA;
453 }
454 }
455 if (slot == 13) {
456 switch (pin) {
457 case 1: return AU1500_PCI_INTA;
458 case 2: return AU1500_PCI_INTB;
459 case 3: return AU1500_PCI_INTC;
460 case 4: return AU1500_PCI_INTD;
461 }
462 }
463 return -1;
464}
465
466static struct resource alchemy_pci_host_res[] = {
467 [0] = {
468 .start = AU1500_PCI_PHYS_ADDR,
469 .end = AU1500_PCI_PHYS_ADDR + 0xfff,
470 .flags = IORESOURCE_MEM,
471 },
472};
473
474static struct alchemy_pci_platdata db1550_pci_pd = {
475 .board_map_irq = db1550_map_pci_irq,
476};
477
478static struct platform_device db1550_pci_host_dev = {
479 .dev.platform_data = &db1550_pci_pd,
480 .name = "alchemy-pci",
481 .id = 0,
482 .num_resources = ARRAY_SIZE(alchemy_pci_host_res),
483 .resource = alchemy_pci_host_res,
484};
485
486/**********************************************************************/
487
488static struct platform_device *db1550_devs[] __initdata = {
489 &db1550_i2c_dev,
490 &db1550_ac97_dev,
491 &db1550_spi_dev,
492 &db1550_i2s_dev,
493 &db1550_stac_dev,
494 &db1550_ac97dma_dev,
495 &db1550_i2sdma_dev,
496 &db1550_sndac97_dev,
497 &db1550_sndi2s_dev,
498};
499
500/* must be arch_initcall; MIPS PCI scans busses in a subsys_initcall */
501int __init db1550_pci_setup(int id)
502{
503 if (id)
504 db1550_pci_pd.board_map_irq = pb1550_map_pci_irq;
505 return platform_device_register(&db1550_pci_host_dev);
506}
507
508static void __init db1550_devices(void)
509{
510 alchemy_gpio_direction_output(203, 0); /* red led on */
511
512 irq_set_irq_type(AU1550_GPIO0_INT, IRQ_TYPE_EDGE_BOTH); /* CD0# */
513 irq_set_irq_type(AU1550_GPIO1_INT, IRQ_TYPE_EDGE_BOTH); /* CD1# */
514 irq_set_irq_type(AU1550_GPIO3_INT, IRQ_TYPE_LEVEL_LOW); /* CARD0# */
515 irq_set_irq_type(AU1550_GPIO5_INT, IRQ_TYPE_LEVEL_LOW); /* CARD1# */
516 irq_set_irq_type(AU1550_GPIO21_INT, IRQ_TYPE_LEVEL_LOW); /* STSCHG0# */
517 irq_set_irq_type(AU1550_GPIO22_INT, IRQ_TYPE_LEVEL_LOW); /* STSCHG1# */
518
519 db1x_register_pcmcia_socket(
520 AU1000_PCMCIA_ATTR_PHYS_ADDR,
521 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
522 AU1000_PCMCIA_MEM_PHYS_ADDR,
523 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
524 AU1000_PCMCIA_IO_PHYS_ADDR,
525 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
526 AU1550_GPIO3_INT, 0,
527 /*AU1550_GPIO21_INT*/0, 0, 0);
528
529 db1x_register_pcmcia_socket(
530 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
531 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
532 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000,
533 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1,
534 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000,
535 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1,
536 AU1550_GPIO5_INT, 1,
537 /*AU1550_GPIO22_INT*/0, 0, 1);
538
539 platform_device_register(&db1550_nand_dev);
540
541 alchemy_gpio_direction_output(202, 0); /* green led on */
542}
543
544static void __init pb1550_devices(void)
545{
546 irq_set_irq_type(AU1550_GPIO0_INT, IRQ_TYPE_LEVEL_LOW);
547 irq_set_irq_type(AU1550_GPIO1_INT, IRQ_TYPE_LEVEL_LOW);
548 irq_set_irq_type(AU1550_GPIO201_205_INT, IRQ_TYPE_LEVEL_HIGH);
549
550 /* enable both PCMCIA card irqs in the shared line */
551 alchemy_gpio2_enable_int(201); /* socket 0 card irq */
552 alchemy_gpio2_enable_int(202); /* socket 1 card irq */
553
554 /* Pb1550, like all others, also has statuschange irqs; however they're
555 * wired up on one of the Au1550's shared GPIO201_205 line, which also
556 * services the PCMCIA card interrupts. So we ignore statuschange and
557 * use the GPIO201_205 exclusively for card interrupts, since a) pcmcia
558 * drivers are used to shared irqs and b) statuschange isn't really use-
559 * ful anyway.
560 */
561 db1x_register_pcmcia_socket(
562 AU1000_PCMCIA_ATTR_PHYS_ADDR,
563 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
564 AU1000_PCMCIA_MEM_PHYS_ADDR,
565 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
566 AU1000_PCMCIA_IO_PHYS_ADDR,
567 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
568 AU1550_GPIO201_205_INT, AU1550_GPIO0_INT, 0, 0, 0);
569
570 db1x_register_pcmcia_socket(
571 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008000000,
572 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008400000 - 1,
573 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x008000000,
574 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x008400000 - 1,
575 AU1000_PCMCIA_IO_PHYS_ADDR + 0x008000000,
576 AU1000_PCMCIA_IO_PHYS_ADDR + 0x008010000 - 1,
577 AU1550_GPIO201_205_INT, AU1550_GPIO1_INT, 0, 0, 1);
578
579 pb1550_nand_setup();
580}
581
582int __init db1550_dev_setup(void)
583{
584 int swapped, id;
585 struct clk *c;
586
587 id = (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) != BCSR_WHOAMI_DB1550);
588
589 i2c_register_board_info(busnum: 0, info: db1550_i2c_devs,
590 ARRAY_SIZE(db1550_i2c_devs));
591 spi_register_board_info(info: db1550_spi_devs,
592 ARRAY_SIZE(db1550_spi_devs));
593
594 c = clk_get(NULL, id: "psc0_intclk");
595 if (!IS_ERR(ptr: c)) {
596 clk_set_rate(clk: c, rate: 50000000);
597 clk_prepare_enable(clk: c);
598 clk_put(clk: c);
599 }
600 c = clk_get(NULL, id: "psc2_intclk");
601 if (!IS_ERR(ptr: c)) {
602 clk_set_rate(clk: c, rate: db1550_spi_platdata.mainclk_hz);
603 clk_prepare_enable(clk: c);
604 clk_put(clk: c);
605 }
606
607 /* Audio PSC clock is supplied by codecs (PSC1, 3) FIXME: platdata!! */
608 __raw_writel(PSC_SEL_CLK_SERCLK,
609 (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET);
610 wmb();
611 __raw_writel(PSC_SEL_CLK_SERCLK,
612 (void __iomem *)KSEG1ADDR(AU1550_PSC3_PHYS_ADDR) + PSC_SEL_OFFSET);
613 wmb();
614 /* SPI/I2C use internally supplied 50MHz source */
615 __raw_writel(PSC_SEL_CLK_INTCLK,
616 (void __iomem *)KSEG1ADDR(AU1550_PSC0_PHYS_ADDR) + PSC_SEL_OFFSET);
617 wmb();
618 __raw_writel(PSC_SEL_CLK_INTCLK,
619 (void __iomem *)KSEG1ADDR(AU1550_PSC2_PHYS_ADDR) + PSC_SEL_OFFSET);
620 wmb();
621
622 id ? pb1550_devices() : db1550_devices();
623
624 swapped = bcsr_read(BCSR_STATUS) &
625 (id ? BCSR_STATUS_PB1550_SWAPBOOT : BCSR_STATUS_DB1000_SWAPBOOT);
626 db1x_register_norflash(size: 128 << 20, width: 4, swapped);
627
628 return platform_add_devices(db1550_devs, ARRAY_SIZE(db1550_devs));
629}
630

source code of linux/arch/mips/alchemy/devboards/db1550.c