From fed466c264ad078c66f7bff9218ba1d3fa0eb201 Mon Sep 17 00:00:00 2001 From: Fabio Baltieri Date: Tue, 19 Jul 2022 15:53:26 +0000 Subject: [PATCH 01/39] include: add "zephyr/" include prefix Add relevant "zephyr/" prefixes to allow building with LEGACY_INCLUDE_PATH=n. Signed-off-by: Fabio Baltieri --- src/include/sof/debug/panic.h | 2 +- src/include/sof/schedule/task.h | 2 +- src/include/sof/spinlock.h | 2 +- src/lib/agent.c | 2 +- src/platform/imx8/lib/clk.c | 2 +- src/platform/imx8m/lib/clk.c | 2 +- src/schedule/zephyr.c | 4 ++-- src/schedule/zephyr_domain.c | 4 ++-- src/schedule/zephyr_ll.c | 2 +- zephyr/edf_schedule.c | 4 ++-- zephyr/include/sof/atomic.h | 2 +- zephyr/include/sof/trace/trace.h | 4 ++-- zephyr/wrapper.c | 6 +++--- 13 files changed, 19 insertions(+), 19 deletions(-) diff --git a/src/include/sof/debug/panic.h b/src/include/sof/debug/panic.h index e23e5af8372f..fa019dafc08e 100644 --- a/src/include/sof/debug/panic.h +++ b/src/include/sof/debug/panic.h @@ -31,7 +31,7 @@ void panic_dump(uint32_t p, struct sof_ipc_panic_info *panic_info, SOF_NORETURN; #ifdef __ZEPHYR__ -#include +#include #define panic(x) k_panic() #define assert(x) \ diff --git a/src/include/sof/schedule/task.h b/src/include/sof/schedule/task.h index 191ca28b627d..f5fb4f1fe79e 100644 --- a/src/include/sof/schedule/task.h +++ b/src/include/sof/schedule/task.h @@ -15,7 +15,7 @@ #include #ifdef __ZEPHYR__ -#include +#include #endif struct comp_dev; diff --git a/src/include/sof/spinlock.h b/src/include/sof/spinlock.h index 70521ed645fe..ce17dc1b6a5d 100644 --- a/src/include/sof/spinlock.h +++ b/src/include/sof/spinlock.h @@ -166,7 +166,7 @@ void _k_spin_unlock_irq(struct k_spinlock *lock, k_spinlock_key_t key, int line) #else -#include +#include /* This has to be moved to Zephyr */ static inline void k_spinlock_init(struct k_spinlock *lock) diff --git a/src/lib/agent.c b/src/lib/agent.c index ad32d35759ef..42c45ed57daf 100644 --- a/src/lib/agent.c +++ b/src/lib/agent.c @@ -35,7 +35,7 @@ #include #ifdef __ZEPHYR__ -#include +#include #endif /* 5276b491-5b64-464e-8984-dc228ef9e6a1 */ diff --git a/src/platform/imx8/lib/clk.c b/src/platform/imx8/lib/clk.c index ab4db8910b8c..45d014b56417 100644 --- a/src/platform/imx8/lib/clk.c +++ b/src/platform/imx8/lib/clk.c @@ -13,7 +13,7 @@ #include #ifdef __ZEPHYR__ -#include +#include #endif const struct freq_table platform_cpu_freq[] = { diff --git a/src/platform/imx8m/lib/clk.c b/src/platform/imx8m/lib/clk.c index d16f328bd5b2..666e455c17f1 100644 --- a/src/platform/imx8m/lib/clk.c +++ b/src/platform/imx8m/lib/clk.c @@ -12,7 +12,7 @@ #include #ifdef __ZEPHYR__ -#include +#include #endif const struct freq_table platform_cpu_freq[] = { diff --git a/src/schedule/zephyr.c b/src/schedule/zephyr.c index 5db1a660291d..a616ad9a8974 100644 --- a/src/schedule/zephyr.c +++ b/src/schedule/zephyr.c @@ -19,9 +19,9 @@ * send tasks to other CPUs. */ -#include +#include -#include +#include #include #include #include diff --git a/src/schedule/zephyr_domain.c b/src/schedule/zephyr_domain.c index 397916a34d4d..512c55bf0dda 100644 --- a/src/schedule/zephyr_domain.c +++ b/src/schedule/zephyr_domain.c @@ -20,8 +20,8 @@ #include #include -#include -#include +#include +#include /* * Currently the Zephyr clock rate is part it's Kconfig known at build time. diff --git a/src/schedule/zephyr_ll.c b/src/schedule/zephyr_ll.c index 86182cfd0a9a..7b33c942a01f 100644 --- a/src/schedule/zephyr_ll.c +++ b/src/schedule/zephyr_ll.c @@ -13,7 +13,7 @@ #include #include -#include +#include /* 1547fe68-de0c-11eb-8461-3158a1294853 */ DECLARE_SOF_UUID("zll-schedule", zll_sched_uuid, 0x1547fe68, 0xde0c, 0x11eb, diff --git a/zephyr/edf_schedule.c b/zephyr/edf_schedule.c index 4abecc1dd3f6..a8e4d7fbcb38 100644 --- a/zephyr/edf_schedule.c +++ b/zephyr/edf_schedule.c @@ -10,8 +10,8 @@ #include #include -#include -#include +#include +#include struct k_work_q edf_workq; K_THREAD_STACK_DEFINE(edf_workq_stack, 8192); diff --git a/zephyr/include/sof/atomic.h b/zephyr/include/sof/atomic.h index ceab603b3cb4..92ff9d7c9d48 100644 --- a/zephyr/include/sof/atomic.h +++ b/zephyr/include/sof/atomic.h @@ -6,7 +6,7 @@ #ifndef __INCLUDE_ATOMIC_H_ #define __INCLUDE_ATOMIC_H_ -#include +#include /* Zephyr commit 174cb7f9f183 switched 'atomic_t' from 'int' to * 'long'. As we don't support 64 bits, this should have made no diff --git a/zephyr/include/sof/trace/trace.h b/zephyr/include/sof/trace/trace.h index caeeada6eab5..bc484719b3d2 100644 --- a/zephyr/include/sof/trace/trace.h +++ b/zephyr/include/sof/trace/trace.h @@ -7,8 +7,8 @@ #define __SOF_TRACE_TRACE1_H__ #ifndef ZEPHYR_INCLUDE_LOGGING_LOG_H_ -#include -#include +#include +#include /* Level of SOF trace on Zephyr */ #define SOF_ZEPHYR_TRACE_LEVEL LOG_LEVEL_INF diff --git a/zephyr/wrapper.c b/zephyr/wrapper.c index 26135ffa0a8d..47466adc0f16 100644 --- a/zephyr/wrapper.c +++ b/zephyr/wrapper.c @@ -22,13 +22,13 @@ #include /* Zephyr includes */ -#include +#include #include -#include +#include #include #if !CONFIG_KERNEL_COHERENCE -#include +#include #endif extern K_KERNEL_STACK_ARRAY_DEFINE(z_interrupt_stacks, CONFIG_MP_NUM_CPUS, From 75a588c937c3c5627ced10bc2f3ccaa9d07ad582 Mon Sep 17 00:00:00 2001 From: Damian Nikodem Date: Thu, 8 Sep 2022 13:36:39 +0200 Subject: [PATCH 02/39] xtensa-build-zephyr: pass sof build version to rimage Rimage expects to receive fw_ver_build to prepare the manifest. Signed-off-by: Damian Nikodem --- scripts/xtensa-build-zephyr.py | 34 +++++++++++++++++++++------------- 1 file changed, 21 insertions(+), 13 deletions(-) diff --git a/scripts/xtensa-build-zephyr.py b/scripts/xtensa-build-zephyr.py index 5562a8881070..cbd82216fa0a 100755 --- a/scripts/xtensa-build-zephyr.py +++ b/scripts/xtensa-build-zephyr.py @@ -33,7 +33,8 @@ west_top = pathlib.Path(SOF_TOP, "..").resolve() default_rimage_key = pathlib.Path(SOF_TOP, "keys", "otc_private_key.pem") -sof_version = None +sof_fw_version = None +sof_build_version = None if py_platform.system() == "Windows": xtensa_tools_version_postfix = "-win32" @@ -387,16 +388,17 @@ def west_update(): execute_command(["west", "update"], check=True, timeout=3000, cwd=west_top) -def get_sof_version(abs_build_dir): - """[summary] Get version string major.minor.micro of SOF firmware - file. When building multiple platforms from the same SOF commit, - all platforms share the same version. So for the 1st platform, - generate the version string from sof_version.h and later platforms - will reuse it. +def get_build_and_sof_version(abs_build_dir): + """[summary] Get version string major.minor.micro and build of SOF + firmware file. When building multiple platforms from the same SOF + commit, all platforms share the same version. So for the 1st platform, + generate the version string from sof_version.h and later platforms will + reuse it. """ - global sof_version - if sof_version: - return sof_version + global sof_fw_version + global sof_build_version + if sof_fw_version and sof_build_version: + return sof_fw_version, sof_build_version versions = {} with open(pathlib.Path(abs_build_dir, @@ -405,9 +407,11 @@ def get_sof_version(abs_build_dir): words = hline.split() if words[0] == '#define': versions[words[1]] = words[2] - sof_version = versions['SOF_MAJOR'] + '.' + versions['SOF_MINOR'] + '.' + \ + sof_fw_version = versions['SOF_MAJOR'] + '.' + versions['SOF_MINOR'] + '.' + \ versions['SOF_MICRO'] - return sof_version + sof_build_version = versions['SOF_BUILD'] + + return sof_fw_version, sof_build_version def build_platforms(): global west_top, SOF_TOP @@ -540,7 +544,11 @@ def build_platforms(): sign_cmd += ["--tool-data", str(rimage_config), "--", "-k", str(signing_key)] - sign_cmd += ["-f", get_sof_version(abs_build_dir)] + sof_fw_version, sof_build_version = get_build_and_sof_version(abs_build_dir) + + sign_cmd += ["-f", sof_fw_version] + + sign_cmd += ["-b", sof_build_version] if args.fw_naming == "AVS": output_fwname="dsp_basefw.bin" From 7f0d64a73610d31af93499415ad2a44ee66a4d18 Mon Sep 17 00:00:00 2001 From: Kai Vehmanen Date: Mon, 12 Sep 2022 12:24:58 +0300 Subject: [PATCH 03/39] west.yml: upgrade Zephyr to 3.2.0-rc1 level Update Zephyr to 0956647aaf6bd2b1e840adcc86db503f274d84a9 (3.2.0-rc1 plus a few fixes merged to upstreamed after the tag). Signed-off-by: Kai Vehmanen --- west.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/west.yml b/west.yml index 7caefdef5b69..3e99e8df9675 100644 --- a/west.yml +++ b/west.yml @@ -24,7 +24,7 @@ manifest: - name: zephyr repo-path: zephyr - revision: dcda3eab8df7e9b25cdf038232abcb0ddc174461 + revision: 0956647aaf6bd2b1e840adcc86db503f274d84a9 remote: zephyrproject # Import some projects listed in zephyr/west.yml@revision # From 0e0468bf967b4ea796a12f1d40ea88ad59282f3d Mon Sep 17 00:00:00 2001 From: Rander Wang Date: Tue, 13 Sep 2022 10:56:47 +0800 Subject: [PATCH 04/39] topology2: add lp_mode as a attribute in pipeline Currently lp_mode setting is not included by topology binary since lp_mode is not defined as a attribute. This patch adds it in pipeline. Signed-off-by: Rander Wang --- .../topology2/include/components/pipeline.conf | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/tools/topology/topology2/include/components/pipeline.conf b/tools/topology/topology2/include/components/pipeline.conf index 0829eac963eb..e9789cd9874e 100644 --- a/tools/topology/topology2/include/components/pipeline.conf +++ b/tools/topology/topology2/include/components/pipeline.conf @@ -84,6 +84,17 @@ Class.Widget."pipeline" { token_ref "sof_tkn_scheduler.word" } + DefineAttribute."lp_mode" { + # Token reference and type + token_ref "sof_tkn_scheduler.word" + constraints { + !tuple_values [ + 1 + 0 + ] + } + } + attributes { # pipeline widget name will be constructed as pipeline.1, pipeline.2 etc !constructor [ From 25026383fe6390b40da44688d0b9dccbe276217e Mon Sep 17 00:00:00 2001 From: Ranjani Sridharan Date: Wed, 14 Sep 2022 16:50:50 -0700 Subject: [PATCH 05/39] test: volume: remove unused code Volume component no longer does format conversion. Remove the unused test code. Signed-off-by: Ranjani Sridharan --- test/cmocka/src/audio/volume/volume_process.c | 89 ------------------- 1 file changed, 89 deletions(-) diff --git a/test/cmocka/src/audio/volume/volume_process.c b/test/cmocka/src/audio/volume/volume_process.c index a0a51b76979d..6b75b6f29f35 100644 --- a/test/cmocka/src/audio/volume/volume_process.c +++ b/test/cmocka/src/audio/volume/volume_process.c @@ -312,95 +312,6 @@ static void verify_s32_to_s24_s32(struct processing_module *mod, } #endif /* CONFIG_FORMAT_S32LE */ -#if 0 - -#if CONFIG_FORMAT_S16LE && (CONFIG_FORMAT_S24LE || CONFIG_FORMAT_S32LE) -static void verify_s16_to_sX(struct comp_dev *dev, struct comp_buffer *sink, - struct comp_buffer *source) -{ - struct vol_data *cd = comp_get_drvdata(dev); - const int16_t *src = (int16_t *)source->r_ptr; - const int32_t *dst = (int32_t *)sink->w_ptr; - double processed; - int32_t dst_sample; - int32_t sample; - int channels = sink->channels; - int channel; - int delta; - int i; - int shift = 0; - - /* get shift value */ - if (cd->sink_format == SOF_IPC_FRAME_S24_4LE) - shift = 8; - else if (cd->sink_format == SOF_IPC_FRAME_S32_LE) - shift = 0; - - for (i = 0; i < sink->size / sizeof(uint32_t); i += channels) { - for (channel = 0; channel < channels; channel++) { - processed = 65536.0 * (double)src[i + channel] * - (double)cd->volume[channel] / - (double)VOL_ZERO_DB + 0.5 * (1 << shift); - if (processed > INT32_MAX) - processed = INT32_MAX; - - if (processed < INT32_MIN) - processed = INT32_MIN; - - sample = ((int32_t)processed) >> shift; - dst_sample = dst[i + channel]; - delta = dst_sample - sample; - if (delta > 1 || delta < -1) - assert_int_equal(dst_sample, sample); - - if (shift && (dst_sample < INT24_MIN || - dst_sample > INT24_MAX)) - assert_int_equal(dst_sample, sample); - } - } -} - -static void verify_sX_to_s16(struct comp_dev *dev, struct comp_buffer *sink, - struct comp_buffer *source) -{ - struct vol_data *cd = comp_get_drvdata(dev); - const int32_t *src = (int32_t *)source->r_ptr; - const int16_t *dst = (int16_t *)sink->w_ptr; - double processed; - int channels = dev->params.channels; - int channel; - int delta; - int i; - int shift = 0; - int16_t sample; - - /* get shift value */ - if (cd->source_format == SOF_IPC_FRAME_S24_4LE) - shift = 8; - - for (i = 0; i < sink->size / sizeof(uint16_t); i += channels) { - for (channel = 0; channel < channels; channel++) { - processed = (double)(src[i + channel] << shift) * - (double)cd->volume[channel] / - (double)VOL_ZERO_DB; - processed = processed / 65536.0 + 0.5; - if (processed > INT16_MAX) - processed = INT16_MAX; - - if (processed < INT16_MIN) - processed = INT16_MIN; - - sample = (int16_t)processed; - delta = dst[i + channel] - sample; - if (delta > 1 || delta < -1) - assert_int_equal(dst[i + channel], sample); - } - } -} -#endif /* CONFIG_FORMAT_S16LE && (CONFIG_FORMAT_S24LE || CONFIG_FORMAT_S32LE) */ - -#endif - static void test_audio_vol(void **state) { struct vol_test_state *vol_state = *state; From d811c56d100b045096c2a991a93aa1054e6969a2 Mon Sep 17 00:00:00 2001 From: Ranjani Sridharan Date: Wed, 14 Sep 2022 16:47:11 -0700 Subject: [PATCH 06/39] test: Add test infrastructure for module adapter Add the test infrastructure for setting up and freeing a module and use it in the volume unit test. Signed-off-by: Ranjani Sridharan --- test/cmocka/src/audio/module_adapter.h | 30 ++++ test/cmocka/src/audio/module_adapter_test.c | 90 +++++++++++ test/cmocka/src/audio/volume/CMakeLists.txt | 2 +- test/cmocka/src/audio/volume/volume_process.c | 153 ++++++------------ 4 files changed, 169 insertions(+), 106 deletions(-) create mode 100644 test/cmocka/src/audio/module_adapter.h create mode 100644 test/cmocka/src/audio/module_adapter_test.c diff --git a/test/cmocka/src/audio/module_adapter.h b/test/cmocka/src/audio/module_adapter.h new file mode 100644 index 000000000000..1f913fa5cbcd --- /dev/null +++ b/test/cmocka/src/audio/module_adapter.h @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: BSD-3-Clause +// +// Copyright(c) 2022 Intel Corporation. All rights reserved. +// + +struct processing_module_test_parameters { + uint32_t channels; + uint32_t frames; + uint32_t buffer_size_ms; + uint32_t source_format; + uint32_t sink_format; + void (*verify)(struct processing_module *mod, struct comp_buffer *sink, + struct comp_buffer *source); +}; + +struct processing_module_test_data { + struct processing_module *mod; + struct comp_buffer **sinks; + struct comp_buffer **sources; + struct input_stream_buffer **input_buffers; + struct output_stream_buffer **output_buffers; + uint32_t num_sources; + uint32_t num_sinks; + struct processing_module_test_parameters parameters; + void (*verify)(struct processing_module *mod, struct comp_buffer *sink, + struct comp_buffer *source); +}; + +int module_adapter_test_setup(struct processing_module_test_data *test_data); +void module_adapter_test_free(struct processing_module_test_data *test_data); diff --git a/test/cmocka/src/audio/module_adapter_test.c b/test/cmocka/src/audio/module_adapter_test.c new file mode 100644 index 000000000000..560c57a6158b --- /dev/null +++ b/test/cmocka/src/audio/module_adapter_test.c @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: BSD-3-Clause +// +// Copyright(c) 2020 Intel Corporation. All rights reserved. +// + +#include "../util.h" + +#include +#include +#include +#include +#include +#include +#include +#include "module_adapter.h" + +int module_adapter_test_setup(struct processing_module_test_data *test_data) +{ + struct processing_module_test_parameters *parameters = &test_data->parameters; + struct processing_module *mod; + struct comp_dev *dev; + uint32_t size; + int i; + + /* allocate and set new device */ + mod = test_malloc(sizeof(struct processing_module)); + test_data->mod = mod; + dev = test_malloc(sizeof(struct comp_dev)); + dev->frames = parameters->frames; + mod->dev = dev; + comp_set_drvdata(dev, mod); + + test_data->sinks = test_calloc(test_data->num_sinks, sizeof(struct comp_buffer *)); + test_data->sources = test_calloc(test_data->num_sources, sizeof(struct comp_buffer *)); + + test_data->input_buffers = test_calloc(test_data->num_sources, + sizeof(struct input_stream_buffer *)); + test_data->output_buffers = test_calloc(test_data->num_sinks, + sizeof(struct output_stream_buffer *)); + + list_init(&dev->bsource_list); + list_init(&dev->bsink_list); + + /* allocate sink buffers */ + size = parameters->frames * + get_frame_bytes(parameters->sink_format, parameters->channels) * + parameters->buffer_size_ms; + for (i = 0; i < test_data->num_sinks; i++) { + test_data->sinks[i] = create_test_sink(dev, 0, parameters->sink_format, + parameters->channels, size); + test_data->output_buffers[i] = test_malloc(sizeof(struct output_stream_buffer)); + test_data->output_buffers[i]->data = &test_data->sinks[i]->stream; + } + + /* allocate source buffers */ + size = parameters->frames * get_frame_bytes(parameters->source_format, + parameters->channels) * parameters->buffer_size_ms; + for (i = 0; i < test_data->num_sources; i++) { + test_data->sources[i] = create_test_source(dev, 0, parameters->source_format, + parameters->channels, size); + test_data->input_buffers[i] = test_malloc(sizeof(struct input_stream_buffer)); + test_data->input_buffers[i]->data = &test_data->sources[i]->stream; + } + + test_data->verify = parameters->verify; + + return 0; +} + +void module_adapter_test_free(struct processing_module_test_data *test_data) +{ + int i; + + for (i = 0; i < test_data->num_sinks; i++) { + free_test_sink(test_data->sinks[i]); + test_free(test_data->output_buffers[i]); + } + + for (i = 0; i < test_data->num_sources; i++) { + free_test_sink(test_data->sources[i]); + test_free(test_data->input_buffers[i]); + } + + test_free(test_data->input_buffers); + test_free(test_data->output_buffers); + test_free(test_data->sinks); + test_free(test_data->sources); + test_free(test_data->mod->dev); + test_free(test_data->mod); +} diff --git a/test/cmocka/src/audio/volume/CMakeLists.txt b/test/cmocka/src/audio/volume/CMakeLists.txt index e5f7051e8a6e..8e25f1685ad8 100644 --- a/test/cmocka/src/audio/volume/CMakeLists.txt +++ b/test/cmocka/src/audio/volume/CMakeLists.txt @@ -1,7 +1,7 @@ # SPDX-License-Identifier: BSD-3-Clause cmocka_test(volume_process - volume_process.c + volume_process.c ../module_adapter_test.c ) target_include_directories(volume_process PRIVATE ${PROJECT_SOURCE_DIR}/src/audio) diff --git a/test/cmocka/src/audio/volume/volume_process.c b/test/cmocka/src/audio/volume/volume_process.c index 6b75b6f29f35..1ae0277b758e 100644 --- a/test/cmocka/src/audio/volume/volume_process.c +++ b/test/cmocka/src/audio/volume/volume_process.c @@ -14,6 +14,7 @@ #include #include #include +#include "../module_adapter.h" /* Add macro for a volume test level. The levels to test with this code * are: @@ -30,27 +31,9 @@ /* Min S24_4LE format value */ #define INT24_MIN -8388608 -struct vol_test_state { - struct processing_module *mod; - struct comp_buffer *sink; - struct comp_buffer *source; - struct input_stream_buffer *input; - struct output_stream_buffer *output; - size_t size; - uint32_t channels; - void (*verify)(struct processing_module *mod, struct comp_buffer *sink, - struct comp_buffer *source); -}; - struct vol_test_parameters { int32_t volume; - uint32_t channels; - uint32_t frames; - uint32_t buffer_size_ms; - uint32_t source_format; - uint32_t sink_format; - void (*verify)(struct processing_module *mod, struct comp_buffer *sink, - struct comp_buffer *source); + struct processing_module_test_parameters module_parameters; }; static void set_volume(int32_t *vol, int32_t value, uint32_t channels) @@ -63,26 +46,21 @@ static void set_volume(int32_t *vol, int32_t value, uint32_t channels) static int setup(void **state) { - struct vol_test_parameters *parameters = *state; - struct vol_test_state *vol_state; + struct vol_test_parameters *vol_parameters = *state; + struct processing_module_test_data *vol_state; struct module_data *md; - struct comp_dev *dev; struct vol_data *cd; - uint32_t size = 0; /* allocate new state */ vol_state = test_malloc(sizeof(*vol_state)); - - /* allocate and set new device */ - vol_state->mod = test_malloc(sizeof(struct processing_module)); - dev = test_malloc(sizeof(struct comp_dev)); - dev->frames = parameters->frames; + vol_state->parameters = vol_parameters->module_parameters; + vol_state->num_sources = 1; + vol_state->num_sinks = 1; + module_adapter_test_setup(vol_state); /* allocate and set new data */ - vol_state->mod->dev = dev; cd = test_malloc(sizeof(*cd)); md = &vol_state->mod->priv; - comp_set_drvdata(dev, vol_state->mod); md->private = cd; /* malloc memory to store current volume 4 times to ensure the address @@ -92,37 +70,9 @@ static int setup(void **state) cd->vol = test_malloc(vol_size); - list_init(&dev->bsource_list); - list_init(&dev->bsink_list); - - /* allocate new sink buffer */ - size = parameters->frames * get_frame_bytes(parameters->sink_format, parameters->channels) * - parameters->buffer_size_ms; - vol_state->size = size; - vol_state->channels = parameters->channels; - - vol_state->sink = create_test_sink(dev, 0, parameters->sink_format, - parameters->channels, size); - - /* allocate new source buffer */ - size = parameters->frames * get_frame_bytes(parameters->source_format, - parameters->channels) * parameters->buffer_size_ms; - - vol_state->source = create_test_source(dev, 0, parameters->source_format, - parameters->channels, size); - - /* allocate intermediate buffers */ - vol_state->input = test_malloc(sizeof(struct input_stream_buffer)); - vol_state->input->data = &vol_state->source->stream; - vol_state->output = test_malloc(sizeof(struct output_stream_buffer)); - vol_state->output->data = &vol_state->sink->stream; - /* set processing function and volume */ - cd->scale_vol = vol_get_processing_function(dev, vol_state->sink); - set_volume(cd->volume, parameters->volume, parameters->channels); - - /* assigns verification function */ - vol_state->verify = parameters->verify; + cd->scale_vol = vol_get_processing_function(vol_state->mod->dev, vol_state->sinks[0]); + set_volume(cd->volume, vol_parameters->volume, vol_state->parameters.channels); /* assign test state */ *state = vol_state; @@ -132,32 +82,26 @@ static int setup(void **state) static int teardown(void **state) { - struct vol_test_state *vol_state = *state; + struct processing_module_test_data *vol_state = *state; struct vol_data *cd = module_get_private_data(vol_state->mod); - /* free everything */ test_free(cd->vol); test_free(cd); - test_free(vol_state->mod->dev); - test_free(vol_state->mod); - test_free(vol_state->input); - test_free(vol_state->output); - free_test_sink(vol_state->sink); - free_test_source(vol_state->source); + module_adapter_test_free(vol_state); test_free(vol_state); return 0; } #if CONFIG_FORMAT_S16LE -static void fill_source_s16(struct vol_test_state *vol_state) +static void fill_source_s16(struct processing_module_test_data *vol_state) { int64_t val; - int16_t *src = (int16_t *)vol_state->source->stream.r_ptr; + int16_t *src = (int16_t *)vol_state->sources[0]->stream.r_ptr; int i; int sign = 1; - for (i = 0; i < vol_state->source->stream.size / sizeof(int16_t); i++) { + for (i = 0; i < vol_state->sources[0]->stream.size / sizeof(int16_t); i++) { val = (INT16_MIN + (i >> 1)) * sign; val = (val > INT16_MAX) ? INT16_MAX : val; src[i] = (int16_t)val; @@ -199,14 +143,14 @@ static void verify_s16_to_s16(struct processing_module *mod, struct comp_buffer #endif /* CONFIG_FORMAT_S16LE */ #if CONFIG_FORMAT_S24LE -static void fill_source_s24(struct vol_test_state *vol_state) +static void fill_source_s24(struct processing_module_test_data *vol_state) { int64_t val; - int32_t *src = (int32_t *)vol_state->source->stream.r_ptr; + int32_t *src = (int32_t *)vol_state->sources[0]->stream.r_ptr; int i; int sign = 1; - for (i = 0; i < vol_state->source->stream.size / sizeof(int32_t); i++) { + for (i = 0; i < vol_state->sources[0]->stream.size / sizeof(int32_t); i++) { val = (INT24_MIN + (i >> 1)) * sign; val = (val > INT24_MAX) ? INT24_MAX : val; src[i] = (int32_t)val; @@ -256,14 +200,14 @@ static void verify_s24_to_s24_s32(struct processing_module *mod, #endif /* CONFIG_FORMAT_S24LE */ #if CONFIG_FORMAT_S32LE -static void fill_source_s32(struct vol_test_state *vol_state) +static void fill_source_s32(struct processing_module_test_data *vol_state) { int64_t val; - int32_t *src = (int32_t *)vol_state->source->stream.r_ptr; + int32_t *src = (int32_t *)vol_state->sources[0]->stream.r_ptr; int i; int sign = 1; - for (i = 0; i < vol_state->source->stream.size / sizeof(int32_t); i++) { + for (i = 0; i < vol_state->sources[0]->stream.size / sizeof(int32_t); i++) { val = (INT32_MIN + (i >> 1)) * sign; val = (val > INT32_MAX) ? INT32_MAX : val; src[i] = (int32_t)val; @@ -314,11 +258,11 @@ static void verify_s32_to_s24_s32(struct processing_module *mod, static void test_audio_vol(void **state) { - struct vol_test_state *vol_state = *state; + struct processing_module_test_data *vol_state = *state; struct processing_module *mod = vol_state->mod; struct vol_data *cd = module_get_private_data(mod); - switch (vol_state->sink->stream.frame_fmt) { + switch (vol_state->sinks[0]->stream.frame_fmt) { case SOF_IPC_FRAME_S16_LE: fill_source_s16(vol_state); break; @@ -334,50 +278,49 @@ static void test_audio_vol(void **state) break; } - vol_state->input->consumed = 0; - vol_state->output->size = 0; + vol_state->input_buffers[0]->consumed = 0; + vol_state->output_buffers[0]->size = 0; - cd->scale_vol(mod, vol_state->input, vol_state->output, mod->dev->frames); + cd->scale_vol(mod, vol_state->input_buffers[0], vol_state->output_buffers[0], + mod->dev->frames); - vol_state->verify(mod, vol_state->sink, vol_state->source); + vol_state->verify(mod, vol_state->sinks[0], vol_state->sources[0]); } -static struct vol_test_parameters parameters[] = { +static struct processing_module_test_parameters test_parameters[] = { #if CONFIG_FORMAT_S16LE - { VOL_MAX, 2, 48, 1, SOF_IPC_FRAME_S16_LE, - SOF_IPC_FRAME_S16_LE, verify_s16_to_s16 }, /* 1 */ - { VOL_ZERO_DB, 2, 48, 1, SOF_IPC_FRAME_S16_LE, - SOF_IPC_FRAME_S16_LE, verify_s16_to_s16 }, /* 2 */ - { VOL_MINUS_80DB, 2, 48, 1, SOF_IPC_FRAME_S16_LE, - SOF_IPC_FRAME_S16_LE, verify_s16_to_s16 }, /* 3 */ + { 2, 48, 1, SOF_IPC_FRAME_S16_LE, SOF_IPC_FRAME_S16_LE, verify_s16_to_s16 }, #endif /* CONFIG_FORMAT_S16LE */ #if CONFIG_FORMAT_S24LE - { VOL_MAX, 2, 48, 1, SOF_IPC_FRAME_S24_4LE, - SOF_IPC_FRAME_S24_4LE, verify_s24_to_s24_s32 }, /* 4 */ - { VOL_ZERO_DB, 2, 48, 1, SOF_IPC_FRAME_S24_4LE, - SOF_IPC_FRAME_S24_4LE, verify_s24_to_s24_s32 }, /* 5 */ - { VOL_MINUS_80DB, 2, 48, 1, SOF_IPC_FRAME_S24_4LE, - SOF_IPC_FRAME_S24_4LE, verify_s24_to_s24_s32 }, /* 6 */ + { 2, 48, 1, SOF_IPC_FRAME_S24_4LE, + SOF_IPC_FRAME_S24_4LE, verify_s24_to_s24_s32 }, #endif /* CONFIG_FORMAT_S24LE */ #if CONFIG_FORMAT_S32LE - { VOL_MAX, 2, 48, 1, SOF_IPC_FRAME_S32_LE, - SOF_IPC_FRAME_S32_LE, verify_s32_to_s24_s32 }, /* 7 */ - { VOL_ZERO_DB, 2, 48, 1, SOF_IPC_FRAME_S32_LE, - SOF_IPC_FRAME_S32_LE, verify_s32_to_s24_s32 }, /* 8 */ - { VOL_MINUS_80DB, 2, 48, 1, SOF_IPC_FRAME_S32_LE, - SOF_IPC_FRAME_S32_LE, verify_s32_to_s24_s32 }, /* 9 */ + { 2, 48, 1, SOF_IPC_FRAME_S32_LE, SOF_IPC_FRAME_S32_LE, verify_s32_to_s24_s32 }, #endif /* CONFIG_FORMAT_S32LE */ }; int main(void) { - int i; + struct vol_test_parameters *parameters; + uint32_t volume_values[] = {VOL_MAX, VOL_ZERO_DB, VOL_MINUS_80DB}; + int num_tests = ARRAY_SIZE(test_parameters) * ARRAY_SIZE(volume_values); + int i, j; + + parameters = test_calloc(num_tests, sizeof(struct vol_test_parameters)); + for (i = 0; i < ARRAY_SIZE(test_parameters); i++) { + for (j = 0; j < ARRAY_SIZE(volume_values); j++) { + parameters[i * ARRAY_SIZE(test_parameters) + j].volume = volume_values[j]; + parameters[i * ARRAY_SIZE(test_parameters) + j].module_parameters = + test_parameters[i]; + } + } - struct CMUnitTest tests[ARRAY_SIZE(parameters)]; + struct CMUnitTest tests[num_tests]; - for (i = 0; i < ARRAY_SIZE(parameters); i++) { + for (i = 0; i < num_tests; i++) { tests[i].name = "test_audio_vol"; tests[i].test_func = test_audio_vol; tests[i].setup_func = setup; From e38b61fa88c15a067a7f0505a0acdb2cf1803c06 Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Thu, 15 Sep 2022 16:41:29 -0400 Subject: [PATCH 07/39] zephyr: both BDW and BYT are not supported in zephyr Both Broadwell and Baytrail are not supported in zephyr and those Kconfigs are not defined anywhere, neither in SOF nor in zephyr. Signed-off-by: Anas Nashif --- zephyr/CMakeLists.txt | 42 --------------------------------- zephyr/include/rtos/interrupt.h | 4 +--- 2 files changed, 1 insertion(+), 45 deletions(-) diff --git a/zephyr/CMakeLists.txt b/zephyr/CMakeLists.txt index 1367ca0d8cd0..654e07d471b0 100644 --- a/zephyr/CMakeLists.txt +++ b/zephyr/CMakeLists.txt @@ -105,48 +105,6 @@ zephyr_include_directories( # SOC level sources # Files that are commented may not be needed. -# Intel BYT, CHT, BSW platforms -if (CONFIG_SOC_SERIES_INTEL_ADSP_BAYTRAIL) - - # Driver sources - zephyr_library_sources( - ${SOF_DRIVERS_PATH}/intel/baytrail/ipc.c - ${SOF_DRIVERS_PATH}/intel/baytrail/ssp.c - ${SOF_DRIVERS_PATH}/intel/pmc-ipc.c - ) - - # Platform sources - zephyr_library_sources( - ${SOF_PLATFORM_PATH}/baytrail/platform.c - ${SOF_PLATFORM_PATH}/baytrail/lib/dai.c - ${SOF_PLATFORM_PATH}/baytrail/lib/clk.c - ${SOF_PLATFORM_PATH}/baytrail/lib/dma.c - ${SOF_SRC_PATH}/schedule/dma_multi_chan_domain.c - ) - - # SOF core infrastructure - runs on top of Zephyr - zephyr_library_sources( - ${SOF_SRC_PATH}/schedule/ll_schedule.c - ) - - set(PLATFORM "baytrail") -endif() - -# Intel HSW, BDW platforms -if (CONFIG_SOC_SERIES_INTEL_ADSP_BROADWELL) - zephyr_library_sources( - ${SOF_DRIVERS_PATH}/intel/haswell/ipc.c - ${SOF_DRIVERS_PATH}/intel/haswell/ssp.c - ) - - # SOF core infrastructure - runs on top of Zephyr - zephyr_library_sources( - ${SOF_SRC_PATH}/schedule/ll_schedule.c - ) - - set(PLATFORM "haswell") -endif() - # Intel APL, KBL, SKL CAVS 1.5 platforms if (CONFIG_SOC_SERIES_INTEL_CAVS_V15) diff --git a/zephyr/include/rtos/interrupt.h b/zephyr/include/rtos/interrupt.h index aadeaaf5d81b..b8c0c2a08e7c 100644 --- a/zephyr/include/rtos/interrupt.h +++ b/zephyr/include/rtos/interrupt.h @@ -48,9 +48,7 @@ static inline void interrupt_unregister(uint32_t irq, const void *arg) */ static inline int interrupt_get_irq(unsigned int irq, const char *cascade) { -#if CONFIG_SOC_SERIES_INTEL_ADSP_BAYTRAIL ||\ - CONFIG_SOC_SERIES_INTEL_ADSP_BROADWELL || \ - CONFIG_LIBRARY +#ifdef CONFIG_LIBRARY return irq; #else if (cascade == irq_name_level2) From 46eb1c53028098a8240eb7de2b00cbb4b6206ee4 Mon Sep 17 00:00:00 2001 From: Balakishorepati Date: Fri, 16 Sep 2022 12:22:41 +0530 Subject: [PATCH 08/39] module_adapter:Fix dangling pointer issue in module reset During module_reset and module_free Calls, pointers are not getting reset to NULL which causes dangling pointer exceptions. Initialize pointers to NULL after deallocating the memory. Signed-off-by: Balakishorepati --- src/audio/module_adapter/module/generic.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/audio/module_adapter/module/generic.c b/src/audio/module_adapter/module/generic.c index 4b9bbf7bf28c..fec8849a4fe0 100644 --- a/src/audio/module_adapter/module/generic.c +++ b/src/audio/module_adapter/module/generic.c @@ -279,6 +279,7 @@ int module_reset(struct processing_module *mod) md->cfg.avail = false; md->cfg.size = 0; rfree(md->cfg.data); + md->cfg.data = NULL; /* * reset the state to allow the module's prepare callback to be invoked again for the @@ -318,9 +319,11 @@ int module_free(struct processing_module *mod) md->cfg.avail = false; md->cfg.size = 0; rfree(md->cfg.data); - if (md->runtime_params) + md->cfg.data = NULL; + if (md->runtime_params) { rfree(md->runtime_params); - + md->runtime_params = NULL; + } md->state = MODULE_DISABLED; return ret; From 82adca620b17bd6b958620d755bca3594995fe00 Mon Sep 17 00:00:00 2001 From: Chao Song Date: Fri, 16 Sep 2022 10:39:59 +0800 Subject: [PATCH 09/39] module_adapter: add helper for module config fragment position This patch adds a helper to convert first_block/last_block indicator to module_cfg_fragment_position enum, which is more efficient than if-else test. Signed-off-by: Chao Song --- src/audio/module_adapter/module_adapter.c | 12 +----------- .../audio/module_adapter/module/module_interface.h | 7 +++++++ 2 files changed, 8 insertions(+), 11 deletions(-) diff --git a/src/audio/module_adapter/module_adapter.c b/src/audio/module_adapter/module_adapter.c index 451ea38728c4..c6c1e588ce22 100644 --- a/src/audio/module_adapter/module_adapter.c +++ b/src/audio/module_adapter/module_adapter.c @@ -917,17 +917,7 @@ int module_set_large_config(struct comp_dev *dev, uint32_t param_id, bool first_ size_t fragment_size; /* set fragment position */ - if (first_block) { - if (last_block) - pos = MODULE_CFG_FRAGMENT_SINGLE; - else - pos = MODULE_CFG_FRAGMENT_FIRST; - } else { - if (!last_block) - pos = MODULE_CFG_FRAGMENT_MIDDLE; - else - pos = MODULE_CFG_FRAGMENT_LAST; - } + pos = first_last_block_to_frag_pos(first_block, last_block); switch (pos) { case MODULE_CFG_FRAGMENT_SINGLE: diff --git a/src/include/sof/audio/module_adapter/module/module_interface.h b/src/include/sof/audio/module_adapter/module/module_interface.h index acb99213c1c0..842994a8c76f 100644 --- a/src/include/sof/audio/module_adapter/module/module_interface.h +++ b/src/include/sof/audio/module_adapter/module/module_interface.h @@ -143,4 +143,11 @@ struct module_interface { int (*free)(struct processing_module *mod); }; +/* Convert first_block/last_block indicator to fragment position */ +static inline enum module_cfg_fragment_position +first_last_block_to_frag_pos(bool first_block, bool last_block) +{ + return (last_block << 1) | first_block; +} + #endif /* __SOF_MODULE_INTERFACE__ */ From 09995d428a65061faaf906cf97f9bdee147b57a2 Mon Sep 17 00:00:00 2001 From: Balakishorepati Date: Thu, 15 Sep 2022 11:13:41 +0530 Subject: [PATCH 10/39] drivers:amd: Fix aclk issue in standalone dmic usecase Change aclk to max or minimum during playback,capture usecases start and stop based on dmic status. Signed-off-by: Balakishorepati --- src/drivers/amd/rembrandt/acp_bt_dma.c | 10 ++++++++-- src/drivers/amd/rembrandt/acp_dmic_dma.c | 21 +++++++++++++++++++++ src/drivers/amd/rembrandt/acp_hs_dma.c | 20 +++++++++++++------- src/drivers/amd/rembrandt/acp_sp_dma.c | 20 +++++++++++++------- src/drivers/amd/rembrandt/interrupt.c | 3 +-- src/drivers/amd/renoir/acp_bt_dma.c | 9 +++++++-- src/drivers/amd/renoir/acp_dmic_dma.c | 23 +++++++++++++++++++++++ src/drivers/amd/renoir/acp_sp_dma.c | 10 ++++++++-- src/drivers/amd/renoir/interrupt.c | 3 +-- 9 files changed, 95 insertions(+), 24 deletions(-) diff --git a/src/drivers/amd/rembrandt/acp_bt_dma.c b/src/drivers/amd/rembrandt/acp_bt_dma.c index 3dba72b95f23..464728748e40 100644 --- a/src/drivers/amd/rembrandt/acp_bt_dma.c +++ b/src/drivers/amd/rembrandt/acp_bt_dma.c @@ -94,11 +94,13 @@ static int acp_dai_bt_dma_start(struct dma_chan_data *channel) acp_bttdm_ier_t bt_ier; acp_bttdm_iter_t bt_tdm_iter; acp_bttdm_irer_t bt_tdm_irer; + uint32_t acp_pdm_en; bt_tdm_iter = (acp_bttdm_iter_t)io_reg_read((PU_REGISTER_BASE + ACP_BTTDM_ITER)); bt_tdm_irer = (acp_bttdm_irer_t)io_reg_read((PU_REGISTER_BASE + ACP_BTTDM_IRER)); + acp_pdm_en = (uint32_t)io_reg_read(PU_REGISTER_BASE + ACP_WOV_PDM_ENABLE); - if (!bt_tdm_iter.bits.bttdm_txen && !bt_tdm_irer.bits.bttdm_rx_en) + if (!bt_tdm_iter.bits.bttdm_txen && !bt_tdm_irer.bits.bttdm_rx_en && !acp_pdm_en) /* Request SMU to set aclk to 600 Mhz */ acp_change_clock_notify(600000000); @@ -149,6 +151,7 @@ static int acp_dai_bt_dma_stop(struct dma_chan_data *channel) { acp_bttdm_iter_t bt_tdm_iter; acp_bttdm_irer_t bt_tdm_irer; + uint32_t acp_pdm_en; switch (channel->status) { case COMP_STATE_READY: @@ -176,10 +179,13 @@ static int acp_dai_bt_dma_stop(struct dma_chan_data *channel) bt_tdm_iter = (acp_bttdm_iter_t)io_reg_read(PU_REGISTER_BASE + ACP_BTTDM_ITER); bt_tdm_irer = (acp_bttdm_irer_t)io_reg_read(PU_REGISTER_BASE + ACP_BTTDM_IRER); + acp_pdm_en = (uint32_t)io_reg_read(PU_REGISTER_BASE + ACP_WOV_PDM_ENABLE); + if (!bt_tdm_iter.bits.bttdm_txen && !bt_tdm_irer.bits.bttdm_rx_en) { io_reg_write((PU_REGISTER_BASE + ACP_BTTDM_IER), BT_IER_DISABLE); /* Request SMU to scale down aclk to minimum clk */ - acp_change_clock_notify(0); + if (!acp_pdm_en) + acp_change_clock_notify(0); } return 0; diff --git a/src/drivers/amd/rembrandt/acp_dmic_dma.c b/src/drivers/amd/rembrandt/acp_dmic_dma.c index 8243cf8f5f0d..0377d17cd011 100644 --- a/src/drivers/amd/rembrandt/acp_dmic_dma.c +++ b/src/drivers/amd/rembrandt/acp_dmic_dma.c @@ -82,9 +82,20 @@ static int acp_dmic_dma_start(struct dma_chan_data *channel) acp_wov_pdm_decimation_factor_t deci_fctr; acp_wov_misc_ctrl_t wov_misc_ctrl; acp_wov_pdm_dma_enable_t pdm_dma_enable; + acp_hstdm_iter_t hs_iter; + acp_hstdm_irer_t hs_irer; + uint32_t acp_pdm_en; struct timer *timer = timer_get(); uint64_t deadline = platform_timer_get(timer) + clock_ms_to_ticks(PLATFORM_DEFAULT_CLOCK, 1) * 500 / 1000; + + hs_iter = (acp_hstdm_iter_t)io_reg_read((PU_REGISTER_BASE + ACP_HSTDM_ITER)); + hs_irer = (acp_hstdm_irer_t)io_reg_read((PU_REGISTER_BASE + ACP_HSTDM_IRER)); + acp_pdm_en = (uint32_t)io_reg_read(PU_REGISTER_BASE + ACP_WOV_PDM_ENABLE); + + if (!hs_iter.bits.hstdm_txen && !hs_irer.bits.hstdm_rx_en && !acp_pdm_en) + /* Request SMU to set aclk to 600 Mhz */ + acp_change_clock_notify(600000000); channel->status = COMP_STATE_ACTIVE; if (channel->direction == DMA_DIR_DEV_TO_MEM) { /* Channel for DMIC */ @@ -140,6 +151,9 @@ static int acp_dmic_dma_pause(struct dma_chan_data *channel) static int acp_dmic_dma_stop(struct dma_chan_data *channel) { acp_wov_pdm_dma_enable_t pdm_dma_enable; + acp_hstdm_iter_t hs_iter; + acp_hstdm_irer_t hs_irer; + uint32_t acp_pdm_en; struct timer *timer = timer_get(); uint64_t deadline = platform_timer_get(timer) + clock_ms_to_ticks(PLATFORM_DEFAULT_CLOCK, 1) * 500 / 1000; @@ -175,6 +189,13 @@ static int acp_dmic_dma_stop(struct dma_chan_data *channel) io_reg_write(PU_REGISTER_BASE + ACP_WOV_PDM_ENABLE, 0); /* Clear PDM FIFO */ io_reg_write(PU_REGISTER_BASE + ACP_WOV_PDM_FIFO_FLUSH, 1); + hs_iter = (acp_hstdm_iter_t)io_reg_read((PU_REGISTER_BASE + ACP_HSTDM_ITER)); + hs_irer = (acp_hstdm_irer_t)io_reg_read((PU_REGISTER_BASE + ACP_HSTDM_IRER)); + acp_pdm_en = (uint32_t)io_reg_read(PU_REGISTER_BASE + ACP_WOV_PDM_ENABLE); + + if (!hs_iter.bits.hstdm_txen && !hs_irer.bits.hstdm_rx_en && !acp_pdm_en) + /* Request SMU to set aclk to minimum aclk */ + acp_change_clock_notify(0); return 0; } diff --git a/src/drivers/amd/rembrandt/acp_hs_dma.c b/src/drivers/amd/rembrandt/acp_hs_dma.c index a902f53dd907..57c9561913b1 100644 --- a/src/drivers/amd/rembrandt/acp_hs_dma.c +++ b/src/drivers/amd/rembrandt/acp_hs_dma.c @@ -85,14 +85,16 @@ static void acp_dai_hs_dma_channel_put(struct dma_chan_data *channel) static int acp_dai_hs_dma_start(struct dma_chan_data *channel) { - acp_hstdm_ier_t hs_ier; - acp_hstdm_iter_t hs_iter; - acp_hstdm_irer_t hs_irer; + acp_hstdm_ier_t hs_ier; + acp_hstdm_iter_t hs_iter; + acp_hstdm_irer_t hs_irer; + uint32_t acp_pdm_en; hs_iter = (acp_hstdm_iter_t)io_reg_read((PU_REGISTER_BASE + ACP_HSTDM_ITER)); hs_irer = (acp_hstdm_irer_t)io_reg_read((PU_REGISTER_BASE + ACP_HSTDM_IRER)); + acp_pdm_en = (uint32_t)io_reg_read(PU_REGISTER_BASE + ACP_WOV_PDM_ENABLE); - if (!hs_iter.bits.hstdm_txen && !hs_irer.bits.hstdm_rx_en) + if (!hs_iter.bits.hstdm_txen && !hs_irer.bits.hstdm_rx_en && !acp_pdm_en) /* Request SMU to set aclk to 600 Mhz */ acp_change_clock_notify(600000000); @@ -141,8 +143,9 @@ static int acp_dai_hs_dma_pause(struct dma_chan_data *channel) static int acp_dai_hs_dma_stop(struct dma_chan_data *channel) { - acp_hstdm_irer_t hs_irer; - acp_hstdm_iter_t hs_iter; + acp_hstdm_irer_t hs_irer; + acp_hstdm_iter_t hs_iter; + uint32_t acp_pdm_en; switch (channel->status) { case COMP_STATE_READY: @@ -170,10 +173,13 @@ static int acp_dai_hs_dma_stop(struct dma_chan_data *channel) } hs_iter = (acp_hstdm_iter_t)io_reg_read((PU_REGISTER_BASE + ACP_HSTDM_ITER)); hs_irer = (acp_hstdm_irer_t)io_reg_read((PU_REGISTER_BASE + ACP_HSTDM_IRER)); + acp_pdm_en = (uint32_t)io_reg_read(PU_REGISTER_BASE + ACP_WOV_PDM_ENABLE); + if (!hs_iter.bits.hstdm_txen && !hs_irer.bits.hstdm_rx_en) { io_reg_write((PU_REGISTER_BASE + ACP_HSTDM_IER), HS_IER_DISABLE); /* Request SMU to scale down aclk to minimum clk */ - acp_change_clock_notify(0); + if (!acp_pdm_en) + acp_change_clock_notify(0); } return 0; } diff --git a/src/drivers/amd/rembrandt/acp_sp_dma.c b/src/drivers/amd/rembrandt/acp_sp_dma.c index fad812425e9f..77acc6000d65 100644 --- a/src/drivers/amd/rembrandt/acp_sp_dma.c +++ b/src/drivers/amd/rembrandt/acp_sp_dma.c @@ -86,14 +86,16 @@ static void acp_dai_sp_dma_channel_put(struct dma_chan_data *channel) static int acp_dai_sp_dma_start(struct dma_chan_data *channel) { - acp_i2stdm_ier_t sp_ier; - acp_i2stdm_iter_t sp_iter; - acp_i2stdm_irer_t sp_irer; + acp_i2stdm_ier_t sp_ier; + acp_i2stdm_iter_t sp_iter; + acp_i2stdm_irer_t sp_irer; + uint32_t acp_pdm_en; sp_iter = (acp_i2stdm_iter_t)io_reg_read((PU_REGISTER_BASE + ACP_I2STDM_ITER)); sp_irer = (acp_i2stdm_irer_t)io_reg_read((PU_REGISTER_BASE + ACP_I2STDM_IRER)); + acp_pdm_en = (uint32_t)io_reg_read(PU_REGISTER_BASE + ACP_WOV_PDM_ENABLE); - if (!sp_iter.bits.i2stdm_txen && !sp_irer.bits.i2stdm_rx_en) + if (!sp_iter.bits.i2stdm_txen && !sp_irer.bits.i2stdm_rx_en && !acp_pdm_en) /* Request SMU to set aclk to 600 Mhz */ acp_change_clock_notify(600000000); @@ -142,8 +144,9 @@ static int acp_dai_sp_dma_pause(struct dma_chan_data *channel) static int acp_dai_sp_dma_stop(struct dma_chan_data *channel) { - acp_i2stdm_irer_t sp_irer; - acp_i2stdm_iter_t sp_iter; + acp_i2stdm_irer_t sp_irer; + acp_i2stdm_iter_t sp_iter; + uint32_t acp_pdm_en; switch (channel->status) { case COMP_STATE_READY: @@ -170,10 +173,13 @@ static int acp_dai_sp_dma_stop(struct dma_chan_data *channel) } sp_iter = (acp_i2stdm_iter_t)io_reg_read((PU_REGISTER_BASE + ACP_I2STDM_ITER)); sp_irer = (acp_i2stdm_irer_t)io_reg_read((PU_REGISTER_BASE + ACP_I2STDM_IRER)); + acp_pdm_en = (uint32_t)io_reg_read(PU_REGISTER_BASE + ACP_WOV_PDM_ENABLE); + if (!sp_iter.bits.i2stdm_txen && !sp_irer.bits.i2stdm_rx_en) { io_reg_write((PU_REGISTER_BASE + ACP_I2STDM_IER), SP_IER_DISABLE); /* Request SMU to scale down aclk to minimum clk */ - acp_change_clock_notify(0); + if (!acp_pdm_en) + acp_change_clock_notify(0); } return 0; diff --git a/src/drivers/amd/rembrandt/interrupt.c b/src/drivers/amd/rembrandt/interrupt.c index 595197e0b8d6..e226f2632866 100644 --- a/src/drivers/amd/rembrandt/interrupt.c +++ b/src/drivers/amd/rembrandt/interrupt.c @@ -413,8 +413,7 @@ void acp_ack_intr_from_host(void) /* acknowledge the host interrupt */ acp_dsp_sw_intr_stat_t sw_intr_stat; - sw_intr_stat = (acp_dsp_sw_intr_stat_t)io_reg_read(PU_REGISTER_BASE + - ACP_DSP_SW_INTR_STAT); + sw_intr_stat.u32all = 0; sw_intr_stat.bits.host_to_dsp0_intr1_stat = INTERRUPT_ENABLE; io_reg_write((PU_REGISTER_BASE + ACP_DSP_SW_INTR_STAT), sw_intr_stat.u32all); } diff --git a/src/drivers/amd/renoir/acp_bt_dma.c b/src/drivers/amd/renoir/acp_bt_dma.c index 6eace980d8f0..2d4e5fc6bfaa 100644 --- a/src/drivers/amd/renoir/acp_bt_dma.c +++ b/src/drivers/amd/renoir/acp_bt_dma.c @@ -93,11 +93,13 @@ static int acp_dai_bt_dma_start(struct dma_chan_data *channel) acp_bttdm_ier_t bt_ier; acp_bttdm_iter_t bt_tdm_iter; acp_bttdm_irer_t bt_tdm_irer; + uint32_t acp_pdm_en; bt_tdm_iter = (acp_bttdm_iter_t)io_reg_read((PU_REGISTER_BASE + ACP_BTTDM_ITER)); bt_tdm_irer = (acp_bttdm_irer_t)io_reg_read((PU_REGISTER_BASE + ACP_BTTDM_IRER)); + acp_pdm_en = (uint32_t)io_reg_read(PU_REGISTER_BASE + ACP_WOV_PDM_ENABLE); - if (!bt_tdm_iter.bits.bttdm_txen && !bt_tdm_irer.bits.bttdm_rx_en) + if (!bt_tdm_iter.bits.bttdm_txen && !bt_tdm_irer.bits.bttdm_rx_en && !acp_pdm_en) /* Request SMU to set aclk to 600 Mhz */ acp_change_clock_notify(600000000); @@ -148,6 +150,7 @@ static int acp_dai_bt_dma_stop(struct dma_chan_data *channel) { acp_bttdm_iter_t bt_tdm_iter; acp_bttdm_irer_t bt_tdm_irer; + uint32_t acp_pdm_en; switch (channel->status) { case COMP_STATE_READY: @@ -175,10 +178,12 @@ static int acp_dai_bt_dma_stop(struct dma_chan_data *channel) bt_tdm_iter = (acp_bttdm_iter_t)io_reg_read(PU_REGISTER_BASE + ACP_BTTDM_ITER); bt_tdm_irer = (acp_bttdm_irer_t)io_reg_read(PU_REGISTER_BASE + ACP_BTTDM_IRER); + acp_pdm_en = (uint32_t)io_reg_read(PU_REGISTER_BASE + ACP_WOV_PDM_ENABLE); if (!bt_tdm_iter.bits.bttdm_txen && !bt_tdm_irer.bits.bttdm_rx_en) { io_reg_write((PU_REGISTER_BASE + ACP_BTTDM_IER), BT_IER_DISABLE); /* Request SMU to scale down aclk to minimum clk */ - acp_change_clock_notify(0); + if (!acp_pdm_en) + acp_change_clock_notify(0); } return 0; diff --git a/src/drivers/amd/renoir/acp_dmic_dma.c b/src/drivers/amd/renoir/acp_dmic_dma.c index 3e0e04819bc8..43dbfe3dd108 100644 --- a/src/drivers/amd/renoir/acp_dmic_dma.c +++ b/src/drivers/amd/renoir/acp_dmic_dma.c @@ -82,9 +82,21 @@ static int acp_dmic_dma_start(struct dma_chan_data *channel) acp_wov_pdm_decimation_factor_t deci_fctr; acp_wov_misc_ctrl_t wov_misc_ctrl; acp_wov_pdm_dma_enable_t pdm_dma_enable; + acp_i2stdm_iter_t sp_iter; + acp_i2stdm_irer_t sp_irer; + uint32_t acp_pdm_en; struct timer *timer = timer_get(); uint64_t deadline = platform_timer_get(timer) + clock_ms_to_ticks(PLATFORM_DEFAULT_CLOCK, 1) * 500 / 1000; + + sp_iter = (acp_i2stdm_iter_t)io_reg_read((PU_REGISTER_BASE + ACP_I2STDM_ITER)); + sp_irer = (acp_i2stdm_irer_t)io_reg_read((PU_REGISTER_BASE + ACP_I2STDM_IRER)); + acp_pdm_en = (uint32_t)io_reg_read(PU_REGISTER_BASE + ACP_WOV_PDM_ENABLE); + + if (!sp_iter.bits.i2stdm_txen && !sp_irer.bits.i2stdm_rx_en && !acp_pdm_en) + /* Request SMU to set aclk to 600 Mhz */ + acp_change_clock_notify(600000000); + channel->status = COMP_STATE_ACTIVE; if (channel->direction == DMA_DIR_DEV_TO_MEM) { /* Channel for DMIC */ @@ -140,6 +152,9 @@ static int acp_dmic_dma_pause(struct dma_chan_data *channel) static int acp_dmic_dma_stop(struct dma_chan_data *channel) { acp_wov_pdm_dma_enable_t pdm_dma_enable; + acp_i2stdm_iter_t sp_iter; + acp_i2stdm_irer_t sp_irer; + uint32_t acp_pdm_en; struct timer *timer = timer_get(); uint64_t deadline = platform_timer_get(timer) + clock_ms_to_ticks(PLATFORM_DEFAULT_CLOCK, 1) * 500 / 1000; @@ -175,6 +190,14 @@ static int acp_dmic_dma_stop(struct dma_chan_data *channel) io_reg_write(PU_REGISTER_BASE + ACP_WOV_PDM_ENABLE, 0); /* Clear PDM FIFO */ io_reg_write(PU_REGISTER_BASE + ACP_WOV_PDM_FIFO_FLUSH, 1); + sp_iter = (acp_i2stdm_iter_t)io_reg_read((PU_REGISTER_BASE + ACP_I2STDM_ITER)); + sp_irer = (acp_i2stdm_irer_t)io_reg_read((PU_REGISTER_BASE + ACP_I2STDM_IRER)); + acp_pdm_en = (uint32_t)io_reg_read(PU_REGISTER_BASE + ACP_WOV_PDM_ENABLE); + + if (!sp_iter.bits.i2stdm_txen && !sp_irer.bits.i2stdm_rx_en && !acp_pdm_en) + /* Request SMU to set aclk to minimum aclk */ + acp_change_clock_notify(0); + return 0; } diff --git a/src/drivers/amd/renoir/acp_sp_dma.c b/src/drivers/amd/renoir/acp_sp_dma.c index fbc499ca12fd..b8f391278951 100644 --- a/src/drivers/amd/renoir/acp_sp_dma.c +++ b/src/drivers/amd/renoir/acp_sp_dma.c @@ -87,11 +87,13 @@ static int acp_dai_sp_dma_start(struct dma_chan_data *channel) acp_i2stdm_ier_t sp_ier; acp_i2stdm_iter_t sp_iter; acp_i2stdm_irer_t sp_irer; + uint32_t acp_pdm_en; sp_iter = (acp_i2stdm_iter_t)io_reg_read((PU_REGISTER_BASE + ACP_I2STDM_ITER)); sp_irer = (acp_i2stdm_irer_t)io_reg_read((PU_REGISTER_BASE + ACP_I2STDM_IRER)); + acp_pdm_en = (uint32_t)io_reg_read(PU_REGISTER_BASE + ACP_WOV_PDM_ENABLE); - if (!sp_iter.bits.i2stdm_txen && !sp_irer.bits.i2stdm_rx_en) + if (!sp_iter.bits.i2stdm_txen && !sp_irer.bits.i2stdm_rx_en && !acp_pdm_en) /* Request SMU to set aclk to 600 Mhz */ acp_change_clock_notify(600000000); @@ -142,6 +144,7 @@ static int acp_dai_sp_dma_stop(struct dma_chan_data *channel) { acp_i2stdm_irer_t sp_irer; acp_i2stdm_iter_t sp_iter; + uint32_t acp_pdm_en; switch (channel->status) { case COMP_STATE_READY: @@ -168,10 +171,13 @@ static int acp_dai_sp_dma_stop(struct dma_chan_data *channel) } sp_iter = (acp_i2stdm_iter_t)io_reg_read((PU_REGISTER_BASE + ACP_I2STDM_ITER)); sp_irer = (acp_i2stdm_irer_t)io_reg_read((PU_REGISTER_BASE + ACP_I2STDM_IRER)); + acp_pdm_en = (uint32_t)io_reg_read(PU_REGISTER_BASE + ACP_WOV_PDM_ENABLE); + if (!sp_iter.bits.i2stdm_txen && !sp_irer.bits.i2stdm_rx_en) { io_reg_write((PU_REGISTER_BASE + ACP_I2STDM_IER), SP_IER_DISABLE); /* Request SMU to scale down aclk to minimum clk */ - acp_change_clock_notify(0); + if (!acp_pdm_en) + acp_change_clock_notify(0); } return 0; diff --git a/src/drivers/amd/renoir/interrupt.c b/src/drivers/amd/renoir/interrupt.c index e3c127d4ca22..fcede00a6f14 100644 --- a/src/drivers/amd/renoir/interrupt.c +++ b/src/drivers/amd/renoir/interrupt.c @@ -376,8 +376,7 @@ void acp_ack_intr_from_host(void) /* acknowledge the host interrupt */ acp_dsp_sw_intr_stat_t sw_intr_stat; - sw_intr_stat = (acp_dsp_sw_intr_stat_t)io_reg_read(PU_REGISTER_BASE + - ACP_DSP_SW_INTR_STAT); + sw_intr_stat.u32all = 0; sw_intr_stat.bits.host_to_dsp0_intr1_stat = INTERRUPT_ENABLE; io_reg_write((PU_REGISTER_BASE + ACP_DSP_SW_INTR_STAT), sw_intr_stat.u32all); } From db668b6e4dba9c8bd8fc220b3574f4cde10e88ab Mon Sep 17 00:00:00 2001 From: Adrian Warecki Date: Tue, 6 Sep 2022 15:13:39 +0200 Subject: [PATCH 11/39] platform: mtl: Add meteorlake plaftom Added base files of meteorlake plaftom: Board configuration CPU, clock and memory configuration Platform bootstrap code IPC driver wrapper for Zephyr IPC API for ACE1.5 platforms. Signed-off-by: Andrey Borisovich Signed-off-by: Marcin Szkudlinski Signed-off-by: Adrian Warecki Signed-off-by: Konrad Leszczynski Signed-off-by: Anas Nashif Signed-off-by: Tomasz Leman Signed-off-by: Rafal Redzimski Signed-off-by: Adrian Bonislawski Signed-off-by: Serhiy Katsyuba --- app/boards/intel_adsp_ace15_mtpm.conf | 17 ++ app/overlays/mtl/fpga_overlay.conf | 2 + src/drivers/intel/ace/ipc.c | 173 ++++++++++++++++++ src/platform/intel/ace/include/ace/lib/clk.h | 56 ++++++ src/platform/intel/ace/include/ace/lib/cpu.h | 25 +++ .../intel/ace/include/ace/lib/memory.h | 78 ++++++++ src/platform/intel/ace/include/ace/version.h | 20 ++ src/platform/intel/ace/platform.c | 100 ++++++++++ .../meteorlake/include/platform/lib/clk.h | 41 +++++ .../meteorlake/include/platform/lib/cpu.h | 24 +++ .../meteorlake/include/platform/lib/memory.h | 59 ++++++ .../meteorlake/include/platform/lib/shim.h | 58 ++++++ .../meteorlake/include/platform/platform.h | 46 +++++ src/platform/meteorlake/lib/clk.c | 35 ++++ zephyr/include/rtos/interrupt.h | 2 +- 15 files changed, 735 insertions(+), 1 deletion(-) create mode 100644 app/boards/intel_adsp_ace15_mtpm.conf create mode 100644 app/overlays/mtl/fpga_overlay.conf create mode 100644 src/drivers/intel/ace/ipc.c create mode 100644 src/platform/intel/ace/include/ace/lib/clk.h create mode 100644 src/platform/intel/ace/include/ace/lib/cpu.h create mode 100644 src/platform/intel/ace/include/ace/lib/memory.h create mode 100644 src/platform/intel/ace/include/ace/version.h create mode 100644 src/platform/intel/ace/platform.c create mode 100644 src/platform/meteorlake/include/platform/lib/clk.h create mode 100644 src/platform/meteorlake/include/platform/lib/cpu.h create mode 100644 src/platform/meteorlake/include/platform/lib/memory.h create mode 100644 src/platform/meteorlake/include/platform/lib/shim.h create mode 100644 src/platform/meteorlake/include/platform/platform.h create mode 100644 src/platform/meteorlake/lib/clk.c diff --git a/app/boards/intel_adsp_ace15_mtpm.conf b/app/boards/intel_adsp_ace15_mtpm.conf new file mode 100644 index 000000000000..57c0769b6038 --- /dev/null +++ b/app/boards/intel_adsp_ace15_mtpm.conf @@ -0,0 +1,17 @@ +CONFIG_METEORLAKE=y +CONFIG_INTEL_DMIC=n +CONFIG_INTEL_DMIC_NHLT=n +CONFIG_INTEL_SSP=n +CONFIG_INTEL_ALH=n +CONFIG_RIMAGE_SIGNING_SCHEMA="mtl" +CONFIG_IPC_MAJOR_4=y +CONFIG_INTEL_ADSP_IPC=y +CONFIG_DW_ICTL_ACE_V1X=y +CONFIG_COMP_SRC=y +CONFIG_INTEL_ADSP_TIMER=y +CONFIG_DMA=y +CONFIG_FORMAT_CONVERT_HIFI3=n +CONFIG_SYS_CLOCK_TICKS_PER_SEC=12000 +CONFIG_ZEPHYR_NATIVE_DRIVERS=y +CONFIG_COMP_KPB=n +CONFIG_TRACE=n diff --git a/app/overlays/mtl/fpga_overlay.conf b/app/overlays/mtl/fpga_overlay.conf new file mode 100644 index 000000000000..c3e768d1aacc --- /dev/null +++ b/app/overlays/mtl/fpga_overlay.conf @@ -0,0 +1,2 @@ +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=19200000 +CONFIG_DMIC_HW_IOCLK=19200000 diff --git a/src/drivers/intel/ace/ipc.c b/src/drivers/intel/ace/ipc.c new file mode 100644 index 000000000000..304151b790a3 --- /dev/null +++ b/src/drivers/intel/ace/ipc.c @@ -0,0 +1,173 @@ +// SPDX-License-Identifier: BSD-3-Clause +// +// Copyright(c) 2022 Intel Corporation. All rights reserved. +// +// Author: Liam Girdwood +// Keyon Jie +// Rander Wang +// Serhiy Katsyuba +// Andrey Borisovich +// Adrian Warecki + +#include + +#include + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +/* 8fa1d42f-bc6f-464b-867f-547af08834da */ +DECLARE_SOF_UUID("ipc-task", ipc_task_uuid, 0x8fa1d42f, 0xbc6f, 0x464b, + 0x86, 0x7f, 0x54, 0x7a, 0xf0, 0x88, 0x34, 0xda); + +/** + * @brief Private data for IPC. + * + * Written in interrupt context to service incoming IPC message using registered + * cAVS IPC Message Handler Callback (message_handler function). + * Filled with content of TDR and TDD registers. + * When IPC message is read fills ipc_cmd_hdr. + */ +static uint32_t g_last_data, g_last_ext_data; + +/** + * @brief cAVS IPC Message Handler Callback function. + * + * See @ref (*intel_adsp_ipc_handler_t) for function signature description. + * @return false so BUSY on the other side will not be cleared immediately but + * will remain set until message would have been processed by scheduled task, i.e. + * until ipc_platform_complete_cmd() call. + */ +static bool message_handler(const struct device *dev, void *arg, uint32_t data, uint32_t ext_data) +{ + struct ipc *ipc = (struct ipc *)arg; + + k_spinlock_key_t key; + + key = k_spin_lock(&ipc->lock); + + g_last_data = data; + g_last_ext_data = ext_data; + +#if CONFIG_DEBUG_IPC_COUNTERS + increment_ipc_received_counter(); +#endif + + ipc_schedule_process(ipc); + + k_spin_unlock(&ipc->lock, key); + + return false; +} + +#if CONFIG_DEBUG_IPC_COUNTERS + +static inline void increment_ipc_received_counter(void) +{ + static uint32_t ipc_received_counter; + + mailbox_sw_reg_write(SRAM_REG_FW_IPC_RECEIVED_COUNT, + ipc_received_counter++); +} + +static inline void increment_ipc_processed_counter(void) +{ + static uint32_t ipc_processed_counter; + uint32_t *uncache_counter = cache_to_uncache(&ipc_processed_counter); + + mailbox_sw_reg_write(SRAM_REG_FW_IPC_PROCESSED_COUNT, + (*uncache_counter)++); +} + +#endif /* CONFIG_DEBUG_IPC_COUNTERS */ + +int ipc_platform_compact_read_msg(struct ipc_cmd_hdr *hdr, int words) +{ + uint32_t *chdr = (uint32_t *)hdr; + + /* compact messages are 2 words on CAVS 1.8 onwards */ + if (words != 2) + return 0; + + chdr[0] = g_last_data; + chdr[1] = g_last_ext_data; + + return 2; /* number of words read */ +} + +int ipc_platform_compact_write_msg(struct ipc_cmd_hdr *hdr, int words) +{ + return 0; /* number of words read - not currently used on this platform */ +} + +enum task_state ipc_platform_do_cmd(struct ipc *ipc) +{ + struct ipc_cmd_hdr *hdr; + + hdr = ipc_compact_read_msg(); + + /* perform command */ + ipc_cmd(hdr); + + return SOF_TASK_STATE_COMPLETED; +} + +void ipc_platform_complete_cmd(struct ipc *ipc) +{ + ARG_UNUSED(ipc); + intel_adsp_ipc_complete(INTEL_ADSP_IPC_HOST_DEV); + +#if CONFIG_DEBUG_IPC_COUNTERS + increment_ipc_processed_counter(); +#endif +} + +int ipc_platform_send_msg(const struct ipc_msg *msg) +{ + if (!intel_adsp_ipc_is_complete(INTEL_ADSP_IPC_HOST_DEV)) + return -EBUSY; + + /* prepare the message and copy to mailbox */ + struct ipc_cmd_hdr *hdr = ipc_prepare_to_send(msg); + + if (!intel_adsp_ipc_send_message(INTEL_ADSP_IPC_HOST_DEV, hdr->pri, hdr->ext)) + /* IPC device is busy with something else */ + return -EBUSY; + + return 0; +} + +int platform_ipc_init(struct ipc *ipc) +{ + ipc_set_drvdata(ipc, NULL); + + /* schedule task */ + schedule_task_init_edf(&ipc->ipc_task, SOF_UUID(ipc_task_uuid), + &ipc_task_ops, ipc, 0, 0); + + /* configure interrupt - some work is done internally by Zephytr API */ + + /* attach handlers */ + intel_adsp_ipc_set_message_handler(INTEL_ADSP_IPC_HOST_DEV, message_handler, ipc); + + return 0; +} diff --git a/src/platform/intel/ace/include/ace/lib/clk.h b/src/platform/intel/ace/include/ace/lib/clk.h new file mode 100644 index 000000000000..abaf6e5f47da --- /dev/null +++ b/src/platform/intel/ace/include/ace/lib/clk.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * + * Copyright(c) 2022 Intel Corporation. All rights reserved. + * + * Author: Liam Girdwood + * Keyon Jie + * Rander Wang + * Adrian Warecki + */ + +/** + * \file ace/lib/clk.h + * \brief Clk parameters for run-time clock data, common for cAVS platforms. + */ + +#ifdef __PLATFORM_LIB_CLK_H__ + +#ifndef __ACE_LIB_CLK_H__ +#define __ACE_LIB_CLK_H__ + +#include +#include +#include +#include +#include +#include + +struct sof; + +/** \brief Core(s) settings, up to CONFIG_CORE_COUNT */ +#define CLK_CPU(x) (x) + +/** \brief SSP clock r-t settings are after the core(s) settings */ +#define CLK_SSP CONFIG_CORE_COUNT + +/* SSP clock run-time data is the last one, so total number is ssp idx +1 */ + +/** \brief Total number of clocks */ +#define NUM_CLOCKS (CLK_SSP + 1) + +extern const struct freq_table *cpu_freq; +extern const uint32_t cpu_freq_enc[]; +extern const uint32_t cpu_freq_status_mask[]; + +void platform_clock_init(struct sof *sof); + +void platform_clock_on_waiti(void); +void platform_clock_on_wakeup(void); + +#endif /* __ACE_LIB_CLK_H__ */ + +#else + +#error "This file shouldn't be included from outside of platform/lib/clk.h" + +#endif /* __PLATFORM_LIB_CLK_H__ */ diff --git a/src/platform/intel/ace/include/ace/lib/cpu.h b/src/platform/intel/ace/include/ace/lib/cpu.h new file mode 100644 index 000000000000..b4d0b88f112f --- /dev/null +++ b/src/platform/intel/ace/include/ace/lib/cpu.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * + * Copyright(c) 2022 Intel Corporation. All rights reserved. + */ + +/** + * \file ace/lib/cpu.h + * \brief DSP parameters, common for cAVS platforms. + */ + +#ifdef __PLATFORM_LIB_CPU_H__ + +#ifndef __ACE_LIB_CPU_H__ +#define __ACE_LIB_CPU_H__ + +/** \brief Id of primary DSP core */ +#define PLATFORM_PRIMARY_CORE_ID 0 + +#endif /* __ACE_LIB_CPU_H__ */ + +#else + +#error "This file shouldn't be included from outside of platform/lib/cpu.h" + +#endif /* __PLATFORM_LIB_CPU_H__ */ diff --git a/src/platform/intel/ace/include/ace/lib/memory.h b/src/platform/intel/ace/include/ace/lib/memory.h new file mode 100644 index 000000000000..46b131d11a0b --- /dev/null +++ b/src/platform/intel/ace/include/ace/lib/memory.h @@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * + * Copyright(c) 2022 Intel Corporation. All rights reserved. + * + * Author: Bartosz Kokoszko + */ + +#ifdef __PLATFORM_LIB_MEMORY_H__ + +#ifndef __ACE_LIB_MEMORY_H__ +#define __ACE_LIB_MEMORY_H__ + +#include +#include +#if !defined(__ASSEMBLER__) && !defined(LINKER) +#include +#endif + +#define SRAM_BANK_SIZE (128 * 1024) + +#define EBB_BANKS_IN_SEGMENT 32 + +/* data cache line alignment */ +#define PLATFORM_DCACHE_ALIGN DCACHE_LINE_SIZE + +/** + * \brief Data shared between different cores. + * Placed into dedicated section, which should be accessed through + * uncached memory region. SMP platforms without uncache can simply + * align to cache line size instead. + */ +#define SHARED_DATA + +#define PLATFORM_LPSRAM_EBB_COUNT (DT_REG_SIZE(DT_NODELABEL(sram1)) / SRAM_BANK_SIZE) +#define PLATFORM_HPSRAM_EBB_COUNT (DT_REG_SIZE(DT_NODELABEL(sram0)) / SRAM_BANK_SIZE) + +#define SRAM_CACHED_BASE 0xA0000000 +#define SRAM_BASE 0x40000000 +#define SRAM_ALIAS_MASK 0xF0000000 +#define SRAM_ALIAS_OFFSET 0x60000000 + +#if !defined UNIT_TEST +#define uncache_to_cache(address) \ + ((__typeof__(address))(((uint32_t)(address) & \ + ~SRAM_ALIAS_MASK) | SRAM_CACHED_BASE)) +#define is_uncached(address) \ + (((uint32_t)(address) & SRAM_ALIAS_MASK) == SRAM_BASE) +#define cache_to_uncache(address) \ + ((__typeof__(address))(((uint32_t)(address) & \ + ~SRAM_ALIAS_MASK) | SRAM_BASE)) +#else +#define uncache_to_cache(address) address +#define cache_to_uncache(address) address +#define is_uncached(address) 0 +#endif + +/** + * \brief Returns pointer to the memory shared by multiple cores. + * \param[in,out] ptr Initial pointer to the allocated memory. + * \param[in] bytes Size of the allocated memory + * \return Appropriate pointer to the shared memory. + * + * This function is called only once right after allocation of shared memory. + * Platforms with uncached memory region should return aliased address. + * On platforms without such region simple invalidate is enough. + */ +static inline void *platform_shared_get(void *ptr, int bytes) +{ + return ptr; +} + +#endif /* __ACE_LIB_MEMORY_H__ */ + +#else + +#error "This file shouldn't be included from outside of platform/lib/memory.h" + +#endif /* __PLATFORM_LIB_MEMORY_H__ */ diff --git a/src/platform/intel/ace/include/ace/version.h b/src/platform/intel/ace/include/ace/version.h new file mode 100644 index 000000000000..26eb80f053e7 --- /dev/null +++ b/src/platform/intel/ace/include/ace/version.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * + * Copyright(c) 2022 Intel Corporation. All rights reserved. + * + * Author: Adrian Warecki + */ + +#ifndef __ACE_VERSION_H__ +#define __ACE_VERSION_H__ + +#define ACE_VERSION_1_5 0x10500 + +/* ACE version defined by CONFIG_ACE_VER_ */ +#if CONFIG_ACE_VERSION_1_5 +#define ACE_VERSION ACE_VERSION_1_5 +#endif + +#define HW_CFG_VERSION ACE_VERSION + +#endif /* __ACE_VERSION_H__ */ diff --git a/src/platform/intel/ace/platform.c b/src/platform/intel/ace/platform.c new file mode 100644 index 000000000000..138ac495434b --- /dev/null +++ b/src/platform/intel/ace/platform.c @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: BSD-3-Clause +// +// Copyright(c) 2022 Intel Corporation. All rights reserved. +// +// Author: Liam Girdwood +// Keyon Jie +// Rander Wang +// Janusz Jankowski + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +static const struct sof_ipc_fw_ready ready + __section(".fw_ready") = { + .hdr = { + .cmd = SOF_IPC_FW_READY, + .size = sizeof(struct sof_ipc_fw_ready), + }, + .version = { + .hdr.size = sizeof(struct sof_ipc_fw_version), + .micro = SOF_MICRO, + .minor = SOF_MINOR, + .major = SOF_MAJOR, +/* opt-in; reproducible build by default */ +#if BLD_COUNTERS + .build = SOF_BUILD, /* See version-build-counter.cmake */ + .date = __DATE__, + .time = __TIME__, +#else /* BLD_COUNTERS */ + .build = -1, + .date = "dtermin.\0", + .time = "fwready.\0", +#endif /* BLD_COUNTERS */ + .tag = SOF_TAG, + .abi_version = SOF_ABI_VERSION, + .src_hash = SOF_SRC_HASH, + }, + .flags = DEBUG_SET_FW_READY_FLAGS, +}; + +int platform_boot_complete(uint32_t boot_message) +{ + struct ipc_cmd_hdr header; + + /* get any IPC specific boot message and optional data */ + ipc_boot_complete_msg(&header, 0); + + struct ipc_msg msg = { + .header = header.pri, + .extension = header.ext, + .tx_size = sizeof(ready), + .tx_data = (void *)&ready, + }; + + /* send fimrware ready message. */ + return ipc_platform_send_msg(&msg); +} + +/* Runs on the primary core only */ +int platform_init(struct sof *sof) +{ + trace_point(TRACE_BOOT_PLATFORM_SCHED); + scheduler_init_edf(); + + /* init low latency timer domain and scheduler */ + sof->platform_timer_domain = zephyr_domain_init(PLATFORM_DEFAULT_CLOCK); + scheduler_init_ll(sof->platform_timer_domain); + + /* init the system agent */ + trace_point(TRACE_BOOT_PLATFORM_AGENT); + sa_init(sof, CONFIG_SYSTICK_PERIOD); + + /* initialize the host IPC mechanisms */ + trace_point(TRACE_BOOT_PLATFORM_IPC); + ipc_init(sof); + + /* show heap status */ + heap_trace_all(1); + + return 0; +} + +int platform_context_save(struct sof *sof) +{ + return 0; +} diff --git a/src/platform/meteorlake/include/platform/lib/clk.h b/src/platform/meteorlake/include/platform/lib/clk.h new file mode 100644 index 000000000000..2eb1732aad55 --- /dev/null +++ b/src/platform/meteorlake/include/platform/lib/clk.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * + * Copyright(c) 2022 Intel Corporation. All rights reserved. + * + * Author: Liam Girdwood + * Keyon Jie + * Rander Wang + */ + +#ifdef __SOF_LIB_CLK_H__ + +#ifndef __PLATFORM_LIB_CLK_H__ +#define __PLATFORM_LIB_CLK_H__ + +#include + +#define CLK_MAX_CPU_HZ 400000000 + +#define CPU_WOVCRO_FREQ_IDX 0 + +#define CPU_LPRO_FREQ_IDX 1 + +#define CPU_HPRO_FREQ_IDX 2 + +#define CPU_LOWEST_FREQ_IDX CPU_WOVCRO_FREQ_IDX + +#define CPU_DEFAULT_IDX CPU_HPRO_FREQ_IDX + +#define SSP_DEFAULT_IDX 1 + +#define NUM_CPU_FREQ 3 + +#define NUM_SSP_FREQ 3 + +#endif /* __PLATFORM_LIB_CLK_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/lib/clk.h" + +#endif /* __SOF_LIB_CLK_H__ */ diff --git a/src/platform/meteorlake/include/platform/lib/cpu.h b/src/platform/meteorlake/include/platform/lib/cpu.h new file mode 100644 index 000000000000..989fb61bf093 --- /dev/null +++ b/src/platform/meteorlake/include/platform/lib/cpu.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * + * Copyright(c) 2022 Intel Corporation. All rights reserved. + */ + +/** + * \file + * \brief DSP core parameters. + */ + +#ifdef __SOF_LIB_CPU_H__ + +#ifndef __PLATFORM_LIB_CPU_H__ +#define __PLATFORM_LIB_CPU_H__ + +#include + +#endif /* __PLATFORM_LIB_CPU_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/lib/cpu.h" + +#endif /* __SOF_LIB_CPU_H__ */ diff --git a/src/platform/meteorlake/include/platform/lib/memory.h b/src/platform/meteorlake/include/platform/lib/memory.h new file mode 100644 index 000000000000..7f81603391e2 --- /dev/null +++ b/src/platform/meteorlake/include/platform/lib/memory.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * + * Copyright(c) 2022 Intel Corporation. All rights reserved. + * + * Author: Marcin Rajwa + */ + +#ifdef __SOF_LIB_MEMORY_H__ + +#ifndef __PLATFORM_LIB_MEMORY_H__ +#define __PLATFORM_LIB_MEMORY_H__ + +#include +#include +#include + +/* HP SRAM windows */ +/* window 0 */ +#define SRAM_SW_REG_BASE ((uint32_t)HP_SRAM_WIN0_BASE) +#define SRAM_SW_REG_SIZE ((uint32_t)HP_SRAM_WIN0_SIZE) + +#define SRAM_OUTBOX_BASE (SRAM_SW_REG_BASE + SRAM_SW_REG_SIZE) +#define SRAM_OUTBOX_SIZE 0x1000 + +/* window 1 */ +#define SRAM_INBOX_BASE (SRAM_OUTBOX_BASE + SRAM_OUTBOX_SIZE) +#define SRAM_INBOX_SIZE 0x2000 + +/* window 2 */ +#define SRAM_DEBUG_BASE ((uint32_t)HP_SRAM_WIN2_BASE) +#define SRAM_DEBUG_SIZE ((uint32_t)HP_SRAM_WIN2_SIZE) + +#define SRAM_EXCEPT_BASE (SRAM_DEBUG_BASE + SRAM_DEBUG_SIZE) +#define SRAM_EXCEPT_SIZE 0x800 + +#define SRAM_STREAM_BASE (SRAM_EXCEPT_BASE + SRAM_EXCEPT_SIZE) +#define SRAM_STREAM_SIZE 0x1000 + +/* Stack configuration */ +#define SOF_STACK_SIZE 0x1000 + +#define PLATFORM_HEAP_SYSTEM CONFIG_CORE_COUNT /* one per core */ +#define PLATFORM_HEAP_SYSTEM_RUNTIME CONFIG_CORE_COUNT /* one per core */ +#define PLATFORM_HEAP_RUNTIME 1 +#define PLATFORM_HEAP_RUNTIME_SHARED 1 +#define PLATFORM_HEAP_SYSTEM_SHARED 1 +#define PLATFORM_HEAP_BUFFER 2 + +/* boot loader in IMR */ +#define IMR_BOOT_LDR_MANIFEST_BASE 0xA1042000 +#define IMR_BOOT_LDR_MANIFEST_SIZE 0x6000 + +#endif /* __PLATFORM_LIB_MEMORY_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/lib/memory.h" + +#endif /* __SOF_LIB_MEMORY_H__ */ diff --git a/src/platform/meteorlake/include/platform/lib/shim.h b/src/platform/meteorlake/include/platform/lib/shim.h new file mode 100644 index 000000000000..fa12a9b6d11b --- /dev/null +++ b/src/platform/meteorlake/include/platform/lib/shim.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * + * Copyright(c) 2022 Intel Corporation. All rights reserved. + * + * Author: Liam Girdwood + * Keyon Jie + * Rander Wang + */ + +#ifdef __SOF_LIB_SHIM_H__ + +#ifndef __PLATFORM_LIB_SHIM_H__ +#define __PLATFORM_LIB_SHIM_H__ + +#include +#include + +/** \brief Request HP RING Oscillator Clock */ +#define SHIM_CLKCTL_RHROSCC BIT(31) + +/** \brief Request WOVCRO Clock */ +#define SHIM_CLKCTL_WOV_CRO_REQUEST BIT(4) + +/** \brief Request LP RING Oscillator Clock */ +#define SHIM_CLKCTL_RLROSCC BIT(29) + +/** \brief Oscillator Clock Select*/ +#define SHIM_CLKCTL_OCS_HP_RING BIT(2) +#define SHIM_CLKCTL_OCS_LP_RING 0 +#define SHIM_CLKCTL_WOVCROSC BIT(3) + +/** \brief LP Memory Clock Select */ +#define SHIM_CLKCTL_LMCS_DIV4 BIT(1) + +/** \brief HP Memory Clock Select */ +#define SHIM_CLKCTL_HMCS_DIV2 0 + +/** \brief HP RING Oscillator Clock Status */ +#define SHIM_CLKSTS_HROSCCS BIT(31) + +/** \brief WOVCRO Clock Status */ +#define SHIM_CLKSTS_WOV_CRO BIT(4) + +/** \brief LP RING Oscillator Clock Status */ +#define SHIM_CLKSTS_LROSCCS BIT(29) + +#define L2HSBPM(x) (0x17A800 + 0x0008 * (x)) +#define SHIM_HSPGCTL(x) (L2HSBPM(x) + 0x0000) + +#define LSPGCTL 0x71D80 + +#endif /* __PLATFORM_LIB_SHIM_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/lib/shim.h" + +#endif /* __SOF_LIB_SHIM_H__ */ diff --git a/src/platform/meteorlake/include/platform/platform.h b/src/platform/meteorlake/include/platform/platform.h new file mode 100644 index 000000000000..cceb15bb78d5 --- /dev/null +++ b/src/platform/meteorlake/include/platform/platform.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * + * Copyright(c) 2022 Intel Corporation. All rights reserved. + * + * Author: Liam Girdwood + * Keyon Jie + * Rander Wang + * Xiuli Pan + */ + +#ifdef __SOF_PLATFORM_H__ + +#ifndef __PLATFORM_PLATFORM_H__ +#define __PLATFORM_PLATFORM_H__ + +#include + +/*! \def PLATFORM_DEFAULT_CLOCK + * \brief clock source for audio pipeline + * + * There are two types of clock: cpu clock which is a internal clock in + * xtensa core, and ssp clock which is provided by external HW IP. + * The choice depends on HW features on different platform + */ +#define PLATFORM_DEFAULT_CLOCK CLK_SSP + +/* Host page size */ +#define HOST_PAGE_SIZE 4096 + +/* Platform stream capabilities */ +#define PLATFORM_MAX_CHANNELS 8 +#define PLATFORM_MAX_STREAMS 16 + +/* local buffer size of DMA tracing */ +#define DMA_TRACE_LOCAL_SIZE (HOST_PAGE_SIZE * 2) + +/* DSP default delay in cycles */ +#define PLATFORM_DEFAULT_DELAY 12 + +#endif /* __PLATFORM_PLATFORM_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/platform.h" + +#endif /* __SOF_PLATFORM_H__ */ diff --git a/src/platform/meteorlake/lib/clk.c b/src/platform/meteorlake/lib/clk.c new file mode 100644 index 000000000000..18b443e54429 --- /dev/null +++ b/src/platform/meteorlake/lib/clk.c @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: BSD-3-Clause +// +// Copyright(c) 2022 Intel Corporation. All rights reserved. +// +// Author: Tomasz Lauda +// Janusz Jankowski + +#include +#include + +static const struct freq_table platform_cpu_freq[] = { + { 38400000, 38400 }, + { 120000000, 120000 }, + { CLK_MAX_CPU_HZ, 400000 }, +}; + +const uint32_t cpu_freq_enc[] = { + SHIM_CLKCTL_WOVCROSC | SHIM_CLKCTL_WOV_CRO_REQUEST | + SHIM_CLKCTL_HMCS_DIV2 | SHIM_CLKCTL_LMCS_DIV4, + SHIM_CLKCTL_RLROSCC | SHIM_CLKCTL_OCS_LP_RING | + SHIM_CLKCTL_HMCS_DIV2 | SHIM_CLKCTL_LMCS_DIV4, + SHIM_CLKCTL_RHROSCC | SHIM_CLKCTL_OCS_HP_RING | + SHIM_CLKCTL_HMCS_DIV2 | SHIM_CLKCTL_LMCS_DIV4, +}; + +const uint32_t cpu_freq_status_mask[] = { + SHIM_CLKSTS_WOV_CRO, + SHIM_CLKSTS_LROSCCS, + SHIM_CLKSTS_HROSCCS +}; + +STATIC_ASSERT(ARRAY_SIZE(platform_cpu_freq) == NUM_CPU_FREQ, + invalid_number_of_cpu_frequencies); + +const struct freq_table *cpu_freq = platform_cpu_freq; diff --git a/zephyr/include/rtos/interrupt.h b/zephyr/include/rtos/interrupt.h index b8c0c2a08e7c..b0dd9fd62c7a 100644 --- a/zephyr/include/rtos/interrupt.h +++ b/zephyr/include/rtos/interrupt.h @@ -48,7 +48,7 @@ static inline void interrupt_unregister(uint32_t irq, const void *arg) */ static inline int interrupt_get_irq(unsigned int irq, const char *cascade) { -#ifdef CONFIG_LIBRARY +#if defined(CONFIG_LIBRARY) || defined(CONFIG_ACE) return irq; #else if (cascade == irq_name_level2) From b233772a44a36bb5eea3ff068347b610869095ec Mon Sep 17 00:00:00 2001 From: Adrian Warecki Date: Tue, 6 Sep 2022 15:28:35 +0200 Subject: [PATCH 12/39] mtl: Add dummy header/source files required by SOF This commit adds empty header files required to build a project successfully. The templates for the required functions have also been added. Signed-off-by: Adrian Warecki --- .../intel/ace/include/ace/drivers/idc.h | 23 +++++ .../intel/ace/include/ace/drivers/interrupt.h | 17 ++++ .../intel/ace/include/ace/lib/mailbox.h | 97 +++++++++++++++++++ src/platform/intel/ace/lib/pm_runtime.c | 30 ++++++ .../meteorlake/include/platform/drivers/alh.h | 19 ++++ .../meteorlake/include/platform/drivers/idc.h | 19 ++++ .../include/platform/drivers/interrupt.h | 36 +++++++ .../meteorlake/include/platform/lib/dai.h | 46 +++++++++ .../meteorlake/include/platform/lib/dma.h | 23 +++++ .../meteorlake/include/platform/lib/mailbox.h | 19 ++++ .../include/platform/lib/pm_runtime.h | 70 +++++++++++++ .../meteorlake/include/platform/trace/trace.h | 26 +++++ 12 files changed, 425 insertions(+) create mode 100644 src/platform/intel/ace/include/ace/drivers/idc.h create mode 100644 src/platform/intel/ace/include/ace/drivers/interrupt.h create mode 100644 src/platform/intel/ace/include/ace/lib/mailbox.h create mode 100644 src/platform/intel/ace/lib/pm_runtime.c create mode 100644 src/platform/meteorlake/include/platform/drivers/alh.h create mode 100644 src/platform/meteorlake/include/platform/drivers/idc.h create mode 100644 src/platform/meteorlake/include/platform/drivers/interrupt.h create mode 100644 src/platform/meteorlake/include/platform/lib/dai.h create mode 100644 src/platform/meteorlake/include/platform/lib/dma.h create mode 100644 src/platform/meteorlake/include/platform/lib/mailbox.h create mode 100644 src/platform/meteorlake/include/platform/lib/pm_runtime.h create mode 100644 src/platform/meteorlake/include/platform/trace/trace.h diff --git a/src/platform/intel/ace/include/ace/drivers/idc.h b/src/platform/intel/ace/include/ace/drivers/idc.h new file mode 100644 index 000000000000..d57ca3dd79a0 --- /dev/null +++ b/src/platform/intel/ace/include/ace/drivers/idc.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * + * Copyright(c) 2022 Intel Corporation. All rights reserved. + */ + +#ifdef __PLATFORM_DRIVERS_IDC_H__ + +#ifndef __ACE_DRIVERS_IDC_H__ +#define __ACE_DRIVERS_IDC_H__ + +struct idc_msg; + +int idc_send_msg(struct idc_msg *msg, uint32_t mode); + +int idc_init(void); + +#endif /* __ACE_DRIVERS_IDC_H__ */ + +#else + +#error "This file shouldn't be included from outside of platform/drivers/idc.h" + +#endif /* __PLATFORM_DRIVERS_IDC_H__ */ diff --git a/src/platform/intel/ace/include/ace/drivers/interrupt.h b/src/platform/intel/ace/include/ace/drivers/interrupt.h new file mode 100644 index 000000000000..4b580e4e8a9f --- /dev/null +++ b/src/platform/intel/ace/include/ace/drivers/interrupt.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * + * Copyright(c) 2022 Intel Corporation. All rights reserved. + */ + +#ifdef __PLATFORM_DRIVERS_INTERRUPT_H__ + +#ifndef __ACE_DRIVERS_INTERRUPT_H__ +#define __ACE_DRIVERS_INTERRUPT_H__ + +#endif /* __ACE_DRIVERS_INTERRUPT_H__ */ + +#else + +#error "This file shouldn't be included from outside of platform/drivers/interrupt.h" + +#endif /* __PLATFORM_DRIVERS_INTERRUPT_H__ */ diff --git a/src/platform/intel/ace/include/ace/lib/mailbox.h b/src/platform/intel/ace/include/ace/lib/mailbox.h new file mode 100644 index 000000000000..68d09e27a1cc --- /dev/null +++ b/src/platform/intel/ace/include/ace/lib/mailbox.h @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * + * Copyright(c) 2022 Intel Corporation. All rights reserved. + * + * Author: Liam Girdwood + * Keyon Jie + */ + +#ifdef __PLATFORM_LIB_MAILBOX_H__ + +#ifndef __ACE_LIB_MAILBOX_H__ +#define __ACE_LIB_MAILBOX_H__ + +#include +#include +#include +#include +#include + +#define MAILBOX_HOSTBOX_BASE SRAM_INBOX_BASE + + /* window 3 - trace */ +#define MAILBOX_TRACE_SIZE SRAM_TRACE_SIZE +#define MAILBOX_TRACE_BASE SRAM_TRACE_BASE + +#define MAILBOX_STREAM_SIZE SRAM_STREAM_SIZE +#define MAILBOX_STREAM_BASE SRAM_STREAM_BASE + + /* window 1 inbox/downlink and FW registers */ +#define MAILBOX_HOSTBOX_SIZE SRAM_INBOX_SIZE + + /* window 0 */ +#define MAILBOX_DSPBOX_SIZE SRAM_OUTBOX_SIZE +#define MAILBOX_DSPBOX_BASE SRAM_OUTBOX_BASE + +#define MAILBOX_SW_REG_SIZE SRAM_SW_REG_SIZE +#define MAILBOX_SW_REG_BASE SRAM_SW_REG_BASE + +static inline void mailbox_sw_reg_write(size_t offset, uint32_t src) +{ + volatile uint32_t *ptr; + volatile uint32_t __sparse_cache *ptr_c; + + ptr_c = (volatile uint32_t __sparse_cache *)(MAILBOX_SW_REG_BASE + offset); + ptr = cache_to_uncache(ptr_c); + *ptr = src; +} + +static inline void mailbox_sw_reg_write64(size_t offset, uint64_t src) +{ + volatile uint64_t *ptr; + volatile uint64_t __sparse_cache *ptr_c; + + ptr_c = (volatile uint64_t __sparse_cache *)(MAILBOX_SW_REG_BASE + offset); + ptr = cache_to_uncache(ptr_c); + *ptr = src; +} + +static inline uint32_t mailbox_sw_reg_read(size_t offset) +{ + volatile uint32_t *ptr; + volatile uint32_t __sparse_cache *ptr_c; + + ptr_c = (volatile uint32_t __sparse_cache *)(MAILBOX_SW_REG_BASE + offset); + ptr = cache_to_uncache(ptr_c); + + return *ptr; +} + +static inline uint64_t mailbox_sw_reg_read64(size_t offset) +{ + volatile uint64_t *ptr; + volatile uint64_t __sparse_cache *ptr_c; + + ptr_c = (volatile uint64_t __sparse_cache *)(MAILBOX_SW_REG_BASE + offset); + ptr = cache_to_uncache(ptr_c); + + return *ptr; +} + +static inline void mailbox_sw_regs_write(size_t offset, const void *src, size_t bytes) +{ + int regs_write_err __unused = memcpy_s((void *)(MAILBOX_SW_REG_BASE + offset), + MAILBOX_SW_REG_SIZE - offset, src, bytes); + + assert(!regs_write_err); + dcache_writeback_region((__sparse_force void __sparse_cache *)(MAILBOX_SW_REG_BASE + + offset), bytes); +} + +#endif /* __ACE_LIB_MAILBOX_H__ */ + +#else + +#error "This file shouldn't be included from outside of platform/lib/mailbox.h" + +#endif /* __PLATFORM_LIB_MAILBOX_H__ */ diff --git a/src/platform/intel/ace/lib/pm_runtime.c b/src/platform/intel/ace/lib/pm_runtime.c new file mode 100644 index 000000000000..07e9b7d794b6 --- /dev/null +++ b/src/platform/intel/ace/lib/pm_runtime.c @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: BSD-3-Clause +// +// Copyright(c) 2022 Intel Corporation. All rights reserved. + +#include +#include +#include +#include +#include +#include + +/* 76cc9773-440c-4df9-95a8-72defe7796fc */ +DECLARE_SOF_UUID("power", power_uuid, 0x76cc9773, 0x440c, 0x4df9, + 0x95, 0xa8, 0x72, 0xde, 0xfe, 0x77, 0x96, 0xfc); + +DECLARE_TR_CTX(power_tr, SOF_UUID(power_uuid), LOG_LEVEL_INFO); + +void platform_pm_runtime_init(struct pm_runtime_data *prd) +{ } + +void platform_pm_runtime_get(enum pm_runtime_context context, uint32_t index, + uint32_t flags) +{ } + +void platform_pm_runtime_put(enum pm_runtime_context context, uint32_t index, + uint32_t flags) +{ } + +void platform_pm_runtime_prepare_d0ix_en(uint32_t index) +{ } diff --git a/src/platform/meteorlake/include/platform/drivers/alh.h b/src/platform/meteorlake/include/platform/drivers/alh.h new file mode 100644 index 000000000000..bd2946104ad6 --- /dev/null +++ b/src/platform/meteorlake/include/platform/drivers/alh.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * + * Copyright(c) 2022 Intel Corporation. All rights reserved. + */ + +#ifdef __SOF_DRIVERS_ALH__ + +#ifndef __PLATFORM_DRIVERS_ALH__ +#define __PLATFORM_DRIVERS_ALH__ + +#include + +#endif /* __PLATFORM_DRIVERS_ALH__ */ + +#else + +#error "This file shouldn't be included from outside of sof/drivers/alh.h" + +#endif diff --git a/src/platform/meteorlake/include/platform/drivers/idc.h b/src/platform/meteorlake/include/platform/drivers/idc.h new file mode 100644 index 000000000000..593b567b0c6f --- /dev/null +++ b/src/platform/meteorlake/include/platform/drivers/idc.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * + * Copyright(c) 2022 Intel Corporation. All rights reserved. + */ + +#ifdef __SOF_DRIVERS_IDC_H__ + +#ifndef __PLATFORM_DRIVERS_IDC_H__ +#define __PLATFORM_DRIVERS_IDC_H__ + +#include + +#endif /* __PLATFORM_DRIVERS_IDC_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/drivers/idc.h" + +#endif /* __SOF_DRIVERS_IDC_H__ */ diff --git a/src/platform/meteorlake/include/platform/drivers/interrupt.h b/src/platform/meteorlake/include/platform/drivers/interrupt.h new file mode 100644 index 000000000000..4bea8d844a7b --- /dev/null +++ b/src/platform/meteorlake/include/platform/drivers/interrupt.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * + * Copyright(c) 2022 Intel Corporation. All rights reserved. + * + * Author: Liam Girdwood + * Keyon Jie + * Rander Wang + */ + +#ifdef __SOF_DRIVERS_INTERRUPT_H__ + +#ifndef __PLATFORM_DRIVERS_INTERRUPT_H__ +#define __PLATFORM_DRIVERS_INTERRUPT_H__ + +#if !defined(__ASSEMBLER__) && !defined(LINKER) + +#include + +#include + +#endif + +/* Required by sof/drivers/interrupt.h */ +#define PLATFORM_IRQ_CHILDREN 32 + +/* Required by zephyr/wrapper.c */ +#define IRQ_NUM_EXT_LEVEL2 4 /* level 2 */ +#define IRQ_NUM_EXT_LEVEL5 16 /* level 5 */ + +#endif /* __PLATFORM_DRIVERS_INTERRUPT_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/drivers/interrupt.h" + +#endif /* __SOF_DRIVERS_INTERRUPT_H__ */ diff --git a/src/platform/meteorlake/include/platform/lib/dai.h b/src/platform/meteorlake/include/platform/lib/dai.h new file mode 100644 index 000000000000..2b6386a35a90 --- /dev/null +++ b/src/platform/meteorlake/include/platform/lib/dai.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * + * Copyright(c) 2022 Intel Corporation. All rights reserved. + * + * Author: Marcin Maka + */ + +#ifdef __SOF_LIB_DAI_H__ + +#ifndef __PLATFORM_LIB_DAI_H__ +#define __PLATFORM_LIB_DAI_H__ + +/* SSP */ + +/* + * Number of base and extended SSP ports must be defined separately + * since some HW registers are in two groups, one for base and one + * for extended. + */ + +/** \brief Number of 'base' SSP ports available */ +#define DAI_NUM_SSP_BASE 6 + +/* HD/A */ + +/** \brief Number of HD/A Link Outputs */ +#define DAI_NUM_HDA_OUT 9 + +/** \brief Number of HD/A Link Inputs */ +#define DAI_NUM_HDA_IN 7 + +/* ALH */ + +/** \brief Number of ALH bi-directional links */ +#define DAI_NUM_ALH_BI_DIR_LINKS 16 + +/** \brief Number of contiguous ALH bi-dir links */ +#define DAI_NUM_ALH_BI_DIR_LINKS_GROUP 4 + +#endif /* __PLATFORM_LIB_DAI_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/lib/dai.h" + +#endif /* __SOF_LIB_DAI_H__ */ diff --git a/src/platform/meteorlake/include/platform/lib/dma.h b/src/platform/meteorlake/include/platform/lib/dma.h new file mode 100644 index 000000000000..ca10b4937c99 --- /dev/null +++ b/src/platform/meteorlake/include/platform/lib/dma.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * + * Copyright(c) 2022 Intel Corporation. All rights reserved. + */ + +#ifdef __SOF_LIB_DMA_H__ + +#ifndef __PLATFORM_LIB_DMA_H__ +#define __PLATFORM_LIB_DMA_H__ + +/* max number of supported DMA channels */ +#define PLATFORM_MAX_DMA_CHAN 9 + +/* number of supported DMACs */ +#define PLATFORM_NUM_DMACS 6 + +#endif /* __PLATFORM_LIB_DMA_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/lib/dma.h" + +#endif /* __SOF_LIB_DMA_H__ */ diff --git a/src/platform/meteorlake/include/platform/lib/mailbox.h b/src/platform/meteorlake/include/platform/lib/mailbox.h new file mode 100644 index 000000000000..3b7f218ad563 --- /dev/null +++ b/src/platform/meteorlake/include/platform/lib/mailbox.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * + * Copyright(c) 2022 Intel Corporation. All rights reserved. + */ + +#ifdef __SOF_LIB_MAILBOX_H__ + +#ifndef __PLATFORM_LIB_MAILBOX_H__ +#define __PLATFORM_LIB_MAILBOX_H__ + +#include + +#endif /* __PLATFORM_LIB_MAILBOX_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/lib/mailbox.h" + +#endif /* __SOF_LIB_MAILBOX_H__ */ diff --git a/src/platform/meteorlake/include/platform/lib/pm_runtime.h b/src/platform/meteorlake/include/platform/lib/pm_runtime.h new file mode 100644 index 000000000000..bbf7c018e904 --- /dev/null +++ b/src/platform/meteorlake/include/platform/lib/pm_runtime.h @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * + * Copyright(c) 2022 Intel Corporation. All rights reserved. + * + * Author: Tomasz Lauda + */ + +/** + * \file platform/tigerlake/include/platform/lib/pm_runtime.h + * \brief Runtime power management header file for Tigerlake + * \author Tomasz Lauda + */ + +#ifdef __SOF_LIB_PM_RUNTIME_H__ + +#ifndef __PLATFORM_LIB_PM_RUNTIME_H__ +#define __PLATFORM_LIB_PM_RUNTIME_H__ + +#include +#include + +/** + * \brief extra pwr flag to power up a core with a specific reason + * it can be powered down only with the same reason (flag) + */ +#define PWRD_MASK MASK(31, 30) +#define PWRD_BY_HPRO BIT(31) /**< requested by HPRO */ +#define PWRD_BY_TPLG BIT(30) /**< typical power up */ + +struct pm_runtime_data; + +/** + * \brief Initializes platform specific runtime power management. + * \param[in,out] prd Runtime power management data. + */ +void platform_pm_runtime_init(struct pm_runtime_data *prd); + +/** + * \brief Retrieves platform specific power management resource. + * + * \param[in] context Type of power management context. + * \param[in] index Index of the device. + * \param[in] flags Flags, set of RPM_... + */ +void platform_pm_runtime_get(uint32_t context, uint32_t index, uint32_t flags); + +/** + * \brief Releases platform specific power management resource. + * + * \param[in] context Type of power management context. + * \param[in] index Index of the device. + * \param[in] flags Flags, set of RPM_... + */ +void platform_pm_runtime_put(uint32_t context, uint32_t index, uint32_t flags); + +void platform_pm_runtime_prepare_d0ix_en(uint32_t index); + +void platform_pm_runtime_enable(uint32_t context, uint32_t index); + +void platform_pm_runtime_disable(uint32_t context, uint32_t index); + +bool platform_pm_runtime_is_active(uint32_t context, uint32_t index); + +#endif /* __PLATFORM_LIB_PM_RUNTIME_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/lib/pm_runtime.h" + +#endif /* __SOF_LIB_PM_RUNTIME_H__ */ diff --git a/src/platform/meteorlake/include/platform/trace/trace.h b/src/platform/meteorlake/include/platform/trace/trace.h new file mode 100644 index 000000000000..b69592196cdb --- /dev/null +++ b/src/platform/meteorlake/include/platform/trace/trace.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * + * Copyright(c) 2022 Intel Corporation. All rights reserved. + */ + +#ifdef __SOF_TRACE_TRACE_H__ + +#ifndef __PLATFORM_TRACE_TRACE_H__ +#define __PLATFORM_TRACE_TRACE_H__ + +#include +#include +#include +#include + +/* Platform defined trace code */ +static inline void platform_trace_point(uint32_t x) +{ } + +#endif /* __PLATFORM_TRACE_TRACE_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/trace/trace.h" + +#endif /* __SOF_TRACE_TRACE_H__ */ From e8074138b04b2703f7c42351e90944e94b8d5b4c Mon Sep 17 00:00:00 2001 From: Adrian Warecki Date: Wed, 14 Sep 2022 19:26:55 +0200 Subject: [PATCH 13/39] base_fw: Add support for multiple platforms This commit defines a new value HW_CFG_VERSION containing the hardware version of the platform. Signed-off-by: Adrian Warecki --- src/audio/base_fw.c | 2 +- src/platform/intel/cavs/include/cavs/version.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/src/audio/base_fw.c b/src/audio/base_fw.c index 4d0ab9522849..4227e932c994 100644 --- a/src/audio/base_fw.c +++ b/src/audio/base_fw.c @@ -125,7 +125,7 @@ static int basefw_hw_config(uint32_t *data_offset, char *data) struct ipc4_tuple *tuple = (struct ipc4_tuple *)data; uint32_t value; - set_tuple_uint32(tuple, IPC4_CAVS_VER_HW_CFG, CAVS_VERSION); + set_tuple_uint32(tuple, IPC4_CAVS_VER_HW_CFG, HW_CFG_VERSION); tuple = next_tuple(tuple); set_tuple_uint32(tuple, IPC4_DSP_CORES_HW_CFG, CONFIG_CORE_COUNT); diff --git a/src/platform/intel/cavs/include/cavs/version.h b/src/platform/intel/cavs/include/cavs/version.h index f3425bb044fe..6f06d7802a31 100644 --- a/src/platform/intel/cavs/include/cavs/version.h +++ b/src/platform/intel/cavs/include/cavs/version.h @@ -24,4 +24,6 @@ #define CAVS_VERSION CAVS_VERSION_2_5 #endif +#define HW_CFG_VERSION CAVS_VERSION + #endif /* __CAVS_VERSION_H__ */ From 84e837e83c1285e010f738d4de5f8762984e1870 Mon Sep 17 00:00:00 2001 From: Rafal Redzimski Date: Fri, 3 Jun 2022 11:05:46 +0200 Subject: [PATCH 14/39] platform: ace: define a dedicated heap section Define a dedicated .heap section in case of zephyr build. Such explicit section is required to allow for unmapping of unused physical pages which can be later used for loadable library/modules support. Signed-off-by: Rafal Redzimski --- zephyr/wrapper.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/zephyr/wrapper.c b/zephyr/wrapper.c index b085851a6703..9b78adbecbed 100644 --- a/zephyr/wrapper.c +++ b/zephyr/wrapper.c @@ -70,6 +70,18 @@ DECLARE_TR_CTX(zephyr_tr, SOF_UUID(zephyr_uuid), LOG_LEVEL_INFO); */ __section(".heap_mem") static uint8_t __aligned(64) heapmem[HEAPMEM_SIZE]; +#elif CONFIG_ACE + +#define HEAPMEM_SIZE 0x40000 + +/* + * System heap definition for ACE is defined below. + * It needs to be explicitly packed into dedicated section + * to allow memory management driver to control unused + * memory pages. + */ +__section(".heap_mem") static uint8_t __aligned(PLATFORM_DCACHE_ALIGN) heapmem[HEAPMEM_SIZE]; + #else extern char _end[], _heap_sentry[]; From 68d0b7ae14fd3de00376a27ccad376a943a419f9 Mon Sep 17 00:00:00 2001 From: Adrian Warecki Date: Tue, 6 Sep 2022 15:44:56 +0200 Subject: [PATCH 15/39] mtl: Added meteorlake platform to the build system Added new mtl platform to xtensa-build-zephyr.py. Added ace directories to cmake files. Added ACE to kconfig. Add Meteorlake platform to be built with Zephyr under CONFIG_ACE_VERSION_1_5 flag. Signed-off-by: Andrey Borisovich Signed-off-by: Marcin Szkudlinski Signed-off-by: Adrian Warecki Signed-off-by: Konrad Leszczynski Signed-off-by: Anas Nashif Signed-off-by: Tomasz Leman Signed-off-by: Rafal Redzimski Signed-off-by: Adrian Bonislawski --- .github/workflows/zephyr.yml | 1 + scripts/xtensa-build-zephyr.py | 7 +++++ src/platform/Kconfig | 20 ++++++++++++ test/cmocka/CMakeLists.txt | 2 ++ test/cmocka/src/lib/alloc/CMakeLists.txt | 29 +++++++++-------- tools/topology/topology2/CMakeLists.txt | 4 +++ zephyr/CMakeLists.txt | 40 ++++++++++++++++++++++-- zephyr/Kconfig | 2 +- 8 files changed, 89 insertions(+), 16 deletions(-) diff --git a/.github/workflows/zephyr.yml b/.github/workflows/zephyr.yml index c5b0bb8c311d..4d08c9db0a7c 100644 --- a/.github/workflows/zephyr.yml +++ b/.github/workflows/zephyr.yml @@ -20,6 +20,7 @@ jobs: icl jsl, tgl tgl-h, imx8 imx8x imx8m, + mtl, # only tgl has IPC4 overlay file now -i IPC4 tgl, ] diff --git a/scripts/xtensa-build-zephyr.py b/scripts/xtensa-build-zephyr.py index cbd82216fa0a..45411434fd51 100755 --- a/scripts/xtensa-build-zephyr.py +++ b/scripts/xtensa-build-zephyr.py @@ -88,6 +88,13 @@ "XTENSA_TOOLS_VERSION": f"RG-2017.8{xtensa_tools_version_postfix}", "RIMAGE_KEY": pathlib.Path(SOF_TOP, "keys", "otc_private_key_3k.pem") }, + { + "name": "mtl", + "PLAT_CONFIG": "intel_adsp_ace15_mtpm", + "XTENSA_CORE": "ace10_LX7HiFi4_RI_2020_5", + "XTENSA_TOOLS_VERSION": f"RI-2020.5{xtensa_tools_version_postfix}", + "RIMAGE_KEY": pathlib.Path(SOF_TOP, "keys", "otc_private_key_3k.pem") + }, # NXP platforms { "name": "imx8", diff --git a/src/platform/Kconfig b/src/platform/Kconfig index 1feed9f8f22b..e80c6be44d9d 100644 --- a/src/platform/Kconfig +++ b/src/platform/Kconfig @@ -159,6 +159,14 @@ config TIGERLAKE help Select if your target platform is Tigerlake-compatible + +config METEORLAKE + bool "Build for Meteorlake" + select ACE + select ACE_VERSION_1_5 + help + Select if your target platform is Meteorlake-compatible + config LIBRARY bool "Build Library" help @@ -291,6 +299,7 @@ config MAX_CORE_COUNT int default 2 if APOLLOLAKE default 4 if ICELAKE || CANNONLAKE || SUECREEK || TIGERLAKE + default 3 if METEORLAKE default 1 help Maximum number of cores per configuration @@ -374,6 +383,17 @@ config CAVS_VERSION_2_5 help Select for CAVS version 2.5 +config ACE + bool + default n + select INTEL + +config ACE_VERSION_1_5 + depends on ACE + bool + help + Select for ACE version 1.5 + config CONFIG_CHERRYTRAIL_EXTRA_DW_DMA bool "Support Cherrytrail 3rd DMAC" default n if !CHERRYTRAIL diff --git a/test/cmocka/CMakeLists.txt b/test/cmocka/CMakeLists.txt index a75e46a6af44..5e3591df6a61 100644 --- a/test/cmocka/CMakeLists.txt +++ b/test/cmocka/CMakeLists.txt @@ -59,6 +59,8 @@ endif() if(CONFIG_CAVS) target_include_directories(sof_options INTERFACE ${PROJECT_SOURCE_DIR}/src/platform/intel/cavs/include) +elseif(CONFIG_ACE) + target_include_directories(sof_options INTERFACE ${PROJECT_SOURCE_DIR}/src/platform/intel/ace/include) endif() target_include_directories(sof_options INTERFACE ${PROJECT_SOURCE_DIR}/src/arch/xtos-wrapper/include) diff --git a/test/cmocka/src/lib/alloc/CMakeLists.txt b/test/cmocka/src/lib/alloc/CMakeLists.txt index 16a6096830c6..4b7649599435 100644 --- a/test/cmocka/src/lib/alloc/CMakeLists.txt +++ b/test/cmocka/src/lib/alloc/CMakeLists.txt @@ -1,20 +1,23 @@ # SPDX-License-Identifier: BSD-3-Clause if(BUILD_UNIT_TESTS_HOST) -cmocka_test(alloc - alloc.c - ${PROJECT_SOURCE_DIR}/src/lib/alloc.c - ${PROJECT_SOURCE_DIR}/src/platform/library/lib/memory.c - ${PROJECT_SOURCE_DIR}/src/spinlock.c -) + cmocka_test(alloc + alloc.c + ${PROJECT_SOURCE_DIR}/src/lib/alloc.c + ${PROJECT_SOURCE_DIR}/src/platform/library/lib/memory.c + ${PROJECT_SOURCE_DIR}/src/spinlock.c + ) else() -cmocka_test(alloc - alloc.c - ${PROJECT_SOURCE_DIR}/src/lib/alloc.c - ${PROJECT_SOURCE_DIR}/src/debug/panic.c - ${PROJECT_SOURCE_DIR}/src/platform/intel/cavs/lib/memory.c - ${PROJECT_SOURCE_DIR}/src/spinlock.c -) + if(CONFIG_CAVS) + set(MEMORY_FILE ${PROJECT_SOURCE_DIR}/src/platform/intel/cavs/lib/memory.c) + endif() + cmocka_test(alloc + alloc.c + ${PROJECT_SOURCE_DIR}/src/lib/alloc.c + ${PROJECT_SOURCE_DIR}/src/debug/panic.c + ${PROJECT_SOURCE_DIR}/src/spinlock.c + ${MEMORY_FILE} + ) endif() target_include_directories(sof_options INTERFACE ${PROJECT_SOURCE_DIR}/src/platform/intel/cavs/include) diff --git a/tools/topology/topology2/CMakeLists.txt b/tools/topology/topology2/CMakeLists.txt index ae5d2b2b1864..cbc12d09ebcf 100644 --- a/tools/topology/topology2/CMakeLists.txt +++ b/tools/topology/topology2/CMakeLists.txt @@ -17,4 +17,8 @@ else() endif() endif() +if (CONFIG_CAVS) add_subdirectory(cavs) +elseif(CONFIG_ACE) +add_subdirectory(ace) +endif() diff --git a/zephyr/CMakeLists.txt b/zephyr/CMakeLists.txt index 654e07d471b0..e69ee81da5f2 100644 --- a/zephyr/CMakeLists.txt +++ b/zephyr/CMakeLists.txt @@ -419,6 +419,36 @@ if (CONFIG_SOC_SERIES_INTEL_CAVS_V25) zephyr_include_directories(${SOF_PLATFORM_PATH}/intel/cavs/include) endif() +# Intel ACE 1.5 and newer platforms +if (CONFIG_ACE_VERSION_1_5) + + # Driver sources + zephyr_library_sources( + ${SOF_DRIVERS_PATH}/intel/ace/ipc.c + ) + + # Platform sources + zephyr_library_sources( + ${SOF_PLATFORM_PATH}/intel/ace/platform.c + ${SOF_PLATFORM_PATH}/meteorlake/lib/clk.c + ${SOF_PLATFORM_PATH}/intel/ace/lib/pm_runtime.c + ) + + # SOF core infrastructure - runs on top of Zephyr + zephyr_library_sources( + ${SOF_SRC_PATH}/schedule/zephyr_ll.c + ) + + zephyr_library_sources_ifdef(CONFIG_CAVS_LPS + ${SOF_PLATFORM_PATH}/intel/ace/lps_wait.c + ) + + set(PLATFORM "meteorlake") + + zephyr_include_directories(${SOF_PLATFORM_PATH}/intel/ace/include) + zephyr_include_directories(${SOF_PLATFORM_PATH}/meteorlake/include) +endif() + # NXP IMX8 platforms if (CONFIG_SOC_SERIES_NXP_IMX8) zephyr_library_sources( @@ -521,8 +551,7 @@ zephyr_library_sources( ${SOF_SRC_PATH}/arch/xtensa/drivers/cache_attr.c ${SOF_SRC_PATH}/schedule/zephyr_domain.c ${SOF_SRC_PATH}/schedule/schedule.c - ${SOF_SRC_PATH}/schedule/dma_single_chan_domain.c - ${SOF_SRC_PATH}/schedule/dma_multi_chan_domain.c + ${SOF_SRC_PATH}/idc/zephyr_idc.c # Bridge wrapper between SOF and Zephyr APIs - Will shrink over time. @@ -531,6 +560,13 @@ zephyr_library_sources( schedule.c ) +if(CONFIG_SCHEDULE_DMA_SINGLE_CHANNEL) + zephyr_library_sources(${SOF_SRC_PATH}/schedule/dma_single_chan_domain.c) +endif() +if(CONFIG_SCHEDULE_DMA_MULTI_CHANNEL) + zephyr_library_sources(${SOF_SRC_PATH}/schedule/dma_multi_chan_domain.c) +endif() + if(CONFIG_COMP_BLOB) zephyr_library_sources( ${SOF_AUDIO_PATH}/data_blob.c diff --git a/zephyr/Kconfig b/zephyr/Kconfig index 4f047f5b1f3c..8e35fbed6086 100644 --- a/zephyr/Kconfig +++ b/zephyr/Kconfig @@ -3,7 +3,7 @@ rsource "../Kconfig.sof" config SOF_ZEPHYR_HEAP_CACHED bool "Cached Zephyr heap for SOF memory non-shared zones" - default y if CAVS + default y if CAVS || ACE default n help Enable cached heap by mapping cached SOF memory zones to different From b6a792561063db60d205e4f8cffaa97e85147a52 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Fri, 23 Sep 2022 08:40:04 +0300 Subject: [PATCH 16/39] topology2: Revert the conditional topology2 building for CAVS/ACE The MTL support added conditional build for topology2 based on CONFIG_CAVS or CONFIG_ACE. This is wrong for several reasons: There is not ace directory present The Kconfig system is not used when building topologies, so we are ending up not building topology2 files at all. There is no reason why CAVS and ACE topologies should be exclusive. Fixes: 784bce763c0e ("mtl: Added meteorlake platform to the build system") Signed-off-by: Peter Ujfalusi --- tools/topology/topology2/CMakeLists.txt | 4 ---- 1 file changed, 4 deletions(-) diff --git a/tools/topology/topology2/CMakeLists.txt b/tools/topology/topology2/CMakeLists.txt index cbc12d09ebcf..ae5d2b2b1864 100644 --- a/tools/topology/topology2/CMakeLists.txt +++ b/tools/topology/topology2/CMakeLists.txt @@ -17,8 +17,4 @@ else() endif() endif() -if (CONFIG_CAVS) add_subdirectory(cavs) -elseif(CONFIG_ACE) -add_subdirectory(ace) -endif() From eef3fb0ebb7f99add7c3c955c1a58cb8fb7ee6cc Mon Sep 17 00:00:00 2001 From: Marc Herbert Date: Wed, 21 Sep 2022 21:45:16 +0000 Subject: [PATCH 17/39] xtensa-build-zephyr.py: remove misleading -i IPC3 option `./xtensa-build-zephyr.py -i IPC3 mtl` builds the MTL default: IPC4. This is wrong, remove the misleading "IPC3" option which never did anything at all. Fix the --help string to describe what actually happens. This is a build script, no need for fancy abstractions and indirections that don't even match reality. Just tell it like it is. Signed-off-by: Marc Herbert --- scripts/xtensa-build-zephyr.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/scripts/xtensa-build-zephyr.py b/scripts/xtensa-build-zephyr.py index 45411434fd51..cccfd8980157 100755 --- a/scripts/xtensa-build-zephyr.py +++ b/scripts/xtensa-build-zephyr.py @@ -152,8 +152,9 @@ def parse_args(): help="List of platforms to build") parser.add_argument("-d", "--debug", required=False, action="store_true", help="Enable debug build") - parser.add_argument("-i", "--ipc", required=False, choices=["IPC3", "IPC4"], - default="IPC3", help="IPC major version") + parser.add_argument("-i", "--ipc", required=False, choices=["IPC4"], + help="""Generic shortcut for: --overlay /ipc4_overlay.conf. Valid only +for IPC3 platforms supporting IPC4 too.""") # NO SOF release will ever user the option --fw-naming. # This option is only for disguising SOF IPC4 as CAVS IPC4 and only in cases where # the kernel 'ipc_type' expects CAVS IPC4. In this way, developers and CI can test From 948766fb0caccb8d4f4feee9f87d46fa0e13f384 Mon Sep 17 00:00:00 2001 From: Marc Herbert Date: Wed, 21 Sep 2022 21:52:52 +0000 Subject: [PATCH 18/39] .github/zephyr.yml: fix IPC3 / IPC4 comments MTL is IPC4 by default. Signed-off-by: Marc Herbert --- .github/workflows/zephyr.yml | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/.github/workflows/zephyr.yml b/.github/workflows/zephyr.yml index 4d08c9db0a7c..03d491284194 100644 --- a/.github/workflows/zephyr.yml +++ b/.github/workflows/zephyr.yml @@ -14,14 +14,17 @@ jobs: strategy: fail-fast: false matrix: + # Using groups to avoid spamming the small results box with too + # many lines. Pay attention to COMMAS. IPC_platforms: [ - # IPC3 + # - IPC3 default apl cnl, icl jsl, tgl tgl-h, imx8 imx8x imx8m, + # - IPC4 default mtl, - # only tgl has IPC4 overlay file now + # Very few IPC3 platforms support IPC4 too. -i IPC4 tgl, ] zephyr_revision: [ From cd42fa37ab2274b5ef5fc5d3b605871b837c93c3 Mon Sep 17 00:00:00 2001 From: Serhiy Katsyuba Date: Wed, 21 Sep 2022 13:05:54 +0200 Subject: [PATCH 19/39] ipc4: block mixin pipeline if no active sink In case mixin pipeline is running but mixout pipeline is not -- do not discard source data but block source pipeline until at least one sink (mixout) started. A typical topology is to have mixin and mixout in separate pipelines. Often, mixout pipeline is started a few milliseconds later after mixin pipeline. In such case mixin pipeline should be blocked until mixout pipeline started to do not loose any audio periods. Signed-off-by: Serhiy Katsyuba --- src/audio/mixin_mixout.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/src/audio/mixin_mixout.c b/src/audio/mixin_mixout.c index 4a0a3643303f..0e886d9944ee 100644 --- a/src/audio/mixin_mixout.c +++ b/src/audio/mixin_mixout.c @@ -742,10 +742,7 @@ static int mixin_copy(struct comp_dev *dev) bytes_to_consume_from_source_buf = 0; if (source_avail_frames > 0) { if (active_mixout_cnt == 0) { - /* discard source data */ - comp_update_buffer_consume(source_c, - audio_stream_period_bytes(&source_c->stream, - source_avail_frames)); + /* block mixin pipeline until at least one mixout pipeline started */ buffer_release(source_c); return 0; } From 2334d7f37b2a6794f4bcdf5502ba4bf6c86353a2 Mon Sep 17 00:00:00 2001 From: "Joe.Cheng" Date: Thu, 15 Sep 2022 13:07:25 +0800 Subject: [PATCH 20/39] topology1:enable SOF EQ + DTS on AMD renoir Period has to be 1ms to avoid playback noise issue on Renoir when SOF EQ + DTS are both enabled. Signed-off-by: Joe.Cheng --- tools/topology/topology1/sof-rn-rt5682-rt1019.m4 | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/tools/topology/topology1/sof-rn-rt5682-rt1019.m4 b/tools/topology/topology1/sof-rn-rt5682-rt1019.m4 index 039572c084f6..caa1853c5b17 100644 --- a/tools/topology/topology1/sof-rn-rt5682-rt1019.m4 +++ b/tools/topology/topology1/sof-rn-rt5682-rt1019.m4 @@ -21,16 +21,16 @@ include(`platform/amd/acp.m4') # Playback pipeline 1 on PCM 0 using max 2 channels of s16le. # Schedule 96 frames per 2000us deadline on core 0 with priority 0 PIPELINE_PCM_ADD( -ifdef(`DTS', sof/pipe-dts-codec-playback.m4, sof/pipe-passthrough-playback.m4), +ifdef(`DTS', sof/pipe-eq-iir-dts-codec-playback.m4, sof/pipe-passthrough-playback.m4), 1, 0, 2, s16le, - 2000, 0, 0, + 1000, 0, 0, 48000, 48000, 48000) # playback DAI is ACPSP using 2 periods DAI_ADD(sof/pipe-dai-playback.m4, 1, ACPSP, 0, acp-headset-codec, PIPELINE_SOURCE_1, 2, s16le, - 2000, 0, 0, SCHEDULE_TIME_DOMAIN_DMA) + 1000, 0, 0, SCHEDULE_TIME_DOMAIN_DMA) DAI_CONFIG(ACPSP, 0, 0, acp-headset-codec, ACPSP_CONFIG(I2S, ACP_CLOCK(mclk, 49152000, codec_mclk_in), @@ -42,14 +42,14 @@ DAI_CONFIG(ACPSP, 0, 0, acp-headset-codec, # Capture pipeline 2 on PCM 0 using max 2 channels of s16le. PIPELINE_PCM_ADD(sof/pipe-passthrough-capture.m4, 2, 0, 2, s16le, - 2000, 0, 0, + 1000, 0, 0, 48000, 48000, 48000) # Capture DAI is ACPSP using 2 periods DAI_ADD(sof/pipe-dai-capture.m4, 2, ACPSP, 0, acp-headset-codec, PIPELINE_SINK_2, 2, s16le, - 2000, 0, 0, SCHEDULE_TIME_DOMAIN_DMA) + 1000, 0, 0, SCHEDULE_TIME_DOMAIN_DMA) # PCM id 0 PCM_DUPLEX_ADD(I2SSP, 0, PIPELINE_PCM_1, PIPELINE_PCM_2) @@ -57,13 +57,13 @@ PCM_DUPLEX_ADD(I2SSP, 0, PIPELINE_PCM_1, PIPELINE_PCM_2) # Capture pipeline 3 on PCM 1 using max 2 channels of s32le. PIPELINE_PCM_ADD(sof/pipe-passthrough-capture.m4, 3, 1, 2, s32le, - 2000, 0, 0, + 1000, 0, 0, 48000, 48000, 48000) DAI_ADD(sof/pipe-dai-capture.m4, 3, ACPDMIC, 0, acp-dmic-codec, PIPELINE_SINK_3, 2, s32le, - 2000, 0, 0, SCHEDULE_TIME_DOMAIN_DMA) + 1000, 0, 0, SCHEDULE_TIME_DOMAIN_DMA) dnl DAI_CONFIG(type, dai_index, link_id, name, acpdmic_config) DAI_CONFIG(ACPDMIC, 3, 2, acp-dmic-codec, From f0e234ed6e2bbc95f24aec6bbbf44424f46ac1c4 Mon Sep 17 00:00:00 2001 From: Muralidhar Reddy Date: Mon, 12 Sep 2022 19:17:15 +0530 Subject: [PATCH 21/39] topology1: CMakeLists: add ADL support for ES83x6 Added ADL support for ES83x6 on SSP1. Signed-off-by: Muralidhar Reddy --- tools/topology/topology1/CMakeLists.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tools/topology/topology1/CMakeLists.txt b/tools/topology/topology1/CMakeLists.txt index 871f70c0ac45..038cd4e0b3fe 100644 --- a/tools/topology/topology1/CMakeLists.txt +++ b/tools/topology/topology1/CMakeLists.txt @@ -248,6 +248,8 @@ set(TPLGS "sof-glk-es8336\;sof-tgl-es8336-dmic4ch-ssp1\;-DPLATFORM=tgl\;-DSSP_NUM=1\;-DCHANNELS=4" "sof-glk-es8336\;sof-tgl-es8336-dmic4ch-ssp2\;-DPLATFORM=tgl\;-DSSP_NUM=2\;-DCHANNELS=4" + "sof-glk-es8336\;sof-adl-es8336-ssp1\;-DPLATFORM=adl\;-DSSP_NUM=1\;-DCHANNELS=0" + "sof-imx8-nocodec\;sof-imx8-nocodec" "sof-imx8-cs42888\;sof-imx8-cs42888" "sof-imx8-nocodec-sai\;sof-imx8-nocodec-sai" From 1e4679c0344b68e10be407ab85152f760699362d Mon Sep 17 00:00:00 2001 From: Muralidhar Reddy Date: Mon, 12 Sep 2022 19:22:51 +0530 Subject: [PATCH 22/39] topology1: CMakeLists: add ADL support for ES83x6 & HDMI_In Capture Add ADL support for ES83x6 on SSP1, LT_HDMI_In capture on SSP0 & SSP2. Signed-off-by: Muralidhar Reddy --- tools/topology/topology1/CMakeLists.txt | 2 + .../platform/intel/intel-hdmi-ssp.m4 | 53 +++++++++++++++++++ tools/topology/topology1/sof-glk-es8336.m4 | 28 ++++++++++ 3 files changed, 83 insertions(+) create mode 100644 tools/topology/topology1/platform/intel/intel-hdmi-ssp.m4 diff --git a/tools/topology/topology1/CMakeLists.txt b/tools/topology/topology1/CMakeLists.txt index 038cd4e0b3fe..3de145bd9078 100644 --- a/tools/topology/topology1/CMakeLists.txt +++ b/tools/topology/topology1/CMakeLists.txt @@ -249,6 +249,8 @@ set(TPLGS "sof-glk-es8336\;sof-tgl-es8336-dmic4ch-ssp2\;-DPLATFORM=tgl\;-DSSP_NUM=2\;-DCHANNELS=4" "sof-glk-es8336\;sof-adl-es8336-ssp1\;-DPLATFORM=adl\;-DSSP_NUM=1\;-DCHANNELS=0" + #sof-adl-es8336-ssp1-hdmi-ssp02 supports es8336 codec along with 2xHDMI_over_SSP Capture's. + "sof-glk-es8336\;sof-adl-es8336-ssp1-hdmi-ssp02\;-DPLATFORM=adl\;-DSSP_NUM=1\;-DCHANNELS=0\;-DHDMI_1_SSP_NUM=0\;-DHDMI_2_SSP_NUM=2" "sof-imx8-nocodec\;sof-imx8-nocodec" "sof-imx8-cs42888\;sof-imx8-cs42888" diff --git a/tools/topology/topology1/platform/intel/intel-hdmi-ssp.m4 b/tools/topology/topology1/platform/intel/intel-hdmi-ssp.m4 new file mode 100644 index 000000000000..afe48b4adad3 --- /dev/null +++ b/tools/topology/topology1/platform/intel/intel-hdmi-ssp.m4 @@ -0,0 +1,53 @@ +# +# HDMI-SSP Audio Offload support +# + +include(`ssp.m4') + +define(`HDMI_SSP_NAME', concat(concat(`SSP', HDMI_SSP_NUM),`-HDMI')) +define(`HDMI_SSP_PCM_NAME', concat(concat(`HDMI-', HDMI_SSP_NUM),`-In')) + +# variable that need to be defined in upper m4 +ifdef(`HDMI_SSP_PIPELINE_CP_ID',`',`fatal_error(note: Need to define capture pcm id for ssp intel-hdmi-in +)') +ifdef(`HDMI_SSP_DAI_LINK_ID',`',`fatal_error(note: Need to define DAI link id for ssp intel-hdmi-in +)') +ifdef(`HDMI_SSP_PCM_ID',`',`fatal_error(note: Need to define pipeline PCM dev id for ssp intel-hdmi-in +)') + + +# Low Latency capture pipeline 4 on PCM HDMI_SSP_PCM_ID using max 2 channels of s32le. +# 1000us deadline with priority 0 on core 0 +PIPELINE_PCM_ADD(sof/pipe-low-latency-capture.m4, + HDMI_SSP_PIPELINE_CP_ID, HDMI_SSP_PCM_ID, 2, s32le, + 1000, 0, 0, + 48000, 48000, 48000) + + +# capture DAI is SSP using 2 periods +# Buffers use s32le format, 1000us deadline with priority 0 on core 0 +DAI_ADD(sof/pipe-dai-capture.m4, + HDMI_SSP_PIPELINE_CP_ID, SSP, HDMI_SSP_NUM, HDMI_SSP_NAME, + concat(`PIPELINE_SINK_', HDMI_SSP_PIPELINE_CP_ID), 2, s32le, + 1000, 0, 0, SCHEDULE_TIME_DOMAIN_DMA) + + +PCM_CAPTURE_ADD(HDMI_SSP_PCM_NAME, HDMI_SSP_PCM_ID, concat(`PIPELINE_PCM_', HDMI_SSP_PIPELINE_CP_ID)) + + +#BE configuration in slave mode +DAI_CONFIG(SSP, HDMI_SSP_NUM, HDMI_SSP_DAI_LINK_ID, HDMI_SSP_NAME, + SSP_CONFIG(I2S, SSP_CLOCK(mclk, 24576000, codec_mclk_in), + SSP_CLOCK(bclk, 3072000, codec_provider), + SSP_CLOCK(fsync, 48000, codec_provider), + SSP_TDM(2, 32, 3, 3), + SSP_CONFIG_DATA(SSP, HDMI_SSP_NUM, 32, 0))) + + +undefine(`HDMI_SSP_PIPELINE_CP_ID') +undefine(`HDMI_SSP_DAI_LINK_ID') +undefine(`HDMI_SSP_PCM_ID') dnl use fixed PCM_ID +undefine(`HDMI_SSP_NUM') +undefine(`HDMI_SSP_NAME') +undefine(`HDMI_SSP_PCM_NAME') + diff --git a/tools/topology/topology1/sof-glk-es8336.m4 b/tools/topology/topology1/sof-glk-es8336.m4 index 08fc45124ca5..181b150ef523 100644 --- a/tools/topology/topology1/sof-glk-es8336.m4 +++ b/tools/topology/topology1/sof-glk-es8336.m4 @@ -53,6 +53,24 @@ include(`platform/intel/intel-generic-dmic.m4') ' ) +# Add HDMI-SSP Audio Offload pass-through +ifdef(`HDMI_1_SSP_NUM', +` define(`HDMI_SSP_NUM', HDMI_1_SSP_NUM) + define(`HDMI_SSP_PIPELINE_CP_ID', `8') + define(`HDMI_SSP_DAI_LINK_ID', 6) + define(`HDMI_SSP_PCM_ID', `3') dnl use fixed PCM_ID + include(`platform/intel/intel-hdmi-ssp.m4') +' +) + +ifdef(`HDMI_2_SSP_NUM', +` define(`HDMI_SSP_NUM', HDMI_2_SSP_NUM) + define(`HDMI_SSP_PIPELINE_CP_ID', `9') + define(`HDMI_SSP_DAI_LINK_ID', 7) + define(`HDMI_SSP_PCM_ID', `4') dnl use fixed PCM_ID + include(`platform/intel/intel-hdmi-ssp.m4') +' +) DEBUG_START # @@ -68,6 +86,16 @@ ifelse(CHANNELS, `0', # PCM5 ----> volume (pipe 5) -----> iDisp1 (HDMI/DP playback, BE link 5) # PCM6 ----> Volume (pipe 6) -----> iDisp2 (HDMI/DP playback, BE link 6) # PCM7 ----> volume (pipe 7) -----> iDisp3 (HDMI/DP playback, BE link 7) +ifdef(`HDMI_1_SSP_NUM', +` +# PCM3 <---- volume <----- HDMI_1_SSP_NUM (lt6911) +' +) +ifdef(`HDMI_2_SSP_NUM', +` +# PCM4 <---- volume <----- HDMI_2_SSP_NUM (lt6911) +' +) # Low Latency playback pipeline 1 on PCM 0 using max 2 channels of s32le. # 1000us deadline with priority 0 on core 0 From 55454268328a3922e21abe0b02e58264dfb19796 Mon Sep 17 00:00:00 2001 From: Marc Herbert Date: Fri, 16 Sep 2022 23:45:20 +0000 Subject: [PATCH 23/39] xtensa-build-zephyr.py: don't complain about cmake_args when pristine Don't ask the user to delete the build directory when they are using the option that deletes the build directory. Signed-off-by: Marc Herbert --- scripts/xtensa-build-zephyr.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/xtensa-build-zephyr.py b/scripts/xtensa-build-zephyr.py index cccfd8980157..992491987150 100755 --- a/scripts/xtensa-build-zephyr.py +++ b/scripts/xtensa-build-zephyr.py @@ -478,7 +478,7 @@ def build_platforms(): abs_build_dir = pathlib.Path(west_top, platform_build_dir_name) if (pathlib.Path(abs_build_dir, "build.ninja").is_file() or pathlib.Path(abs_build_dir, "Makefile").is_file()): - if args.cmake_args: + if args.cmake_args and not args.pristine: print(args.cmake_args) raise RuntimeError("Some CMake arguments are ignored in incremental builds, " + f"you must delete {abs_build_dir} first") From 9e3835aa3ddd963da8e5b2057ac78f5f9c3132aa Mon Sep 17 00:00:00 2001 From: Marc Herbert Date: Sat, 17 Sep 2022 00:30:23 +0000 Subject: [PATCH 24/39] .github: extend yamllint line-length to 100 Also run on west.yml Signed-off-by: Marc Herbert --- .github/workflows/codestyle.yml | 7 ++++++- west.yml | 1 + 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/.github/workflows/codestyle.yml b/.github/workflows/codestyle.yml index ad8d299e1689..b09097b37348 100644 --- a/.github/workflows/codestyle.yml +++ b/.github/workflows/codestyle.yml @@ -59,4 +59,9 @@ jobs: - uses: actions/checkout@v2 - name: run yamllint - run: yamllint --strict .github/workflows/*.yml + # Quoting to please all parsers is hard. This indirection helps. + env: + yamllint_config: '{extends: default, rules: {line-length: {max: 100}}}' + run: yamllint -f parsable + -d "$yamllint_config" + --strict .github/workflows/*.yml *.yml diff --git a/west.yml b/west.yml index 3e99e8df9675..3a339aac6841 100644 --- a/west.yml +++ b/west.yml @@ -1,3 +1,4 @@ +--- # SOF west manifest manifest: version: "0.13" From b16f0cdbd2f61772bbeb6e84be852f37bd80f88a Mon Sep 17 00:00:00 2001 From: Marc Herbert Date: Fri, 16 Sep 2022 23:48:55 +0000 Subject: [PATCH 25/39] zephyr/docker-*.sh: pass REAL_CC through for sparse support Other minor fixes Signed-off-by: Marc Herbert --- zephyr/docker-build.sh | 11 +++++++++-- zephyr/docker-run.sh | 1 + 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/zephyr/docker-build.sh b/zephyr/docker-build.sh index e4280129760a..a612a9ac03f5 100755 --- a/zephyr/docker-build.sh +++ b/zephyr/docker-build.sh @@ -15,6 +15,10 @@ unset ZEPHYR_BASE # Make sure we're in the right place test -e ./sof/scripts/xtensa-build-zephyr.py +# See .github/workflows/zephyr.yml +PATH="$PATH":/opt/sparse/bin +command -v sparse || true +: REAL_CC="$REAL_CC" # See https://stackoverflow.com/questions/35291520/docker-and-userns-remap-how-to-manage-volume-permissions-to-share-data-betwee + many others exec_as_sof_uid() @@ -52,7 +56,7 @@ exec_as_sof_uid() # Double sudo to work around some funny restriction in # zephyr-build:/etc/sudoers: 'user' can do anything but... only as # root. - sudo sudo -u "$sof_user" "$0" "$@" + sudo sudo -u "$sof_user" REAL_CC="$REAL_CC" "$0" "$@" exit "$?" } @@ -76,4 +80,7 @@ if test -e .west || test -e zephyr; then else init_update='-u' fi -./sof/scripts/xtensa-build-zephyr.py $init_update --no-interactive "$@" + +# To investigate what went wrong enable the trailing comment. +# This cannot be enabled by default for automation reasons. +./sof/scripts/xtensa-build-zephyr.py $init_update --no-interactive "$@" # || /bin/bash diff --git a/zephyr/docker-run.sh b/zephyr/docker-run.sh index 1e42b0c12fc8..6d9a382f8c0c 100755 --- a/zephyr/docker-run.sh +++ b/zephyr/docker-run.sh @@ -53,6 +53,7 @@ main() docker run -i -v "$(west topdir)":/zep_workspace \ --workdir /zep_workspace \ $SOF_DOCKER_RUN \ + --env REAL_CC \ ghcr.io/zephyrproject-rtos/zephyr-build:latest \ "$@" } From 2da59da4f863d6f536cdb93f4c4abca142134f0d Mon Sep 17 00:00:00 2001 From: Marc Herbert Date: Fri, 16 Sep 2022 23:48:55 +0000 Subject: [PATCH 26/39] Add sparse_always_green to Github Actions The next step is to find how to extract the (too many?) errors. In the mean time this already makes sure the build process never bitrots and that it will always possible to use sparse. It also "documents" how to use sparse: just copy/paste the commands run by CI. Signed-off-by: Marc Herbert --- .github/workflows/zephyr.yml | 44 ++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/.github/workflows/zephyr.yml b/.github/workflows/zephyr.yml index 03d491284194..c06021f43f65 100644 --- a/.github/workflows/zephyr.yml +++ b/.github/workflows/zephyr.yml @@ -58,3 +58,47 @@ jobs: run: cd workspace && ./sof/zephyr/docker-run.sh ./sof/zephyr/docker-build.sh --cmake-args=-DEXTRA_CFLAGS=-Werror --cmake-args=--warn-uninitialized ${{ matrix.IPC_platforms }} + + + # As of sparse commit ce1a6720f69e / Sept 2022, the exit status of sparse.c is an + # unusable mess and always zero in practice. "Send patches"? So for now the only purpose + # of this check is to keep sparse _usable_ and demo how to use it but not to catch any + # regression. + # + # The only, undocumented way to make sparse return a non-zero exit status is to use its + # -Wsparse-error option; see check_symbols() code in sparse.c. Without -Wsparse-error, + # sparse.c always returns zero no matter how many warnings and errors it printed. BUT of + # course -Wsparse-error has another, intended and expected effect documented in "man + # sparse": promote all our (very many) warnings into errors. Which means we cannot use + # -Wsparse-error yet, otherwise it would be "always red". + # + # Note sparse does not support promoting individual warning types to errors either. + sparse_always_green: + runs-on: ubuntu-22.04 + + strategy: + fail-fast: false + matrix: + platforms: [ + {platform: tgl, + real_cc: xtensa-intel_s1000_zephyr-elf/bin/xtensa-intel_s1000_zephyr-elf-gcc}, + ] + + steps: + - uses: actions/checkout@v2 + # From time to time this will catch a git tag and change SOF_VERSION + with: + fetch-depth: 10 + path: ./workspace/sof + + - name: west clones + run: pip3 install west && cd workspace/sof/ && west init -l && + west update --narrow --fetch-opt=--depth=5 + + - name: build + run: cd workspace && + ZSDK=/opt/toolchains/zephyr-sdk-0.15.0; + _RCC=${{ matrix.platforms.real_cc }}; + REAL_CC="$ZSDK/$_RCC" ./sof/zephyr/docker-run.sh + ./sof/zephyr/docker-build.sh ${{ matrix.platforms.platform }} + --cmake-args=-DSPARSE=y # --cmake-args=-DEXTRA_CFLAGS=-Wsparse-error From 2159c25f279b1a00434cfa8d224053a692ddd893 Mon Sep 17 00:00:00 2001 From: Marc Herbert Date: Tue, 20 Sep 2022 17:48:53 +0000 Subject: [PATCH 27/39] scripts: add link to CMake envvars FAQ next to XTENSA_SYSTEM definition Environment variables like XTENSA_SYSTEM are an absolute CMake pain. Add a link to the CMake FAQ and a one-line description why. Signed-off-by: Marc Herbert --- scripts/xtensa-build-all.sh | 2 ++ scripts/xtensa-build-zephyr.py | 4 +++- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/scripts/xtensa-build-all.sh b/scripts/xtensa-build-all.sh index 981ad81ff2d7..f12bf197be24 100755 --- a/scripts/xtensa-build-all.sh +++ b/scripts/xtensa-build-all.sh @@ -392,6 +392,8 @@ do then TOOLCHAIN=xt ROOT="$XTENSA_BUILDS_DIR/$XTENSA_CORE/xtensa-elf" + # CMake cannot set (evil) build-time environment variables at configure time: +# https://gitlab.kitware.com/cmake/community/-/wikis/FAQ#how-can-i-get-or-set-environment-variables export XTENSA_SYSTEM=$XTENSA_BUILDS_DIR/$XTENSA_CORE/config printf 'XTENSA_SYSTEM=%s\n' "${XTENSA_SYSTEM}" PATH=$XTENSA_TOOLS_DIR/XtensaTools/bin:$OLDPATH diff --git a/scripts/xtensa-build-zephyr.py b/scripts/xtensa-build-zephyr.py index 992491987150..256158e2fdfb 100755 --- a/scripts/xtensa-build-zephyr.py +++ b/scripts/xtensa-build-zephyr.py @@ -464,7 +464,9 @@ def build_platforms(): print(f"XTENSA_TOOLCHAIN_PATH={XTENSA_TOOLCHAIN_PATH}") print(f"TOOLCHAIN_VER={TOOLCHAIN_VER}") - # set variables expected by xcc toolchain + # Set variables expected by xcc toolchain. CMake cannot set (evil) build-time + # environment variables at configure time: + # https://gitlab.kitware.com/cmake/community/-/wikis/FAQ#how-can-i-get-or-set-environment-variables XTENSA_BUILDS_DIR=str(pathlib.Path(xtensa_tools_root_dir, "install", "builds", TOOLCHAIN_VER).absolute()) XTENSA_SYSTEM = str(pathlib.Path(XTENSA_BUILDS_DIR, XTENSA_CORE, "config").absolute()) From bbd988a2b75aeea318bad56002d568c39ffba8fb Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Thu, 22 Sep 2022 16:44:11 +0300 Subject: [PATCH 28/39] west: update to newer rimage baseline tgl-h zephyr build is broken due to outdated rimage revision. Signed-off-by: Peter Ujfalusi --- west.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/west.yml b/west.yml index 3a339aac6841..bba679b9601d 100644 --- a/west.yml +++ b/west.yml @@ -16,7 +16,7 @@ manifest: - name: rimage repo-path: rimage path: sof/rimage - revision: 02abc5d342a3ee6965bdc933ea1439d85d0256da + revision: 542924d70c1715671ad8213440f01dc6dadb52e4 - name: tomlc99 repo-path: tomlc99 From 5c28eda7515f748fcf472521fe0717f957d808d6 Mon Sep 17 00:00:00 2001 From: Jyri Sarha Date: Tue, 20 Sep 2022 21:40:20 +0300 Subject: [PATCH 29/39] probe: Drop old IPC3 style probe DMA framing Drop IPC3 probe DMA framing and use IPC4 framing for IPC3 mode too. This change simplifies the code quite a bit. After this change both the SOF firmware and sof-probe demux tool should be updated at the same time. Signed-off-by: Jyri Sarha --- src/include/ipc/probe.h | 2 + src/include/ipc/probe_dma_frame.h | 83 +++++++++++++++++++++++++++++++ src/include/ipc3/probe.h | 73 --------------------------- src/include/ipc4/probe.h | 72 --------------------------- src/probe/probe.c | 15 ++---- tools/probes/probes_main.c | 48 ++++++++++-------- 6 files changed, 117 insertions(+), 176 deletions(-) create mode 100644 src/include/ipc/probe_dma_frame.h diff --git a/src/include/ipc/probe.h b/src/include/ipc/probe.h index 3c77dbc55ae1..3f54f7a12594 100644 --- a/src/include/ipc/probe.h +++ b/src/include/ipc/probe.h @@ -3,6 +3,8 @@ * Copyright(c) 2022 Intel Corporation. All rights reserved. */ +#include + #if CONFIG_IPC_MAJOR_4 #include #else diff --git a/src/include/ipc/probe_dma_frame.h b/src/include/ipc/probe_dma_frame.h new file mode 100644 index 000000000000..0628704fdcef --- /dev/null +++ b/src/include/ipc/probe_dma_frame.h @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * + * Copyright(c) 2022 Intel Corporation. All rights reserved. + */ + +#ifndef __IPC_PROBE_DMA_FRAME_H__ +#define __IPC_PROBE_DMA_FRAME_H__ + +#include + +/** + * Header for data packets sent via compressed PCM from extraction probes + */ +struct probe_data_packet { + uint32_t sync_word; /**< PROBE_EXTRACT_SYNC_WORD */ + uint32_t buffer_id; /**< Buffer ID from which data was extracted */ + uint32_t format; /**< Encoded data format */ + uint32_t timestamp_low; /**< Low 32 bits of timestamp in us */ + uint32_t timestamp_high; /**< High 32 bits of timestamp in us */ + uint32_t data_size_bytes; /**< Size of following audio data */ + uint8_t data[]; /**< Audio data extracted from buffer */ +} __attribute__((packed, aligned(4))); + +#define PROBE_EXTRACT_SYNC_WORD 0xBABEBEBA + +/** + * \brief Definitions of shifts and masks for format encoding in probe + * extraction stream + * + * Audio format from extraction probes is encoded as 32 bit value. Following + * graphic explains encoding. + * + * A|BBBB|CCCC|DDDD|EEEEE|FF|GG|H|I|J|XXXXXXX + * A - 1 bit - Specifies Type Encoding - 1 for Standard encoding + * B - 4 bits - Specify Standard Type - 0 for Audio + * C - 4 bits - Specify Audio format - 0 for PCM + * D - 4 bits - Specify Sample Rate - value enumerating standard sample rates: + * 8000 Hz = 0x0 + * 11025 Hz = 0x1 + * 12000 Hz = 0x2 + * 16000 Hz = 0x3 + * 22050 Hz = 0x4 + * 24000 Hz = 0x5 + * 32000 Hz = 0x6 + * 44100 Hz = 0x7 + * 48000 Hz = 0x8 + * 64000 Hz = 0x9 + * 88200 Hz = 0xA + * 96000 Hz = 0xB + * 128000 Hz = 0xC + * 176400 Hz = 0xD + * 192000 Hz = 0xE + * none of the above = 0xF + * E - 5 bits - Specify Number of Channels minus 1 + * F - 2 bits - Specify Sample Size, number of valid sample bytes minus 1 + * G - 2 bits - Specify Container Size, number of container bytes minus 1 + * H - 1 bit - Specifies Sample Format - 0 for Integer, 1 for Floating point + * I - 1 bit - Specifies Sample Endianness - 0 for LE + * J - 1 bit - Specifies Interleaving - 1 for Sample Interleaving + */ +#define PROBE_SHIFT_FMT_TYPE 31 +#define PROBE_SHIFT_STANDARD_TYPE 27 +#define PROBE_SHIFT_AUDIO_FMT 23 +#define PROBE_SHIFT_SAMPLE_RATE 19 +#define PROBE_SHIFT_NB_CHANNELS 14 +#define PROBE_SHIFT_SAMPLE_SIZE 12 +#define PROBE_SHIFT_CONTAINER_SIZE 10 +#define PROBE_SHIFT_SAMPLE_FMT 9 +#define PROBE_SHIFT_SAMPLE_END 8 +#define PROBE_SHIFT_INTERLEAVING_ST 7 + +#define PROBE_MASK_FMT_TYPE MASK(31, 31) +#define PROBE_MASK_STANDARD_TYPE MASK(30, 27) +#define PROBE_MASK_AUDIO_FMT MASK(26, 23) +#define PROBE_MASK_SAMPLE_RATE MASK(22, 19) +#define PROBE_MASK_NB_CHANNELS MASK(18, 14) +#define PROBE_MASK_SAMPLE_SIZE MASK(13, 12) +#define PROBE_MASK_CONTAINER_SIZE MASK(11, 10) +#define PROBE_MASK_SAMPLE_FMT MASK(9, 9) +#define PROBE_MASK_SAMPLE_END MASK(8, 8) +#define PROBE_MASK_INTERLEAVING_ST MASK(7, 7) + +#endif diff --git a/src/include/ipc3/probe.h b/src/include/ipc3/probe.h index 9e1a80fe9430..b603f77a9cdd 100644 --- a/src/include/ipc3/probe.h +++ b/src/include/ipc3/probe.h @@ -31,79 +31,6 @@ #define PROBE_PURPOSE_LOGGING 0x3 #define PROBE_PURPOSE_TRACING 0x4 -#define PROBE_EXTRACT_SYNC_WORD 0xBABEBEBA - -/** - * \brief Definitions of shifts and masks for format encoding in probe - * extraction stream - * - * Audio format from extraction probes is encoded as 32 bit value. Following - * graphic explains encoding. - * - * A|BBBB|CCCC|DDDD|EEEEE|FF|GG|H|I|J|XXXXXXX - * A - 1 bit - Specifies Type Encoding - 1 for Standard encoding - * B - 4 bits - Specify Standard Type - 0 for Audio - * C - 4 bits - Specify Audio format - 0 for PCM - * D - 4 bits - Specify Sample Rate - value enumerating standard sample rates: - * 8000 Hz = 0x0 - * 11025 Hz = 0x1 - * 12000 Hz = 0x2 - * 16000 Hz = 0x3 - * 22050 Hz = 0x4 - * 24000 Hz = 0x5 - * 32000 Hz = 0x6 - * 44100 Hz = 0x7 - * 48000 Hz = 0x8 - * 64000 Hz = 0x9 - * 88200 Hz = 0xA - * 96000 Hz = 0xB - * 128000 Hz = 0xC - * 176400 Hz = 0xD - * 192000 Hz = 0xE - * none of the above = 0xF - * E - 5 bits - Specify Number of Channels minus 1 - * F - 2 bits - Specify Sample Size, number of valid sample bytes minus 1 - * G - 2 bits - Specify Container Size, number of container bytes minus 1 - * H - 1 bit - Specifies Sample Format - 0 for Integer, 1 for Floating point - * I - 1 bit - Specifies Sample Endianness - 0 for LE - * J - 1 bit - Specifies Interleaving - 1 for Sample Interleaving - */ -#define PROBE_SHIFT_FMT_TYPE 31 -#define PROBE_SHIFT_STANDARD_TYPE 27 -#define PROBE_SHIFT_AUDIO_FMT 23 -#define PROBE_SHIFT_SAMPLE_RATE 19 -#define PROBE_SHIFT_NB_CHANNELS 14 -#define PROBE_SHIFT_SAMPLE_SIZE 12 -#define PROBE_SHIFT_CONTAINER_SIZE 10 -#define PROBE_SHIFT_SAMPLE_FMT 9 -#define PROBE_SHIFT_SAMPLE_END 8 -#define PROBE_SHIFT_INTERLEAVING_ST 7 - -#define PROBE_MASK_FMT_TYPE MASK(31, 31) -#define PROBE_MASK_STANDARD_TYPE MASK(30, 27) -#define PROBE_MASK_AUDIO_FMT MASK(26, 23) -#define PROBE_MASK_SAMPLE_RATE MASK(22, 19) -#define PROBE_MASK_NB_CHANNELS MASK(18, 14) -#define PROBE_MASK_SAMPLE_SIZE MASK(13, 12) -#define PROBE_MASK_CONTAINER_SIZE MASK(11, 10) -#define PROBE_MASK_SAMPLE_FMT MASK(9, 9) -#define PROBE_MASK_SAMPLE_END MASK(8, 8) -#define PROBE_MASK_INTERLEAVING_ST MASK(7, 7) - -/** - * Header for data packets sent via compressed PCM from extraction probes - */ -struct probe_data_packet { - uint32_t sync_word; /**< PROBE_EXTRACT_SYNC_WORD */ - uint32_t buffer_id; /**< Buffer ID from which data was extracted */ - uint32_t format; /**< Encoded data format */ - uint32_t timestamp_low; /**< Low 32 bits of timestamp in us */ - uint32_t timestamp_high; /**< High 32 bits of timestamp in us */ - uint32_t checksum; /**< CRC32 of header and payload */ - uint32_t data_size_bytes; /**< Size of following audio data */ - uint32_t data[]; /**< Audio data extracted from buffer */ -} __attribute__((packed, aligned(4))); - /** * Description of probe dma */ diff --git a/src/include/ipc4/probe.h b/src/include/ipc4/probe.h index 77c3849b9e4a..aec424d41539 100644 --- a/src/include/ipc4/probe.h +++ b/src/include/ipc4/probe.h @@ -47,78 +47,6 @@ #define IPC4_PROBE_MODULE_PROBE_POINTS_ADD 3 #define IPC4_PROBE_MODULE_DISCONNECT_PROBE_POINTS 4 -#define PROBE_EXTRACT_SYNC_WORD 0xBABEBEBA - -/** - * \brief Definitions of shifts and masks for format encoding in probe - * extraction stream - * - * Audio format from extraction probes is encoded as 32 bit value. Following - * graphic explains encoding. - * - * A|BBBB|CCCC|DDDD|EEEEE|FF|GG|H|I|J|XXXXXXX - * A - 1 bit - Specifies Type Encoding - 1 for Standard encoding - * B - 4 bits - Specify Standard Type - 0 for Audio - * C - 4 bits - Specify Audio format - 0 for PCM - * D - 4 bits - Specify Sample Rate - value enumerating standard sample rates: - * 8000 Hz = 0x0 - * 11025 Hz = 0x1 - * 12000 Hz = 0x2 - * 16000 Hz = 0x3 - * 22050 Hz = 0x4 - * 24000 Hz = 0x5 - * 32000 Hz = 0x6 - * 44100 Hz = 0x7 - * 48000 Hz = 0x8 - * 64000 Hz = 0x9 - * 88200 Hz = 0xA - * 96000 Hz = 0xB - * 128000 Hz = 0xC - * 176400 Hz = 0xD - * 192000 Hz = 0xE - * none of the above = 0xF - * E - 5 bits - Specify Number of Channels minus 1 - * F - 2 bits - Specify Sample Size, number of valid sample bytes minus 1 - * G - 2 bits - Specify Container Size, number of container bytes minus 1 - * H - 1 bit - Specifies Sample Format - 0 for Integer, 1 for Floating point - * I - 1 bit - Specifies Sample Endianness - 0 for LE - * J - 1 bit - Specifies Interleaving - 1 for Sample Interleaving - */ -#define PROBE_SHIFT_FMT_TYPE 31 -#define PROBE_SHIFT_STANDARD_TYPE 27 -#define PROBE_SHIFT_AUDIO_FMT 23 -#define PROBE_SHIFT_SAMPLE_RATE 19 -#define PROBE_SHIFT_NB_CHANNELS 14 -#define PROBE_SHIFT_SAMPLE_SIZE 12 -#define PROBE_SHIFT_CONTAINER_SIZE 10 -#define PROBE_SHIFT_SAMPLE_FMT 9 -#define PROBE_SHIFT_SAMPLE_END 8 -#define PROBE_SHIFT_INTERLEAVING_ST 7 - -#define PROBE_MASK_FMT_TYPE MASK(31, 31) -#define PROBE_MASK_STANDARD_TYPE MASK(30, 27) -#define PROBE_MASK_AUDIO_FMT MASK(26, 23) -#define PROBE_MASK_SAMPLE_RATE MASK(22, 19) -#define PROBE_MASK_NB_CHANNELS MASK(18, 14) -#define PROBE_MASK_SAMPLE_SIZE MASK(13, 12) -#define PROBE_MASK_CONTAINER_SIZE MASK(11, 10) -#define PROBE_MASK_SAMPLE_FMT MASK(9, 9) -#define PROBE_MASK_SAMPLE_END MASK(8, 8) -#define PROBE_MASK_INTERLEAVING_ST MASK(7, 7) - -/** - * Header for data packets sent via compressed PCM from extraction probes - */ -struct probe_data_packet { - uint32_t sync_word; /**< PROBE_EXTRACT_SYNC_WORD */ - uint32_t buffer_id; /**< Buffer ID from which data was extracted */ - uint32_t format; /**< Encoded data format */ - uint32_t timestamp_low; /**< Low 32 bits of timestamp in us */ - uint32_t timestamp_high; /**< High 32 bits of timestamp in us */ - uint32_t data_size_bytes; /**< Size of following audio data */ - uint32_t data[]; /**< Audio data extracted from buffer */ -} __attribute__((packed, aligned(4))); - /** * Description of probe dma */ diff --git a/src/probe/probe.c b/src/probe/probe.c index 79fc50ca21f8..7fb022735b6d 100644 --- a/src/probe/probe.c +++ b/src/probe/probe.c @@ -627,7 +627,7 @@ static int probe_gen_header(uint32_t buffer_id, uint32_t size, header->timestamp_low = (uint32_t)timestamp; header->timestamp_high = (uint32_t)(timestamp >> 32); header->data_size_bytes = size; -#if CONFIG_IPC_MAJOR_4 + /* calc checksum to check validation by probe parse app */ *checksum = header->sync_word + header->buffer_id + @@ -635,11 +635,6 @@ static int probe_gen_header(uint32_t buffer_id, uint32_t size, header->timestamp_high + header->timestamp_low + header->data_size_bytes; -#else - /* calc crc to check validation by probe parse app */ - header->checksum = 0; - header->checksum = crc32(0, header, sizeof(*header)); -#endif dcache_writeback_region((__sparse_force void __sparse_cache *)header, sizeof(*header)); @@ -775,12 +770,12 @@ static void probe_logging_hook(uint8_t *buffer, size_t length) buffer, length); if (ret < 0) return; -#if CONFIG_IPC_MAJOR_4 + ret = copy_to_pbuffer(&_probe->ext_dma.dmapb, &checksum, sizeof(checksum)); if (ret < 0) return; -#endif + kick_probe_task(_probe); } #endif @@ -857,12 +852,12 @@ static void probe_cb_produce(void *arg, enum notify_id type, void *data) if (ret < 0) goto err; } -#if CONFIG_IPC_MAJOR_4 + ret = copy_to_pbuffer(&_probe->ext_dma.dmapb, &checksum, sizeof(checksum)); if (ret < 0) goto err; -#endif + kick_probe_task(_probe); } else { /* search for DMA used by this probe point */ diff --git a/tools/probes/probes_main.c b/tools/probes/probes_main.c index 4114f5d86be0..c02ea800ccc2 100644 --- a/tools/probes/probes_main.c +++ b/tools/probes/probes_main.c @@ -13,10 +13,6 @@ * */ -#include -#include -#include "wave.h" - #include #include #include @@ -28,6 +24,11 @@ #include #include +#include +#include + +#include "wave.h" + #define APP_NAME "sof-probes" #define PACKET_MAX_SIZE 4096 /**< Size limit for probe data packet */ @@ -182,39 +183,44 @@ void finalize_wave_files(struct wave_files *files) } } -int validate_data_packet(struct probe_data_packet *data_packet) +int validate_data_packet(struct probe_data_packet *packet) { - uint32_t received_crc; - uint32_t calc_crc; - - received_crc = data_packet->checksum; - data_packet->checksum = 0; - calc_crc = crc32(0, (char *)data_packet, sizeof(*data_packet)); - - if (received_crc == calc_crc) { - return 0; - } else { - fprintf(stderr, "error: data packet for buffer %d is not valid: crc32: %d/%d\n", - data_packet->buffer_id, calc_crc, received_crc); + uint64_t *checksump; + uint64_t sum; + + sum = (uint32_t) (packet->sync_word + + packet->buffer_id + + packet->format + + packet->timestamp_high + + packet->timestamp_low + + packet->data_size_bytes); + + checksump = (uint64_t *) (packet->data + packet->data_size_bytes); + + if (sum != *checksump) { + fprintf(stderr, "Checksum error 0x%016lx != 0x%016lx\n", sum, *checksump); return -EINVAL; } + + return 0; } int process_sync(struct probe_data_packet *packet, uint8_t **w_ptr, uint32_t *total_data_to_copy) { struct probe_data_packet *temp_packet; - /* request to copy data_size from probe packet */ - *total_data_to_copy = packet->data_size_bytes; + /* request to copy data_size from probe packet and 64-bit checksum */ + *total_data_to_copy = packet->data_size_bytes + sizeof(uint64_t); - if (packet->data_size_bytes > PACKET_MAX_SIZE) { + if (*total_data_to_copy > PACKET_MAX_SIZE) { temp_packet = realloc(packet, - sizeof(struct probe_data_packet) + packet->data_size_bytes); + sizeof(struct probe_data_packet) + *total_data_to_copy); if (!temp_packet) return -ENOMEM; } *w_ptr = (uint8_t *)&packet->data; + return 0; } From ad4af3785fb40b10d9ea3328b52b68731745c8d6 Mon Sep 17 00:00:00 2001 From: Jyri Sarha Date: Wed, 21 Sep 2022 17:24:47 +0300 Subject: [PATCH 30/39] tools/probe: Several fixes and restructuring for demuxcode Several fixes and restructuring for demuxcode to make it work with sub 32-bit word granularity. Signed-off-by: Jyri Sarha --- tools/probes/probes_main.c | 77 +++++++++++++++++++++----------------- 1 file changed, 43 insertions(+), 34 deletions(-) diff --git a/tools/probes/probes_main.c b/tools/probes/probes_main.c index c02ea800ccc2..6d56aef59197 100644 --- a/tools/probes/probes_main.c +++ b/tools/probes/probes_main.c @@ -244,7 +244,7 @@ void parse_data(char *file_in) uint32_t total_data_to_copy = 0; uint32_t data_to_copy = 0; uint8_t *w_ptr; - int i, j, file; + int start, i, j, file; enum p_state state = READY; @@ -267,45 +267,39 @@ void parse_data(char *file_in) memset(&data, 0, DATA_READ_LIMIT); memset(&files, 0, sizeof(struct wave_files) * FILES_LIMIT); - /* data read loop to process DATA_READ_LIMIT bytes at each iteration */ + start = 0; + /* Data read loop to process DATA_READ_LIMIT bytes at each + * iteration. If there is under sizeof(sync_word) bytes left + * in the buffer when a new frame is searched for, the remaining + * bytes are moved to the beginning of the buffer for the next + * iteration. + */ do { - i = fread(&data, 1, DATA_READ_LIMIT, fd_in); + i = fread(&data[start], 1, DATA_READ_LIMIT - start, fd_in); + i += start; + j = 0; + start = 0; /* processing all loaded bytes */ - for (j = 0; j < i; j++) { - /* check for SYNC */ - if (sync_word_at(&data[j], i - j)) { - if (state != READY) { - fprintf(stderr, "error: wrong state %d, err %d\n", - state, errno); - free(packet); - exit(0); - } - memset(packet, 0, PACKET_MAX_SIZE); - /* request to copy full data packet */ - total_data_to_copy = sizeof(struct probe_data_packet); - w_ptr = (uint8_t *)packet; - state = SYNC; - } - /* data copying section */ - if (total_data_to_copy > 0) { - /* check if there is enough bytes loaded */ - /* or copy partially if not */ - if (j + total_data_to_copy > i) { - data_to_copy = i - j; - total_data_to_copy -= data_to_copy; - } else { - data_to_copy = total_data_to_copy; - total_data_to_copy = 0; - } - memcpy(w_ptr, data + j, data_to_copy); - w_ptr += data_to_copy; - j += data_to_copy - 1; - } - + while (j < i) { if (total_data_to_copy == 0) { switch (state) { case READY: + /* check for SYNC */ + if (i - j < sizeof(packet->sync_word)) { + start = i - j; + memmove(&data[0], &data[j], start); + j += start; + } else if (sync_word_at(&data[j], i - j)) { + memset(packet, 0, PACKET_MAX_SIZE); + /* request to copy full data packet */ + total_data_to_copy = + sizeof(struct probe_data_packet); + w_ptr = (uint8_t *)packet; + state = SYNC; + } else { + j++; + } break; case SYNC: /* SYNC -> CHECK */ @@ -343,6 +337,21 @@ void parse_data(char *file_in) break; } } + /* data copying section */ + if (total_data_to_copy > 0) { + /* check if there is enough bytes loaded */ + /* or copy partially if not */ + if (j + total_data_to_copy > i) { + data_to_copy = i - j; + total_data_to_copy -= data_to_copy; + } else { + data_to_copy = total_data_to_copy; + total_data_to_copy = 0; + } + memcpy(w_ptr, data + j, data_to_copy); + w_ptr += data_to_copy; + j += data_to_copy; + } } } while (i > 0); From f99d272adbbc1b482b8a58dbdd602c7e2897b45e Mon Sep 17 00:00:00 2001 From: Jyri Sarha Date: Wed, 21 Sep 2022 18:29:47 +0300 Subject: [PATCH 31/39] tools/probe: Fix realloc() usage Realloc may change the location of memory and the code should anticipate it. Signed-off-by: Jyri Sarha --- tools/probes/probes_main.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/tools/probes/probes_main.c b/tools/probes/probes_main.c index 6d56aef59197..323c31db195b 100644 --- a/tools/probes/probes_main.c +++ b/tools/probes/probes_main.c @@ -205,21 +205,23 @@ int validate_data_packet(struct probe_data_packet *packet) return 0; } -int process_sync(struct probe_data_packet *packet, uint8_t **w_ptr, uint32_t *total_data_to_copy) +int process_sync(struct probe_data_packet **packet, uint8_t **w_ptr, uint32_t *total_data_to_copy) { struct probe_data_packet *temp_packet; /* request to copy data_size from probe packet and 64-bit checksum */ - *total_data_to_copy = packet->data_size_bytes + sizeof(uint64_t); + *total_data_to_copy = (*packet)->data_size_bytes + sizeof(uint64_t); if (*total_data_to_copy > PACKET_MAX_SIZE) { temp_packet = realloc(packet, sizeof(struct probe_data_packet) + *total_data_to_copy); if (!temp_packet) return -ENOMEM; + + *packet = temp_packet; } - *w_ptr = (uint8_t *)&packet->data; + *w_ptr = (uint8_t *)&(*packet)->data; return 0; } @@ -303,7 +305,7 @@ void parse_data(char *file_in) break; case SYNC: /* SYNC -> CHECK */ - if (process_sync(packet, &w_ptr, &total_data_to_copy) < 0) { + if (process_sync(&packet, &w_ptr, &total_data_to_copy) < 0) { fprintf(stderr, "OOM, quitting\n"); goto err; } From 6efaa375ebba516cfa30b53567f15b7f5410c084 Mon Sep 17 00:00:00 2001 From: Jyri Sarha Date: Fri, 23 Sep 2022 09:26:05 +0300 Subject: [PATCH 32/39] tools/probe: Remove unused write_data() function Signed-off-by: Jyri Sarha --- tools/probes/probes_main.c | 17 ----------------- 1 file changed, 17 deletions(-) diff --git a/tools/probes/probes_main.c b/tools/probes/probes_main.c index 323c31db195b..e73071daa86a 100644 --- a/tools/probes/probes_main.c +++ b/tools/probes/probes_main.c @@ -63,23 +63,6 @@ static void usage(void) exit(0); } -int write_data(char *path, char *data) -{ - FILE *fd; - - fd = fopen(path, "w"); - if (!fd) { - fprintf(stderr, "error: unable to open file %s, error %d\n", - path, errno); - return errno; - } - - fprintf(fd, "%s", data); - fclose(fd); - - return 0; -} - int get_buffer_file(struct wave_files *files, uint32_t buffer_id) { int i; From 7c19538396168cb78fc7a470b4cdc90d0584338c Mon Sep 17 00:00:00 2001 From: Jyri Sarha Date: Fri, 23 Sep 2022 16:11:47 +0300 Subject: [PATCH 33/39] tools/probe: Drop sync_word_at(), a simple == condition will do The sync_word_at() only checks for two things, if the len parameter is greater than sizeof(uint32_t) and if the memory pointed p parameter holds PROBE_EXTRACT_SYNC_WORD value. Now that the available bytes is checked just before sync_word_at() call, the whole function starts to look a bit pointless. Signed-off-by: Jyri Sarha --- tools/probes/probes_main.c | 14 ++------------ 1 file changed, 2 insertions(+), 12 deletions(-) diff --git a/tools/probes/probes_main.c b/tools/probes/probes_main.c index e73071daa86a..2ca2ee995305 100644 --- a/tools/probes/probes_main.c +++ b/tools/probes/probes_main.c @@ -209,17 +209,6 @@ int process_sync(struct probe_data_packet **packet, uint8_t **w_ptr, uint32_t *t return 0; } -static bool sync_word_at(uint8_t *buf, size_t len) -{ - if (len < sizeof(uint32_t)) - return false; - - if (*((uint32_t *)buf) == PROBE_EXTRACT_SYNC_WORD) - return true; - - return false; -} - void parse_data(char *file_in) { FILE *fd_in; @@ -275,7 +264,8 @@ void parse_data(char *file_in) start = i - j; memmove(&data[0], &data[j], start); j += start; - } else if (sync_word_at(&data[j], i - j)) { + } else if (*((uint32_t *)&data[j]) == + PROBE_EXTRACT_SYNC_WORD) { memset(packet, 0, PACKET_MAX_SIZE); /* request to copy full data packet */ total_data_to_copy = From c4cfdbf1cd5cf01ea7f78dd23901c4d2fa84c0da Mon Sep 17 00:00:00 2001 From: Jyri Sarha Date: Fri, 23 Sep 2022 16:13:44 +0300 Subject: [PATCH 34/39] tools/probe: Move data_to_copy variable down in scope Signed-off-by: Jyri Sarha --- tools/probes/probes_main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/probes/probes_main.c b/tools/probes/probes_main.c index 2ca2ee995305..9aedc3f6fcfc 100644 --- a/tools/probes/probes_main.c +++ b/tools/probes/probes_main.c @@ -216,7 +216,6 @@ void parse_data(char *file_in) struct probe_data_packet *packet; uint8_t data[DATA_READ_LIMIT]; uint32_t total_data_to_copy = 0; - uint32_t data_to_copy = 0; uint8_t *w_ptr; int start, i, j, file; @@ -314,6 +313,7 @@ void parse_data(char *file_in) } /* data copying section */ if (total_data_to_copy > 0) { + uint32_t data_to_copy; /* check if there is enough bytes loaded */ /* or copy partially if not */ if (j + total_data_to_copy > i) { From deb4d63b2d4d8b3b2e794ef092d2be63b9a27b5d Mon Sep 17 00:00:00 2001 From: Jyri Sarha Date: Tue, 27 Sep 2022 00:22:16 +0300 Subject: [PATCH 35/39] tools/probe: Fix realloc condition The allocated packet should accommodate the header, the data, and the checksum. The header size was missing from the condition from the beginning, even if its there in realloc parameter. The bug should be harmless waste of cycles thou. Signed-off-by: Jyri Sarha --- tools/probes/probes_main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/probes/probes_main.c b/tools/probes/probes_main.c index 9aedc3f6fcfc..db8ab73a3a21 100644 --- a/tools/probes/probes_main.c +++ b/tools/probes/probes_main.c @@ -195,7 +195,7 @@ int process_sync(struct probe_data_packet **packet, uint8_t **w_ptr, uint32_t *t /* request to copy data_size from probe packet and 64-bit checksum */ *total_data_to_copy = (*packet)->data_size_bytes + sizeof(uint64_t); - if (*total_data_to_copy > PACKET_MAX_SIZE) { + if (sizeof(struct probe_data_packet) + *total_data_to_copy > PACKET_MAX_SIZE) { temp_packet = realloc(packet, sizeof(struct probe_data_packet) + *total_data_to_copy); if (!temp_packet) From 1da1a052e4c02a3aa34de564a037aa5fe360db1b Mon Sep 17 00:00:00 2001 From: Daniel Baluta Date: Mon, 26 Sep 2022 11:42:19 +0300 Subject: [PATCH 36/39] module: cadence: Support params for more than 1 codec We want to be able to play different compress stream types using the same topology: e.g $ cplay -I MP3 -d 0 -c 0 sample.mp3 [ end of playback ] $ cplay -I AAC -d 0 -c 0 sample.aac Some static parameters for compress streams are set up in topology bytes in the form: [0:3]: param ID [4:7]: size in bytes [8:n-1]: data[] We need now a way to specify codec ID, so we borrow 2 bytes from param ID, like this: [0:3]: (param ID, codec ID) [4:7]: size in bytes [8:n-1]: data[] Using 0 for codec ID means 'dont care'. Topologies supporting just 1 codec are not affected and need not to be changed. Signed-off-by: Daniel Baluta --- src/audio/module_adapter/module/cadence.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/src/audio/module_adapter/module/cadence.c b/src/audio/module_adapter/module/cadence.c index 3e8df03e6a04..d334bdb48aae 100644 --- a/src/audio/module_adapter/module/cadence.c +++ b/src/audio/module_adapter/module/cadence.c @@ -260,6 +260,8 @@ static int cadence_codec_apply_config(struct processing_module *mod) { int ret = 0; int size; + uint16_t param_id; + uint16_t codec_id; struct module_config *cfg; void *data; struct module_param *param; @@ -291,8 +293,20 @@ static int cadence_codec_apply_config(struct processing_module *mod) param = data; comp_dbg(dev, "cadence_codec_apply_config() applying param %d value %d", param->id, param->data[0]); + + param_id = param->id & 0xFF; + codec_id = param->id >> 16; + + /* if the parameter is not for current codec skip it! */ + if (codec_id && codec_id != cd->api_id) { + /* Obtain next parameter */ + data = (char *)data + param->size; + size -= param->size; + continue; + } + /* Set read parameter */ - API_CALL(cd, XA_API_CMD_SET_CONFIG_PARAM, param->id, + API_CALL(cd, XA_API_CMD_SET_CONFIG_PARAM, param_id, param->data, ret); if (ret != LIB_NO_ERROR) { if (LIB_IS_FATAL_ERROR(ret)) { From e3723733d0e622e30790af1be66cbcf854529cf3 Mon Sep 17 00:00:00 2001 From: Daniel Baluta Date: Mon, 26 Sep 2022 12:20:09 +0300 Subject: [PATCH 37/39] topology1: Update documentation to reflect multicodec support This updates documentation to reflect that now param id is only 2 bytes followed by 2 bytes codec id. Signed-off-by: Daniel Baluta --- tools/topology/topology1/sof/pipe-codec-adapter-capture.m4 | 3 ++- tools/topology/topology1/sof/pipe-codec-adapter-playback.m4 | 3 ++- .../topology1/sof/pipe-eq-iir-codec-adapter-playback.m4 | 3 ++- .../topology/topology1/sof/pipe-host-codec-adapter-playback.m4 | 3 ++- 4 files changed, 8 insertions(+), 4 deletions(-) diff --git a/tools/topology/topology1/sof/pipe-codec-adapter-capture.m4 b/tools/topology/topology1/sof/pipe-codec-adapter-capture.m4 index 6d947456f4fe..e5e5c4cda3a0 100644 --- a/tools/topology/topology1/sof/pipe-codec-adapter-capture.m4 +++ b/tools/topology/topology1/sof/pipe-codec-adapter-capture.m4 @@ -30,7 +30,8 @@ include(`bytecontrol.m4') # - [16:31]: reserved 0s # - (optional) 12+ bytes codec_param: codec TLV parameters container, for more details please refer # struct codec_param under audio/codec_adapter/codec/generic.h -# - [0:3]: param ID +# - [0:1]: param ID +# - [2:3]: codec ID (when supporting multiple codecs, 0 otherwise) # - [4:7]: size in bytes (ID + size + data) # - [8:n-1]: data[], the param data ifdef(`CA_SETUP_CONTROLBYTES',`', `define(`CA_SETUP_CONTROLBYTES', diff --git a/tools/topology/topology1/sof/pipe-codec-adapter-playback.m4 b/tools/topology/topology1/sof/pipe-codec-adapter-playback.m4 index b30e9d6260f2..dcfe4d75dbe6 100644 --- a/tools/topology/topology1/sof/pipe-codec-adapter-playback.m4 +++ b/tools/topology/topology1/sof/pipe-codec-adapter-playback.m4 @@ -30,7 +30,8 @@ include(`bytecontrol.m4') # - [16:31]: reserved 0s # - (optional) 12+ bytes codec_param: codec TLV parameters container, for more details please refer # struct codec_param under audio/codec_adapter/codec/generic.h -# - [0:3]: param ID +# - [0:1]: param ID +# - [2:3]: codec ID (when supporting multiple codecs, 0 otherwise) # - [4:7]: size in bytes (ID + size + data) # - [8:n-1]: data[], the param data ifdef(`CA_SETUP_CONTROLBYTES',`', `define(`CA_SETUP_CONTROLBYTES', diff --git a/tools/topology/topology1/sof/pipe-eq-iir-codec-adapter-playback.m4 b/tools/topology/topology1/sof/pipe-eq-iir-codec-adapter-playback.m4 index fbc19e80804c..c93d599819a7 100644 --- a/tools/topology/topology1/sof/pipe-eq-iir-codec-adapter-playback.m4 +++ b/tools/topology/topology1/sof/pipe-eq-iir-codec-adapter-playback.m4 @@ -31,7 +31,8 @@ include(`eq_iir.m4') # - [16:31]: reserved 0s # - (optional) 12+ bytes codec_param: codec TLV parameters container, for more details please refer # struct codec_param under audio/codec_adapter/codec/generic.h -# - [0:3]: param ID +# - [0:1]: param ID +# - [2:3]: codec ID (when supporting multiple codecs, 0 otherwise) # - [4:7]: size in bytes (ID + size + data) # - [8:n-1]: data[], the param data ifdef(`CA_SETUP_CONTROLBYTES',`', `define(`CA_SETUP_CONTROLBYTES', diff --git a/tools/topology/topology1/sof/pipe-host-codec-adapter-playback.m4 b/tools/topology/topology1/sof/pipe-host-codec-adapter-playback.m4 index 1ecd1abb799f..2ee73c6ac32c 100644 --- a/tools/topology/topology1/sof/pipe-host-codec-adapter-playback.m4 +++ b/tools/topology/topology1/sof/pipe-host-codec-adapter-playback.m4 @@ -30,7 +30,8 @@ include(`bytecontrol.m4') # - [16:31]: reserved 0s # - (optional) 12+ bytes codec_param: codec TLV parameters container, for more details please refer # struct codec_param under audio/codec_adapter/codec/generic.h -# - [0:3]: param ID +# - [0:1]: param ID +# - [2:3]: codec ID, when supporting multiple codecs, 0 otherwise # - [4:7]: size in bytes (ID + size + data) # - [8:n-1]: data[], the param data ifdef(`CA_SETUP_CONTROLBYTES',`', `define(`CA_SETUP_CONTROLBYTES', From 2cb07114b16f617c510f2033363278ac580ca547 Mon Sep 17 00:00:00 2001 From: Daniel Baluta Date: Mon, 26 Sep 2022 12:26:19 +0300 Subject: [PATCH 38/39] topology1: Merge i.MX AAC/MP3 compr topology Because now we can support multiple codecs with same topology lets merge i.MX aac/mp3 topologies. Signed-off-by: Daniel Baluta --- .../topology1/development/CMakeLists.txt | 6 +- .../development/sof-imx8-compr-mp3-wm8960.m4 | 94 ------------------ ...aac-wm8960.m4 => sof-imx8-compr-wm8960.m4} | 11 ++- .../sof-imx8mp-compr-aac-wm8960.m4 | 95 ------------------- ...3-wm8960.m4 => sof-imx8mp-compr-wm8960.m4} | 9 +- 5 files changed, 15 insertions(+), 200 deletions(-) delete mode 100644 tools/topology/topology1/development/sof-imx8-compr-mp3-wm8960.m4 rename tools/topology/topology1/development/{sof-imx8-compr-aac-wm8960.m4 => sof-imx8-compr-wm8960.m4} (88%) delete mode 100644 tools/topology/topology1/development/sof-imx8mp-compr-aac-wm8960.m4 rename tools/topology/topology1/development/{sof-imx8mp-compr-mp3-wm8960.m4 => sof-imx8mp-compr-wm8960.m4} (89%) diff --git a/tools/topology/topology1/development/CMakeLists.txt b/tools/topology/topology1/development/CMakeLists.txt index 973703177b7c..28966ed85bd8 100644 --- a/tools/topology/topology1/development/CMakeLists.txt +++ b/tools/topology/topology1/development/CMakeLists.txt @@ -25,12 +25,10 @@ set(TPLGS "sof-imx8mp-src-wm8960\;sof-imx8mp-src-wm8960" "sof-imx8-src-wm8960\;sof-imx8-src-wm8960" "sof-imx8-src-cs42888\;sof-imx8-src-cs42888" - "sof-imx8-compr-aac-wm8960\;sof-imx8-compr-aac-wm8960" - "sof-imx8-compr-mp3-wm8960\;sof-imx8-compr-mp3-wm8960" + "sof-imx8-compr-wm8960\;sof-imx8-compr-wm8960" "sof-imx8-compr-pcm-wm8960\;sof-imx8-compr-pcm-wm8960" "sof-imx8-compr-pcm-cap-wm8960\;sof-imx8-compr-pcm-cap-wm8960" - "sof-imx8mp-compr-aac-wm8960\;sof-imx8mp-compr-aac-wm8960" - "sof-imx8mp-compr-mp3-wm8960\;sof-imx8mp-compr-mp3-wm8960" + "sof-imx8mp-compr-wm8960\;sof-imx8mp-compr-wm8960" "sof-imx8mp-compr-pcm-wm8960\;sof-imx8mp-compr-pcm-wm8960" "sof-imx8mp-compr-pcm-cap-wm8960\;sof-imx8mp-compr-pcm-cap-wm8960" "sof-apl-nocodec-demux-eq-4ch4ch\;sof-apl-nocodec-demux-eq-4ch4ch" diff --git a/tools/topology/topology1/development/sof-imx8-compr-mp3-wm8960.m4 b/tools/topology/topology1/development/sof-imx8-compr-mp3-wm8960.m4 deleted file mode 100644 index ab9f31bcd427..000000000000 --- a/tools/topology/topology1/development/sof-imx8-compr-mp3-wm8960.m4 +++ /dev/null @@ -1,94 +0,0 @@ -# -# Topology with codec_adapter processing component for i.MX8QM/i.MX8QXP -# - -# Include topology builder -include(`utils.m4') -include(`dai.m4') -include(`pipeline.m4') -include(`sai.m4') -include(`pcm.m4') -include(`buffer.m4') - -# Include TLV library -include(`common/tlv.m4') - -# Include Token library -include(`sof/tokens.m4') - -# Include DSP configuration -include(`platform/imx/imx8.m4') - - -# Post process setup config - - #codec Post Process setup config -# -# Define the pipelines -# -# PCM0 <----> volume <-----> SAI3 (wm8960) -# - - -DECLARE_SOF_RT_UUID("Cadence Codec", cadence_codec_uuid, 0xd8218443, 0x5ff3, - 0x4a4c, 0xb3, 0x88, 0x6c, 0xfe, 0x07, 0xb9, 0x56, 0xaa); - -define(`CA_UUID', cadence_codec_uuid) - -# Post process setup config -define(`CA_SETUP_CONTROLBYTES', -`` bytes "0x53,0x4f,0x46,0x00,0x00,0x00,0x00,0x00,' -` 0x0C,0x00,0x00,0x00,0x00,0x10,0x00,0x03,' -` 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,' -` 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,' -` 0x00,0x00,0x00,0x00,0x0C,0x00,0x00,0x00,' -` 0x20,0x00,0x00,0x00"'' -) - -define(`CA_SETUP_CONTROLBYTES_MAX', 300) - -undefine(`DAI_PERIODS') -define(`DAI_PERIODS', 8) - -dnl PIPELINE_PCM_ADD(pipeline, -dnl pipe id, pcm, max channels, format, -dnl period, priority, core, -dnl pcm_min_rate, pcm_max_rate, pipeline_rate, -dnl time_domain, sched_comp) - -# Low Latency playback pipeline 1 on PCM 0 using max 2 channels of s32le. -# Set 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-codec-adapter-playback.m4, - 1, 0, 2, s32le, - 1000, 0, 0, - 48000, 48000, 48000) - -# -# DAIs configuration -# - -dnl DAI_ADD(pipeline, -dnl pipe id, dai type, dai_index, dai_be, -dnl buffer, periods, format, -dnl period, priority, core, time_domain) - -# playback DAI is SAI3 using 2 periods -# Buffers use s32le format, with 48 frame per 1000us on core 0 with priority 0 -DAI_ADD(sof/pipe-dai-playback.m4, - 1, SAI, 1, sai1-wm8960-hifi, - PIPELINE_SOURCE_1, 2, s32le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_DMA) - - -# PCM Low Latency, id 0 - -dnl PCM_DUPLEX_ADD(name, pcm_id, playback, capture) -COMPR_PLAYBACK_ADD(Port0, 0, PIPELINE_PCM_1) - -dnl DAI_CONFIG(type, idx, link_id, name, sai_config) -DAI_CONFIG(SAI, 1, 0, sai1-wm8960-hifi, - SAI_CONFIG(I2S, SAI_CLOCK(mclk, 12288000, codec_mclk_in), - SAI_CLOCK(bclk, 3072000, codec_master), - SAI_CLOCK(fsync, 48000, codec_master), - SAI_TDM(2, 32, 3, 3), - SAI_CONFIG_DATA(SAI, 1, 0))) diff --git a/tools/topology/topology1/development/sof-imx8-compr-aac-wm8960.m4 b/tools/topology/topology1/development/sof-imx8-compr-wm8960.m4 similarity index 88% rename from tools/topology/topology1/development/sof-imx8-compr-aac-wm8960.m4 rename to tools/topology/topology1/development/sof-imx8-compr-wm8960.m4 index a11ba177962d..ebc1bcb22dc9 100644 --- a/tools/topology/topology1/development/sof-imx8-compr-aac-wm8960.m4 +++ b/tools/topology/topology1/development/sof-imx8-compr-wm8960.m4 @@ -1,5 +1,6 @@ # # Topology with codec_adapter processing component for i.MX8QM/i.MX8QXP +# supporting following codecs: MP3, AAC. # # Include topology builder @@ -38,12 +39,14 @@ define(`CA_UUID', cadence_codec_uuid) # Post process setup config define(`CA_SETUP_CONTROLBYTES', `` bytes "0x53,0x4f,0x46,0x00,0x00,0x00,0x00,0x00,' -` 0x18,0x00,0x00,0x00,0x00,0x10,0x00,0x03,' +` 0x24,0x00,0x00,0x00,0x00,0x10,0x00,0x03,' ` 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,' ` 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,' -` 0x07,0x00,0x00,0x00,0x0C,0x00,0x00,0x00,' -` 0x18,0x00,0x00,0x00,0x03,0x00,0x00,0x00,' -` 0x0C,0x00,0x00,0x00,0x02,0x00,0x00,0x00"'') +` 0x07,0x00,0x02,0x00,0x0C,0x00,0x00,0x00,' +` 0x18,0x00,0x00,0x00,0x03,0x00,0x02,0x00,' +` 0x0C,0x00,0x00,0x00,0x02,0x00,0x00,0x00,' +` 0x00,0x00,0x06,0x00,0x0C,0x00,0x00,0x00,' +` 0x20,0x00,0x0,0x0"'') define(`CA_SETUP_CONTROLBYTES_MAX', 300) diff --git a/tools/topology/topology1/development/sof-imx8mp-compr-aac-wm8960.m4 b/tools/topology/topology1/development/sof-imx8mp-compr-aac-wm8960.m4 deleted file mode 100644 index 8b0f0dc59b36..000000000000 --- a/tools/topology/topology1/development/sof-imx8mp-compr-aac-wm8960.m4 +++ /dev/null @@ -1,95 +0,0 @@ -# -# Topology with codec_adapter processing component for i.MX8MP -# - -# Include topology builder -include(`utils.m4') -include(`dai.m4') -include(`pipeline.m4') -include(`sai.m4') -include(`pcm.m4') -include(`buffer.m4') - -# Include TLV library -include(`common/tlv.m4') - -# Include Token library -include(`sof/tokens.m4') - -# Include DSP configuration -include(`platform/imx/imx8.m4') - - -# Post process setup config - - #codec Post Process setup config -# -# Define the pipelines -# -# PCM0 <----> volume <-----> SAI3 (wm8960) -# - - -DECLARE_SOF_RT_UUID("Cadence Codec", cadence_codec_uuid, 0xd8218443, 0x5ff3, - 0x4a4c, 0xb3, 0x88, 0x6c, 0xfe, 0x07, 0xb9, 0x56, 0xaa); - -define(`CA_UUID', cadence_codec_uuid) - -# Post process setup config -define(`CA_SETUP_CONTROLBYTES', -`` bytes "0x53,0x4f,0x46,0x00,0x00,0x00,0x00,0x00,' -` 0x18,0x00,0x00,0x00,0x00,0x10,0x00,0x03,' -` 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,' -` 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,' -` 0x07,0x00,0x00,0x00,0x0C,0x00,0x00,0x00,' -` 0x18,0x00,0x00,0x00,0x03,0x00,0x00,0x00,' -` 0x0C,0x00,0x00,0x00,0x02,0x00,0x00,0x00"'' -) - -define(`CA_SETUP_CONTROLBYTES_MAX', 300) - -undefine(`DAI_PERIODS') -define(`DAI_PERIODS', 8) - -dnl PIPELINE_PCM_ADD(pipeline, -dnl pipe id, pcm, max channels, format, -dnl period, priority, core, -dnl pcm_min_rate, pcm_max_rate, pipeline_rate, -dnl time_domain, sched_comp) - -# Low Latency playback pipeline 1 on PCM 0 using max 2 channels of s32le. -# Set 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-codec-adapter-playback.m4, - 1, 0, 2, s32le, - 1000, 0, 0, - 48000, 48000, 48000) - -# -# DAIs configuration -# - -dnl DAI_ADD(pipeline, -dnl pipe id, dai type, dai_index, dai_be, -dnl buffer, periods, format, -dnl period, priority, core, time_domain) - -# playback DAI is SAI3 using 2 periods -# Buffers use s32le format, with 48 frame per 1000us on core 0 with priority 0 -DAI_ADD(sof/pipe-dai-playback.m4, - 1, SAI, 3, sai3-wm8960-hifi, - PIPELINE_SOURCE_1, 2, s32le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_DMA) - - -# PCM Low Latency, id 0 - -dnl PCM_DUPLEX_ADD(name, pcm_id, playback, capture) -COMPR_PLAYBACK_ADD(Port0, 0, PIPELINE_PCM_1) - -dnl DAI_CONFIG(type, idx, link_id, name, sai_config) -DAI_CONFIG(SAI, 3, 0, sai3-wm8960-hifi, - SAI_CONFIG(I2S, SAI_CLOCK(mclk, 12288000, codec_mclk_in), - SAI_CLOCK(bclk, 3072000, codec_master), - SAI_CLOCK(fsync, 48000, codec_master), - SAI_TDM(2, 32, 3, 3), - SAI_CONFIG_DATA(SAI, 3, 0))) diff --git a/tools/topology/topology1/development/sof-imx8mp-compr-mp3-wm8960.m4 b/tools/topology/topology1/development/sof-imx8mp-compr-wm8960.m4 similarity index 89% rename from tools/topology/topology1/development/sof-imx8mp-compr-mp3-wm8960.m4 rename to tools/topology/topology1/development/sof-imx8mp-compr-wm8960.m4 index d18970b1a295..0f9850966f49 100644 --- a/tools/topology/topology1/development/sof-imx8mp-compr-mp3-wm8960.m4 +++ b/tools/topology/topology1/development/sof-imx8mp-compr-wm8960.m4 @@ -1,6 +1,6 @@ # # Topology with codec_adapter processing component for i.MX8MP -# +# supporting following codecs: MP3, AAC. # Include topology builder include(`utils.m4') @@ -38,10 +38,13 @@ define(`CA_UUID', cadence_codec_uuid) # Post process setup config define(`CA_SETUP_CONTROLBYTES', `` bytes "0x53,0x4f,0x46,0x00,0x00,0x00,0x00,0x00,' -` 0x0C,0x00,0x00,0x00,0x00,0x10,0x00,0x03,' +` 0x24,0x00,0x00,0x00,0x00,0x10,0x00,0x03,' ` 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,' ` 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,' -` 0x00,0x00,0x00,0x00,0x0C,0x00,0x00,0x00,' +` 0x07,0x00,0x02,0x00,0x0C,0x00,0x00,0x00,' +` 0x18,0x00,0x00,0x00,0x03,0x00,0x02,0x00,' +` 0x0C,0x00,0x00,0x00,0x02,0x00,0x00,0x00,' +` 0x00,0x00,0x06,0x00,0x0C,0x00,0x00,0x00,' ` 0x20,0x00,0x00,0x00"'' ) From 9b564ea205b9597d29971cac0b5dcd9312db84d4 Mon Sep 17 00:00:00 2001 From: Daniel Baluta Date: Thu, 29 Sep 2022 17:02:43 +0300 Subject: [PATCH 39/39] Revert "xtensa: configs: Enable comp legacy on i.MX platforms" This reverts commit 1044e004e4ecbaf9a6ff53a2aa253e9072d8f535. On i.MX platforms we noticed a bug were playback followed by capture would cause capture to fail. This issue was later fixed by: commit b9889d52d0e1b ("module_adapter: Modify reset API") so we can get rid of CONFIG_LEGACY_INTERFACE. Signed-off-by: Daniel Baluta --- src/arch/xtensa/configs/imx8_defconfig | 1 - src/arch/xtensa/configs/imx8m_defconfig | 1 - src/arch/xtensa/configs/imx8ulp_defconfig | 1 - src/arch/xtensa/configs/imx8x_defconfig | 1 - 4 files changed, 4 deletions(-) diff --git a/src/arch/xtensa/configs/imx8_defconfig b/src/arch/xtensa/configs/imx8_defconfig index f82f6f45392c..a245738a5d80 100644 --- a/src/arch/xtensa/configs/imx8_defconfig +++ b/src/arch/xtensa/configs/imx8_defconfig @@ -2,4 +2,3 @@ CONFIG_IMX8=y CONFIG_HAVE_AGENT=n CONFIG_FORMAT_CONVERT_HIFI3=n CONFIG_KPB_FORCE_COPY_TYPE_NORMAL=n -CONFIG_COMP_LEGACY_INTERFACE=y diff --git a/src/arch/xtensa/configs/imx8m_defconfig b/src/arch/xtensa/configs/imx8m_defconfig index 84d7eff14190..bb9d86024498 100644 --- a/src/arch/xtensa/configs/imx8m_defconfig +++ b/src/arch/xtensa/configs/imx8m_defconfig @@ -2,4 +2,3 @@ CONFIG_IMX8M=y CONFIG_HAVE_AGENT=n CONFIG_FORMAT_CONVERT_HIFI3=n CONFIG_KPB_FORCE_COPY_TYPE_NORMAL=n -CONFIG_COMP_LEGACY_INTERFACE=y diff --git a/src/arch/xtensa/configs/imx8ulp_defconfig b/src/arch/xtensa/configs/imx8ulp_defconfig index 104d2ac240d4..28247a20678e 100644 --- a/src/arch/xtensa/configs/imx8ulp_defconfig +++ b/src/arch/xtensa/configs/imx8ulp_defconfig @@ -2,4 +2,3 @@ CONFIG_IMX8ULP=y CONFIG_HAVE_AGENT=n CONFIG_FORMAT_CONVERT_HIFI3=n CONFIG_KPB_FORCE_COPY_TYPE_NORMAL=n -CONFIG_COMP_LEGACY_INTERFACE=y diff --git a/src/arch/xtensa/configs/imx8x_defconfig b/src/arch/xtensa/configs/imx8x_defconfig index ef61560dbd40..a7766c19bb61 100644 --- a/src/arch/xtensa/configs/imx8x_defconfig +++ b/src/arch/xtensa/configs/imx8x_defconfig @@ -2,4 +2,3 @@ CONFIG_IMX8X=y CONFIG_HAVE_AGENT=n CONFIG_FORMAT_CONVERT_HIFI3=n CONFIG_KPB_FORCE_COPY_TYPE_NORMAL=n -CONFIG_COMP_LEGACY_INTERFACE=y