Implement requested changes

hierophect · hierophect · commit a89928c13c74 · 2020-04-01T13:02:05.000-04:00
diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
@@ -188,6 +188,7 @@ jobs:
         - "mini_sam_m4"
         - "monster_m4sk"
         - "ndgarage_ndbit6"
+        - "nucleo_h743zi_2"
         - "ohs2020_badge"
         - "openbook_m4"
         - "particle_argon"
diff --git a/extmod/ulab b/extmod/ulab
@@ -1 +1 @@
-Subproject commit 66b89de8c714790de8647dc55f59430002044171
+Subproject commit a91b36986d81fd906a6232010778f2a93d690f8e
diff --git a/locale/ID.po b/locale/ID.po
@@ -8,7 +8,7 @@ msgid ""
 msgstr ""
 "Project-Id-Version: PACKAGE VERSION\n"
 "Report-Msgid-Bugs-To: \n"
-"POT-Creation-Date: 2020-03-20 17:57-0500\n"
+"POT-Creation-Date: 2020-04-01 12:29-0400\n"
 "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
 "Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
 "Language-Team: LANGUAGE <LL@li.org>\n"
diff --git a/locale/circuitpython.pot b/locale/circuitpython.pot
@@ -8,7 +8,7 @@ msgid ""
 msgstr ""
 "Project-Id-Version: PACKAGE VERSION\n"
 "Report-Msgid-Bugs-To: \n"
-"POT-Creation-Date: 2020-03-20 17:57-0500\n"
+"POT-Creation-Date: 2020-04-01 12:29-0400\n"
 "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
 "Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
 "Language-Team: LANGUAGE <LL@li.org>\n"
diff --git a/locale/de_DE.po b/locale/de_DE.po
@@ -7,7 +7,7 @@ msgid ""
 msgstr ""
 "Project-Id-Version: \n"
 "Report-Msgid-Bugs-To: \n"
-"POT-Creation-Date: 2020-03-20 17:57-0500\n"
+"POT-Creation-Date: 2020-04-01 12:29-0400\n"
 "PO-Revision-Date: 2018-07-27 11:55-0700\n"
 "Last-Translator: Pascal Deneaux\n"
 "Language-Team: Sebastian Plamauer, Pascal Deneaux\n"
diff --git a/locale/en_US.po b/locale/en_US.po
@@ -7,7 +7,7 @@ msgid ""
 msgstr ""
 "Project-Id-Version: \n"
 "Report-Msgid-Bugs-To: \n"
-"POT-Creation-Date: 2020-03-20 17:57-0500\n"
+"POT-Creation-Date: 2020-04-01 12:29-0400\n"
 "PO-Revision-Date: 2018-07-27 11:55-0700\n"
 "Last-Translator: \n"
 "Language-Team: \n"
diff --git a/locale/en_x_pirate.po b/locale/en_x_pirate.po
@@ -7,7 +7,7 @@ msgid ""
 msgstr ""
 "Project-Id-Version: \n"
 "Report-Msgid-Bugs-To: \n"
-"POT-Creation-Date: 2020-03-20 17:57-0500\n"
+"POT-Creation-Date: 2020-04-01 12:29-0400\n"
 "PO-Revision-Date: 2018-07-27 11:55-0700\n"
 "Last-Translator: \n"
 "Language-Team: @sommersoft, @MrCertainly\n"
diff --git a/locale/es.po b/locale/es.po
@@ -7,7 +7,7 @@ msgid ""
 msgstr ""
 "Project-Id-Version: \n"
 "Report-Msgid-Bugs-To: \n"
-"POT-Creation-Date: 2020-03-20 17:57-0500\n"
+"POT-Creation-Date: 2020-04-01 12:29-0400\n"
 "PO-Revision-Date: 2018-08-24 22:56-0500\n"
 "Last-Translator: \n"
 "Language-Team: \n"
diff --git a/locale/fil.po b/locale/fil.po
@@ -7,7 +7,7 @@ msgid ""
 msgstr ""
 "Project-Id-Version: \n"
 "Report-Msgid-Bugs-To: \n"
-"POT-Creation-Date: 2020-03-20 17:57-0500\n"
+"POT-Creation-Date: 2020-04-01 12:29-0400\n"
 "PO-Revision-Date: 2018-12-20 22:15-0800\n"
 "Last-Translator: Timothy <me@timothygarcia.ca>\n"
 "Language-Team: fil\n"
diff --git a/locale/fr.po b/locale/fr.po
@@ -8,7 +8,7 @@ msgid ""
 msgstr ""
 "Project-Id-Version: 0.1\n"
 "Report-Msgid-Bugs-To: \n"
-"POT-Creation-Date: 2020-03-20 17:57-0500\n"
+"POT-Creation-Date: 2020-04-01 12:29-0400\n"
 "PO-Revision-Date: 2019-04-14 20:05+0100\n"
 "Last-Translator: Pierrick Couturier <arofarn@arofarn.info>\n"
 "Language-Team: fr\n"
diff --git a/locale/it_IT.po b/locale/it_IT.po
@@ -8,7 +8,7 @@ msgid ""
 msgstr ""
 "Project-Id-Version: PACKAGE VERSION\n"
 "Report-Msgid-Bugs-To: \n"
-"POT-Creation-Date: 2020-03-20 17:57-0500\n"
+"POT-Creation-Date: 2020-04-01 12:29-0400\n"
 "PO-Revision-Date: 2018-10-02 16:27+0200\n"
 "Last-Translator: Enrico Paganin <enrico.paganin@mail.com>\n"
 "Language-Team: \n"
diff --git a/locale/ko.po b/locale/ko.po
@@ -8,7 +8,7 @@ msgid ""
 msgstr ""
 "Project-Id-Version: PACKAGE VERSION\n"
 "Report-Msgid-Bugs-To: \n"
-"POT-Creation-Date: 2020-03-20 17:57-0500\n"
+"POT-Creation-Date: 2020-04-01 12:29-0400\n"
 "PO-Revision-Date: 2019-05-06 14:22-0700\n"
 "Last-Translator: \n"
 "Language-Team: LANGUAGE <LL@li.org>\n"
diff --git a/locale/pl.po b/locale/pl.po
@@ -7,7 +7,7 @@ msgid ""
 msgstr ""
 "Project-Id-Version: \n"
 "Report-Msgid-Bugs-To: \n"
-"POT-Creation-Date: 2020-03-20 17:57-0500\n"
+"POT-Creation-Date: 2020-04-01 12:29-0400\n"
 "PO-Revision-Date: 2019-03-19 18:37-0700\n"
 "Last-Translator: Radomir Dopieralski <circuitpython@sheep.art.pl>\n"
 "Language-Team: pl\n"
diff --git a/locale/pt_BR.po b/locale/pt_BR.po
@@ -8,7 +8,7 @@ msgid ""
 msgstr ""
 "Project-Id-Version: PACKAGE VERSION\n"
 "Report-Msgid-Bugs-To: \n"
-"POT-Creation-Date: 2020-03-20 17:57-0500\n"
+"POT-Creation-Date: 2020-04-01 12:29-0400\n"
 "PO-Revision-Date: 2018-10-02 21:14-0000\n"
 "Last-Translator: \n"
 "Language-Team: \n"
diff --git a/locale/zh_Latn_pinyin.po b/locale/zh_Latn_pinyin.po
@@ -7,7 +7,7 @@ msgid ""
 msgstr ""
 "Project-Id-Version: circuitpython-cn\n"
 "Report-Msgid-Bugs-To: \n"
-"POT-Creation-Date: 2020-03-20 17:57-0500\n"
+"POT-Creation-Date: 2020-04-01 12:29-0400\n"
 "PO-Revision-Date: 2019-04-13 10:10-0700\n"
 "Last-Translator: hexthat\n"
 "Language-Team: Chinese Hanyu Pinyin\n"
diff --git a/ports/stm/Makefile b/ports/stm/Makefile
@@ -78,7 +78,6 @@ INC += -I../../lib/mp-readline
 INC += -I../../lib/tinyusb/src
 INC += -I../../supervisor/shared/usb
 
-
 #Debugging/Optimization
 ifeq ($(DEBUG), 1)
 	CFLAGS += -ggdb
@@ -106,9 +105,9 @@ CFLAGS += -Wno-cast-align
 CFLAGS += -mthumb -mabi=aapcs-linux
 
 # Arm core selection
-MCU_FLAGS_F4 = -mtune=cortex-m4 -mcpu=cortex-m4
-MCU_FLAGS_F7 = -mtune=cortex-m7 -mcpu=cortex-m7
-MCU_FLAGS_H7 = -mtune=cortex-m7 -mcpu=cortex-m7
+MCU_FLAGS_F4 = -mcpu=cortex-m4
+MCU_FLAGS_F7 = -mcpu=cortex-m7
+MCU_FLAGS_H7 = -mcpu=cortex-m7
 CFLAGS += $(MCU_FLAGS_$(MCU_SERIES))
 
 CFLAGS += -DSTM32_HAL_H='<stm32$(MCU_SERIES_LOWER)xx_hal.h>'
diff --git a/ports/stm/boards/STM32H743_fs.ld b/ports/stm/boards/STM32H743_fs.ld
@@ -54,9 +54,6 @@ ENTRY(Reset_Handler)
 
 /* Highest address of the user mode stack */
 _estack = 0x20020000;    /* end of RAM */
-/* Generate a link error if heap and stack don't fit into RAM */
-_Min_Heap_Size = 0x200;      /* required amount of heap  */
-_Min_Stack_Size = 0x400; /* required amount of stack */
 
 /* Specify the memory areas */
 MEMORY
@@ -65,14 +62,20 @@ MEMORY
     FLASH_ISR (rx)  : ORIGIN = 0x08000000, LENGTH = 128K    /* sector 0, 128K */
     FLASH_FS (r)    : ORIGIN = 0x08020000, LENGTH = 128K    /* sector 1, 128K */
     FLASH_TEXT (rx) : ORIGIN = 0x08040000, LENGTH = 1792K   /* sectors 6*128 + 8*128 */
-    DTCM (xrw)      : ORIGIN = 0x20000000, LENGTH = 128K    /* Used for storage cache */
+    DTCM (xrw)      : ORIGIN = 0x20000000, LENGTH = 128K
     RAM (xrw)       : ORIGIN = 0x24000000, LENGTH = 512K    /* AXI SRAM */
+    SRAM_D2 (xrw)   : ORIGIN = 0x30000000, LENGTH = 288K    /* AHB1 SRAM */
+    SRAM_D3 (xrw)   : ORIGIN = 0x30040000, LENGTH = 64K     /* AHB2 SRAM */
+    ITCM (xrw)      : ORIGIN = 0x00000000, LENGTH = 64K
 }
 
 /* produce a link error if there is not this amount of RAM for these sections */
 _minimum_stack_size = 2K;
 _minimum_heap_size = 16K;
 
+/* brainless copy paste for stack code. Results in ambiguous hard crash */
+/* _ld_default_stack_size = 20K; */
+
 /* Define tho top end of the stack.  The stack is full descending so begins just
    above last byte of RAM.  Note that EABI requires the stack to be 8-byte
    aligned for a call. */
@@ -158,6 +161,51 @@ SECTIONS
         . = ALIGN(4);
     } >RAM
 
+    /* itcm stuff doesn't work, results in arcane hard crashes
+    .itcm :
+    {
+        . = ALIGN(4);
+
+        *(.itcm.*)
+
+        . = ALIGN(4);
+    } > ITCM AT> FLASH_TEXT
+    _ld_itcm_destination = ADDR(.itcm);
+    _ld_itcm_flash_copy = LOADADDR(.itcm);
+    _ld_itcm_size = SIZEOF(.itcm);
+
+    .dtcm_data :
+    {
+        . = ALIGN(4);
+
+        *(.dtcm_data.*)
+
+        . = ALIGN(4);
+    } > DTCM AT> FLASH_TEXT
+    _ld_dtcm_data_destination = ADDR(.dtcm_data);
+    _ld_dtcm_data_flash_copy = LOADADDR(.dtcm_data);
+    _ld_dtcm_data_size = SIZEOF(.dtcm_data);
+
+    .dtcm_bss :
+    {
+        . = ALIGN(4);
+
+        *(.dtcm_bss.*)
+
+        . = ALIGN(4);
+    } > DTCM AT> DTCM
+    _ld_dtcm_bss_start = ADDR(.dtcm_bss);
+    _ld_dtcm_bss_size = SIZEOF(.dtcm_bss);
+
+    .stack :
+    {
+        . = ALIGN(8);
+        _ld_stack_bottom = .;
+        . += _ld_default_stack_size;
+    } > DTCM
+    _ld_stack_top = ORIGIN(DTCM) + LENGTH(DTCM);
+    */
+
     .ARM.attributes 0 : { *(.ARM.attributes) }
 }
 
diff --git a/ports/stm/boards/nucleo_h743zi_2/board.c b/ports/stm/boards/nucleo_h743zi_2/board.c
diff --git a/ports/stm/boards/nucleo_h743zi_2/mpconfigboard.h b/ports/stm/boards/nucleo_h743zi_2/mpconfigboard.h
@@ -26,10 +26,9 @@
 
 //Micropython setup
 
-#define MICROPY_HW_BOARD_NAME       "STM32H743_DISCO"
+#define MICROPY_HW_BOARD_NAME       "NUCLEO STM32H743"
 #define MICROPY_HW_MCU_NAME         "STM32H743"
 
-// #define FLASH_SIZE                  (0x200000)
 #define FLASH_PAGE_SIZE             (0x4000)
 
 #define BOARD_OSC_DIV (8)
diff --git a/ports/stm/boards/nucleo_h743zi_2/mpconfigboard.mk b/ports/stm/boards/nucleo_h743zi_2/mpconfigboard.mk
@@ -1,6 +1,6 @@
 USB_VID = 0x239A #REPLACE
 USB_PID = 0x808A #REPLACE
-USB_PRODUCT = "STM32H743ZI Discovery Board - CPy"
+USB_PRODUCT = "Nucleo H743ZI - CPy"
 USB_MANUFACTURER = "STMicroelectronics"
 USB_DEVICES = "CDC,MSC"
 
diff --git a/ports/stm/boards/nucleo_h743zi_2/pins.c b/ports/stm/boards/nucleo_h743zi_2/pins.c
diff --git a/ports/stm/boards/nucleo_h743zi_2/stm32h7xx_hal_conf.h b/ports/stm/boards/nucleo_h743zi_2/stm32h7xx_hal_conf.h
diff --git a/ports/stm/peripherals/stm32h7/stm32h743xx/clocks.c b/ports/stm/peripherals/stm32h7/stm32h743xx/clocks.c
@@ -79,84 +79,5 @@ void stm32_peripherals_clocks_init(void) {
   RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
   RCC_PeriphCLKInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL;
   HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphCLKInitStruct);
-  
-    // RCC_OscInitTypeDef RCC_OscInitStruct = {0};
-    // RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
-    // RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
-
-    // /** Supply configuration update enable 
-    // */
-    // HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
-    // /** Configure the main internal regulator output voltage 
-    // */
-    // __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-
-    // while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
-    // /** Macro to configure the PLL clock source 
-    // */
-    // __HAL_RCC_PLL_PLLSOURCE_CONFIG(RCC_PLLSOURCE_HSE);
-    // /** Initializes the CPU, AHB and APB busses clocks 
-    // */
-    // RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
-    // RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
-    // RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
-    // RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
-    // RCC_OscInitStruct.PLL.PLLM = 4;
-    // RCC_OscInitStruct.PLL.PLLN = 400;
-    // RCC_OscInitStruct.PLL.PLLP = 2;
-    // RCC_OscInitStruct.PLL.PLLQ = 4;
-    // RCC_OscInitStruct.PLL.PLLR = 2;
-    // RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_1;
-    // RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
-    // RCC_OscInitStruct.PLL.PLLFRACN = 0;
-    // if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-    // {
-
-    // }
-    // /** Initializes the CPU, AHB and APB busses clocks 
-    // */
-    // RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
-    //                           |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2
-    //                           |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1;
-    // RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
-    // RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
-    // RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
-    // RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
-    // RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
-    // RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
-    // RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
-
-    // if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
-    // {
-
-    // }
-    // PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; /*RCC_PERIPHCLK_USART3|RCC_PERIPHCLK_UART4
-    //                           |RCC_PERIPHCLK_SPI1|RCC_PERIPHCLK_ADC
-    //                           |RCC_PERIPHCLK_I2C1| */
-    // // PeriphClkInitStruct.PLL2.PLL2M = 1;
-    // // PeriphClkInitStruct.PLL2.PLL2N = 19;
-    // // PeriphClkInitStruct.PLL2.PLL2P = 2;
-    // // PeriphClkInitStruct.PLL2.PLL2Q = 2;
-    // // PeriphClkInitStruct.PLL2.PLL2R = 2;
-    // // PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_3;
-    // // PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOMEDIUM;
-    // // PeriphClkInitStruct.PLL2.PLL2FRACN = 0;
-    // PeriphClkInitStruct.PLL3.PLL3M = 4;
-    // PeriphClkInitStruct.PLL3.PLL3N = 120;
-    // PeriphClkInitStruct.PLL3.PLL3P = 2;
-    // PeriphClkInitStruct.PLL3.PLL3Q = 5;
-    // PeriphClkInitStruct.PLL3.PLL3R = 2;
-    // PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3VCIRANGE_1;
-    // PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3VCOWIDE;
-    // PeriphClkInitStruct.PLL3.PLL3FRACN = 0;
-    // PeriphClkInitStruct.Spi123ClockSelection = RCC_SPI123CLKSOURCE_PLL;
-    // PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1;
-    // PeriphClkInitStruct.I2c123ClockSelection = RCC_I2C123CLKSOURCE_D2PCLK1;
-    // PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL3;
-    // PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_PLL2;
-    // if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
-    // {
-
-    // }
 
 }
diff --git a/ports/stm/supervisor/internal_flash.c b/ports/stm/supervisor/internal_flash.c
@@ -181,25 +181,6 @@ void supervisor_flash_flush(void) {
             reset_into_safe_mode(FLASH_WRITE_FAIL);
         }
 
-        // __HAL_FLASH_DATA_CACHE_DISABLE();
-        // __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
-
-        // __HAL_FLASH_DATA_CACHE_RESET();
-        // __HAL_FLASH_INSTRUCTION_CACHE_RESET();
-
-        // __HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
-        // __HAL_FLASH_DATA_CACHE_ENABLE();
-
-        // // reprogram the sector
-        // for (uint32_t i = 0; i < sector_size; i++) {
-        //     if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_BYTE, sector_start_addr, (uint64_t)_flash_cache[i]) != HAL_OK) {
-        //         // error occurred during flash write
-        //         HAL_FLASH_Lock(); // lock the flash
-        //         mp_printf(&mp_plat_print, "FLASH WRITE ERROR");
-        //     }
-        //     sector_start_addr += 1;
-        // }
-
         uint32_t * cache_addr = (uint32_t*)_flash_cache;
 
         #if defined(STM32H7)
diff --git a/ports/stm/supervisor/internal_flash.h b/ports/stm/supervisor/internal_flash.h
diff --git a/ports/stm/supervisor/usb.c b/ports/stm/supervisor/usb.c
diff --git a/supervisor/linker.h b/supervisor/linker.h
