# 16-Bit-RISC Processor
16-Bit RISC processor written in VHDL. Could be implemented onto FPGA with proper configuration.

***The Architecture of this processor is take from [Github Repo](https://github.com/acarcher/risc)***

 ALU Opcode
 -
 
![image](https://github.com/vaidikk10/16-Bit-RISC/assets/59808940/52efaa64-1d6d-4e5e-8ffc-c68e03848b36)

 Instruction Architecure
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 ![image](https://github.com/vaidikk10/16-Bit-RISC/assets/59808940/97b1f636-c23c-4b3f-86a6-8e8dc481a808)

  General Description
  -
  - `14` available instruction
  - `8` General purpose Registers
  - Available `LDR/STR`
  - Branch Available with instructions `B/BEQ`
  - Default Clock Speed set at `10 ns` or `100 Mhz`

Processor Organisation
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![16-Bit RISC](https://github.com/vaidikk10/16-Bit-RISC/assets/59808940/d17c91f5-5731-4aa1-907e-c007fe2c9785)

This project was just to learn bit more about Microprocessor Organisation. [This Repo](https://github.com/acarcher/risc) was key towards my learning.