Skip to content

Commit b9bcb95

Browse files
tao-rendavem330
tao-ren
authored and
davem330
committed
net: phy: broadcom: add 1000Base-X support for BCM54616S
The BCM54616S PHY cannot work properly in RGMII->1000Base-X mode, mainly because genphy functions are designed for copper links, and 1000Base-X (clause 37) auto negotiation needs to be handled differently. This patch enables 1000Base-X support for BCM54616S by customizing 3 driver callbacks, and it's verified to be working on Facebook CMM BMC platform (RGMII->1000Base-KX): - probe: probe callback detects PHY's operation mode based on INTERF_SEL[1:0] pins and 1000X/100FX selection bit in SerDES 100-FX Control register. - config_aneg: calls genphy_c37_config_aneg when the PHY is running in 1000Base-X mode; otherwise, genphy_config_aneg will be called. - read_status: calls genphy_c37_read_status when the PHY is running in 1000Base-X mode; otherwise, genphy_read_status will be called. Note: BCM54616S PHY can also be configured in RGMII->100Base-FX mode, and 100Base-FX support is not available as of now. Signed-off-by: Tao Ren <taoren@fb.com> Acked-by: Vladimir Oltean <olteanv@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
1 parent fa6e98c commit b9bcb95

2 files changed

Lines changed: 61 additions & 6 deletions

File tree

‎drivers/net/phy/broadcom.c‎

Lines changed: 53 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -359,9 +359,9 @@ static int bcm5482_config_init(struct phy_device *phydev)
359359
/*
360360
* Select 1000BASE-X register set (primary SerDes)
361361
*/
362-
reg = bcm_phy_read_shadow(phydev, BCM5482_SHD_MODE);
363-
bcm_phy_write_shadow(phydev, BCM5482_SHD_MODE,
364-
reg | BCM5482_SHD_MODE_1000BX);
362+
reg = bcm_phy_read_shadow(phydev, BCM54XX_SHD_MODE);
363+
bcm_phy_write_shadow(phydev, BCM54XX_SHD_MODE,
364+
reg | BCM54XX_SHD_MODE_1000BX);
365365

366366
/*
367367
* LED1=ACTIVITYLED, LED3=LINKSPD[2]
@@ -427,19 +427,66 @@ static int bcm5481_config_aneg(struct phy_device *phydev)
427427
return ret;
428428
}
429429

430+
static int bcm54616s_probe(struct phy_device *phydev)
431+
{
432+
int val, intf_sel;
433+
434+
val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_MODE);
435+
if (val < 0)
436+
return val;
437+
438+
/* The PHY is strapped in RGMII-fiber mode when INTERF_SEL[1:0]
439+
* is 01b, and the link between PHY and its link partner can be
440+
* either 1000Base-X or 100Base-FX.
441+
* RGMII-1000Base-X is properly supported, but RGMII-100Base-FX
442+
* support is still missing as of now.
443+
*/
444+
intf_sel = (val & BCM54XX_SHD_INTF_SEL_MASK) >> 1;
445+
if (intf_sel == 1) {
446+
val = bcm_phy_read_shadow(phydev, BCM54616S_SHD_100FX_CTRL);
447+
if (val < 0)
448+
return val;
449+
450+
/* Bit 0 of the SerDes 100-FX Control register, when set
451+
* to 1, sets the MII/RGMII -> 100BASE-FX configuration.
452+
* When this bit is set to 0, it sets the GMII/RGMII ->
453+
* 1000BASE-X configuration.
454+
*/
455+
if (!(val & BCM54616S_100FX_MODE))
456+
phydev->dev_flags |= PHY_BCM_FLAGS_MODE_1000BX;
457+
}
458+
459+
return 0;
460+
}
461+
430462
static int bcm54616s_config_aneg(struct phy_device *phydev)
431463
{
432464
int ret;
433465

434466
/* Aneg firsly. */
435-
ret = genphy_config_aneg(phydev);
467+
if (phydev->dev_flags & PHY_BCM_FLAGS_MODE_1000BX)
468+
ret = genphy_c37_config_aneg(phydev);
469+
else
470+
ret = genphy_config_aneg(phydev);
436471

437472
/* Then we can set up the delay. */
438473
bcm54xx_config_clock_delay(phydev);
439474

440475
return ret;
441476
}
442477

478+
static int bcm54616s_read_status(struct phy_device *phydev)
479+
{
480+
int err;
481+
482+
if (phydev->dev_flags & PHY_BCM_FLAGS_MODE_1000BX)
483+
err = genphy_c37_read_status(phydev);
484+
else
485+
err = genphy_read_status(phydev);
486+
487+
return err;
488+
}
489+
443490
static int brcm_phy_setbits(struct phy_device *phydev, int reg, int set)
444491
{
445492
int val;
@@ -631,6 +678,8 @@ static struct phy_driver broadcom_drivers[] = {
631678
.config_aneg = bcm54616s_config_aneg,
632679
.ack_interrupt = bcm_phy_ack_intr,
633680
.config_intr = bcm_phy_config_intr,
681+
.read_status = bcm54616s_read_status,
682+
.probe = bcm54616s_probe,
634683
}, {
635684
.phy_id = PHY_ID_BCM5464,
636685
.phy_id_mask = 0xfffffff0,

‎include/linux/brcmphy.h‎

Lines changed: 8 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -200,9 +200,15 @@
200200
#define BCM5482_SHD_SSD 0x14 /* 10100: Secondary SerDes control */
201201
#define BCM5482_SHD_SSD_LEDM 0x0008 /* SSD LED Mode enable */
202202
#define BCM5482_SHD_SSD_EN 0x0001 /* SSD enable */
203-
#define BCM5482_SHD_MODE 0x1f /* 11111: Mode Control Register */
204-
#define BCM5482_SHD_MODE_1000BX 0x0001 /* Enable 1000BASE-X registers */
205203

204+
/* 10011: SerDes 100-FX Control Register */
205+
#define BCM54616S_SHD_100FX_CTRL 0x13
206+
#define BCM54616S_100FX_MODE BIT(0) /* 100-FX SerDes Enable */
207+
208+
/* 11111: Mode Control Register */
209+
#define BCM54XX_SHD_MODE 0x1f
210+
#define BCM54XX_SHD_INTF_SEL_MASK GENMASK(2, 1) /* INTERF_SEL[1:0] */
211+
#define BCM54XX_SHD_MODE_1000BX BIT(0) /* Enable 1000-X registers */
206212

207213
/*
208214
* EXPANSION SHADOW ACCESS REGISTERS. (PHY REG 0x15, 0x16, and 0x17)

0 commit comments

Comments
 (0)