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rddunlaptorvalds
rddunlap
authored and
torvalds
committed
atyfb: fix CONFIG_ namespace violations
Fix namespace violations by changing non-kconfig CONFIG_ names to CNFG_*. Fixes breakage in staging/, which adds a real CONFIG_PANEL. Signed-off-by: Randy Dunlap <randy.dunlap@oracle.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
1 parent cd29cf7 commit fe86175

7 files changed

Lines changed: 52 additions & 52 deletions

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‎drivers/video/aty/aty128fb.c‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1475,7 +1475,7 @@ static int aty128fb_set_par(struct fb_info *info)
14751475
aty128_set_pll(&par->pll, par);
14761476
aty128_set_fifo(&par->fifo_reg, par);
14771477

1478-
config = aty_ld_le32(CONFIG_CNTL) & ~3;
1478+
config = aty_ld_le32(CNFG_CNTL) & ~3;
14791479

14801480
#if defined(__BIG_ENDIAN)
14811481
if (par->crtc.bpp == 32)
@@ -1484,7 +1484,7 @@ static int aty128fb_set_par(struct fb_info *info)
14841484
config |= 1; /* make aperture do 16 bit swapping */
14851485
#endif
14861486

1487-
aty_st_le32(CONFIG_CNTL, config);
1487+
aty_st_le32(CNFG_CNTL, config);
14881488
aty_st_8(CRTC_EXT_CNTL + 1, 0); /* turn the video back on */
14891489

14901490
info->fix.line_length = (par->crtc.vxres * par->crtc.bpp) >> 3;
@@ -1875,7 +1875,7 @@ static int __devinit aty128_init(struct pci_dev *pdev, const struct pci_device_i
18751875
u32 dac;
18761876

18771877
/* Get the chip revision */
1878-
chip_rev = (aty_ld_le32(CONFIG_CNTL) >> 16) & 0x1F;
1878+
chip_rev = (aty_ld_le32(CNFG_CNTL) >> 16) & 0x1F;
18791879

18801880
strcpy(video_card, "Rage128 XX ");
18811881
video_card[8] = ent->device >> 8;
@@ -2057,7 +2057,7 @@ static int __devinit aty128_probe(struct pci_dev *pdev, const struct pci_device_
20572057

20582058
/* Grab memory size from the card */
20592059
// How does this relate to the resource length from the PCI hardware?
2060-
par->vram_size = aty_ld_le32(CONFIG_MEMSIZE) & 0x03FFFFFF;
2060+
par->vram_size = aty_ld_le32(CNFG_MEMSIZE) & 0x03FFFFFF;
20612061

20622062
/* Virtualize the framebuffer */
20632063
info->screen_base = ioremap(fb_addr, par->vram_size);

‎drivers/video/aty/atyfb_base.c‎

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -135,7 +135,7 @@
135135
#if defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || \
136136
defined (CONFIG_FB_ATY_GENERIC_LCD) || defined(CONFIG_FB_ATY_BACKLIGHT)
137137
static const u32 lt_lcd_regs[] = {
138-
CONFIG_PANEL_LG,
138+
CNFG_PANEL_LG,
139139
LCD_GEN_CNTL_LG,
140140
DSTN_CONTROL_LG,
141141
HFB_PITCH_ADDR_LG,
@@ -446,7 +446,7 @@ static int __devinit correct_chipset(struct atyfb_par *par)
446446
par->pll_limits.ecp_max = aty_chips[i].ecp_max;
447447
par->features = aty_chips[i].features;
448448

449-
chip_id = aty_ld_le32(CONFIG_CHIP_ID, par);
449+
chip_id = aty_ld_le32(CNFG_CHIP_ID, par);
450450
type = chip_id & CFG_CHIP_TYPE;
451451
rev = (chip_id & CFG_CHIP_REV) >> 24;
452452

@@ -629,7 +629,7 @@ static void aty_get_crtc(const struct atyfb_par *par, struct crtc *crtc)
629629
crtc->lcd_index = aty_ld_le32(LCD_INDEX, par);
630630
aty_st_le32(LCD_INDEX, crtc->lcd_index, par);
631631
}
632-
crtc->lcd_config_panel = aty_ld_lcd(CONFIG_PANEL, par);
632+
crtc->lcd_config_panel = aty_ld_lcd(CNFG_PANEL, par);
633633
crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par);
634634

635635

@@ -676,7 +676,7 @@ static void aty_set_crtc(const struct atyfb_par *par, const struct crtc *crtc)
676676
aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl & ~(CRTC_EXT_DISP_EN | CRTC_EN), par);
677677

678678
/* update non-shadow registers first */
679-
aty_st_lcd(CONFIG_PANEL, crtc->lcd_config_panel, par);
679+
aty_st_lcd(CNFG_PANEL, crtc->lcd_config_panel, par);
680680
aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl &
681681
~(CRTC_RW_SELECT | SHADOW_EN | SHADOW_RW_EN), par);
682682

@@ -858,7 +858,7 @@ static int aty_var_to_crtc(const struct fb_info *info,
858858
if (!M64_HAS(MOBIL_BUS))
859859
crtc->lcd_index |= CRTC2_DISPLAY_DIS;
860860

861-
crtc->lcd_config_panel = aty_ld_lcd(CONFIG_PANEL, par) | 0x4000;
861+
crtc->lcd_config_panel = aty_ld_lcd(CNFG_PANEL, par) | 0x4000;
862862
crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par) & ~CRTC_RW_SELECT;
863863

864864
crtc->lcd_gen_cntl &=
@@ -2254,7 +2254,7 @@ static int __devinit aty_init(struct fb_info *info)
22542254
if (!M64_HAS(INTEGRATED)) {
22552255
u32 stat0;
22562256
u8 dac_type, dac_subtype, clk_type;
2257-
stat0 = aty_ld_le32(CONFIG_STAT0, par);
2257+
stat0 = aty_ld_le32(CNFG_STAT0, par);
22582258
par->bus_type = (stat0 >> 0) & 0x07;
22592259
par->ram_type = (stat0 >> 3) & 0x07;
22602260
ramname = aty_gx_ram[par->ram_type];
@@ -2324,7 +2324,7 @@ static int __devinit aty_init(struct fb_info *info)
23242324
par->dac_ops = &aty_dac_ct;
23252325
par->pll_ops = &aty_pll_ct;
23262326
par->bus_type = PCI;
2327-
par->ram_type = (aty_ld_le32(CONFIG_STAT0, par) & 0x07);
2327+
par->ram_type = (aty_ld_le32(CNFG_STAT0, par) & 0x07);
23282328
ramname = aty_ct_ram[par->ram_type];
23292329
/* for many chips, the mclk is 67 MHz for SDRAM, 63 MHz otherwise */
23302330
if (par->pll_limits.mclk == 67 && par->ram_type < SDRAM)
@@ -2433,7 +2433,7 @@ static int __devinit aty_init(struct fb_info *info)
24332433
}
24342434

24352435
if (M64_HAS(MAGIC_VRAM_SIZE)) {
2436-
if (aty_ld_le32(CONFIG_STAT1, par) & 0x40000000)
2436+
if (aty_ld_le32(CNFG_STAT1, par) & 0x40000000)
24372437
info->fix.smem_len += 0x400000;
24382438
}
24392439

@@ -2946,7 +2946,7 @@ static int __devinit atyfb_setup_sparc(struct pci_dev *pdev,
29462946
* Fix PROMs idea of MEM_CNTL settings...
29472947
*/
29482948
mem = aty_ld_le32(MEM_CNTL, par);
2949-
chip_id = aty_ld_le32(CONFIG_CHIP_ID, par);
2949+
chip_id = aty_ld_le32(CNFG_CHIP_ID, par);
29502950
if (((chip_id & CFG_CHIP_TYPE) == VT_CHIP_ID) && !((chip_id >> 24) & 1)) {
29512951
switch (mem & 0x0f) {
29522952
case 3:
@@ -2964,7 +2964,7 @@ static int __devinit atyfb_setup_sparc(struct pci_dev *pdev,
29642964
default:
29652965
break;
29662966
}
2967-
if ((aty_ld_le32(CONFIG_STAT0, par) & 7) >= SDRAM)
2967+
if ((aty_ld_le32(CNFG_STAT0, par) & 7) >= SDRAM)
29682968
mem &= ~(0x00700000);
29692969
}
29702970
mem &= ~(0xcf80e000); /* Turn off all undocumented bits. */
@@ -3572,7 +3572,7 @@ static int __init atyfb_atari_probe(void)
35723572
}
35733573

35743574
/* Fake pci_id for correct_chipset() */
3575-
switch (aty_ld_le32(CONFIG_CHIP_ID, par) & CFG_CHIP_TYPE) {
3575+
switch (aty_ld_le32(CNFG_CHIP_ID, par) & CFG_CHIP_TYPE) {
35763576
case 0x00d7:
35773577
par->pci_id = PCI_CHIP_MACH64GX;
35783578
break;

‎drivers/video/aty/radeon_base.c‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1936,8 +1936,8 @@ static void fixup_memory_mappings(struct radeonfb_info *rinfo)
19361936
OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl | CRTC_DISP_REQ_EN_B);
19371937
mdelay(100);
19381938

1939-
aper_base = INREG(CONFIG_APER_0_BASE);
1940-
aper_size = INREG(CONFIG_APER_SIZE);
1939+
aper_base = INREG(CNFG_APER_0_BASE);
1940+
aper_size = INREG(CNFG_APER_SIZE);
19411941

19421942
#ifdef SET_MC_FB_FROM_APERTURE
19431943
/* Set framebuffer to be at the same address as set in PCI BAR */
@@ -2024,11 +2024,11 @@ static void radeon_identify_vram(struct radeonfb_info *rinfo)
20242024
~CRTC_H_CUTOFF_ACTIVE_EN);
20252025
}
20262026
} else {
2027-
tmp = INREG(CONFIG_MEMSIZE);
2027+
tmp = INREG(CNFG_MEMSIZE);
20282028
}
20292029

20302030
/* mem size is bits [28:0], mask off the rest */
2031-
rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK;
2031+
rinfo->video_ram = tmp & CNFG_MEMSIZE_MASK;
20322032

20332033
/*
20342034
* Hack to get around some busted production M6's
@@ -2228,7 +2228,7 @@ static int __devinit radeonfb_pci_register (struct pci_dev *pdev,
22282228
*/
22292229
rinfo->errata = 0;
22302230
if (rinfo->family == CHIP_FAMILY_R300 &&
2231-
(INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK)
2231+
(INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK)
22322232
== CFG_ATI_REV_A11)
22332233
rinfo->errata |= CHIP_ERRATA_R300_CG;
22342234

‎drivers/video/aty/radeon_pm.c‎

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -333,7 +333,7 @@ static void radeon_pm_enable_dynamic_mode(struct radeonfb_info *rinfo)
333333
if (!rinfo->has_CRTC2) {
334334
tmp = INPLL(pllSCLK_CNTL);
335335

336-
if ((INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK) > CFG_ATI_REV_A13)
336+
if ((INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK) > CFG_ATI_REV_A13)
337337
tmp &= ~(SCLK_CNTL__FORCE_CP | SCLK_CNTL__FORCE_RB);
338338
tmp &= ~(SCLK_CNTL__FORCE_HDP | SCLK_CNTL__FORCE_DISP1 |
339339
SCLK_CNTL__FORCE_TOP | SCLK_CNTL__FORCE_SE |
@@ -468,9 +468,9 @@ static void radeon_pm_enable_dynamic_mode(struct radeonfb_info *rinfo)
468468

469469
/*RAGE_6::A11 A12 A12N1 A13, RV250::A11 A12, R300*/
470470
if ((rinfo->family == CHIP_FAMILY_RV250 &&
471-
((INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK) < CFG_ATI_REV_A13)) ||
471+
((INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK) < CFG_ATI_REV_A13)) ||
472472
((rinfo->family == CHIP_FAMILY_RV100) &&
473-
((INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK) <= CFG_ATI_REV_A13))) {
473+
((INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK) <= CFG_ATI_REV_A13))) {
474474
tmp |= SCLK_CNTL__FORCE_CP;
475475
tmp |= SCLK_CNTL__FORCE_VIP;
476476
}
@@ -486,7 +486,7 @@ static void radeon_pm_enable_dynamic_mode(struct radeonfb_info *rinfo)
486486
/* RV200::A11 A12 RV250::A11 A12 */
487487
if (((rinfo->family == CHIP_FAMILY_RV200) ||
488488
(rinfo->family == CHIP_FAMILY_RV250)) &&
489-
((INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK) < CFG_ATI_REV_A13))
489+
((INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK) < CFG_ATI_REV_A13))
490490
tmp |= SCLK_MORE_CNTL__FORCEON;
491491

492492
OUTPLL(pllSCLK_MORE_CNTL, tmp);
@@ -497,7 +497,7 @@ static void radeon_pm_enable_dynamic_mode(struct radeonfb_info *rinfo)
497497
/* RV200::A11 A12, RV250::A11 A12 */
498498
if (((rinfo->family == CHIP_FAMILY_RV200) ||
499499
(rinfo->family == CHIP_FAMILY_RV250)) &&
500-
((INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK) < CFG_ATI_REV_A13)) {
500+
((INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK) < CFG_ATI_REV_A13)) {
501501
tmp = INPLL(pllPLL_PWRMGT_CNTL);
502502
tmp |= PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE;
503503
OUTPLL(pllPLL_PWRMGT_CNTL, tmp);
@@ -702,7 +702,7 @@ static void radeon_pm_restore_regs(struct radeonfb_info *rinfo)
702702
OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]);
703703
OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]);
704704
OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]);
705-
OUTREG(CONFIG_MEMSIZE, rinfo->video_ram);
705+
OUTREG(CNFG_MEMSIZE, rinfo->video_ram);
706706

707707
OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]);
708708
OUTREG(DISP_PWR_MAN, rinfo->save_regs[10]);
@@ -1723,7 +1723,7 @@ static void radeon_reinitialize_M10(struct radeonfb_info *rinfo)
17231723
OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]);
17241724
OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]);
17251725
OUTREG(OV0_BASE_ADDR, rinfo->save_regs[80]);
1726-
OUTREG(CONFIG_MEMSIZE, rinfo->video_ram);
1726+
OUTREG(CNFG_MEMSIZE, rinfo->video_ram);
17271727
OUTREG(BUS_CNTL, rinfo->save_regs[36]);
17281728
OUTREG(BUS_CNTL1, rinfo->save_regs[14]);
17291729
OUTREG(MPP_TB_CONFIG, rinfo->save_regs[37]);
@@ -1961,7 +1961,7 @@ static void radeon_pm_m9p_reconfigure_mc(struct radeonfb_info *rinfo)
19611961
OUTMC(rinfo, ixMC_CHP_IO_CNTL_B1, rinfo->save_regs[68] /*0x141555ff*/);
19621962
OUTMC(rinfo, ixMC_IMP_CNTL_0, rinfo->save_regs[71] /*0x00009249*/);
19631963
OUTREG(MC_IND_INDEX, 0);
1964-
OUTREG(CONFIG_MEMSIZE, rinfo->video_ram);
1964+
OUTREG(CNFG_MEMSIZE, rinfo->video_ram);
19651965

19661966
mdelay(20);
19671967
}
@@ -2361,7 +2361,7 @@ static void radeon_reinitialize_QW(struct radeonfb_info *rinfo)
23612361
OUTMC(rinfo, ixMC_IMP_CNTL_0, 0x00009249);
23622362
OUTREG(MC_IND_INDEX, 0);
23632363

2364-
OUTREG(CONFIG_MEMSIZE, rinfo->video_ram);
2364+
OUTREG(CNFG_MEMSIZE, rinfo->video_ram);
23652365

23662366
radeon_pm_full_reset_sdram(rinfo);
23672367

‎include/video/aty128.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -21,9 +21,9 @@
2121
#define I2C_CNTL_1 0x0094
2222
#define PALETTE_INDEX 0x00b0
2323
#define PALETTE_DATA 0x00b4
24-
#define CONFIG_CNTL 0x00e0
24+
#define CNFG_CNTL 0x00e0
2525
#define GEN_RESET_CNTL 0x00f0
26-
#define CONFIG_MEMSIZE 0x00f8
26+
#define CNFG_MEMSIZE 0x00f8
2727
#define MEM_CNTL 0x0140
2828
#define MEM_POWER_MISC 0x015c
2929
#define AGP_BASE 0x0170

‎include/video/mach64.h‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -103,7 +103,7 @@
103103
#define CUR_HORZ_VERT_OFF 0x0070 /* Dword offset 0_1C */
104104
#define CUR2_HORZ_VERT_OFF 0x0070 /* Dword offset 0_1C */
105105

106-
#define CONFIG_PANEL_LG 0x0074 /* Dword offset 0_1D (LG) */
106+
#define CNFG_PANEL_LG 0x0074 /* Dword offset 0_1D (LG) */
107107

108108
/* General I/O Control */
109109
#define GP_IO 0x0078 /* Dword offset 0_1E */
@@ -146,8 +146,8 @@
146146
#define CLOCK_SEL_CNTL 0x0090 /* Dword offset 0_24 */
147147

148148
/* Configuration */
149-
#define CONFIG_STAT1 0x0094 /* Dword offset 0_25 */
150-
#define CONFIG_STAT2 0x0098 /* Dword offset 0_26 */
149+
#define CNFG_STAT1 0x0094 /* Dword offset 0_25 */
150+
#define CNFG_STAT2 0x0098 /* Dword offset 0_26 */
151151

152152
/* Bus Control */
153153
#define BUS_CNTL 0x00A0 /* Dword offset 0_28 */
@@ -190,9 +190,9 @@
190190
#define POWER_MANAGEMENT_LG 0x00D8 /* Dword offset 0_36 (LG) */
191191

192192
/* Configuration */
193-
#define CONFIG_CNTL 0x00DC /* Dword offset 0_37 (CT, ET, VT) */
194-
#define CONFIG_CHIP_ID 0x00E0 /* Dword offset 0_38 */
195-
#define CONFIG_STAT0 0x00E4 /* Dword offset 0_39 */
193+
#define CNFG_CNTL 0x00DC /* Dword offset 0_37 (CT, ET, VT) */
194+
#define CNFG_CHIP_ID 0x00E0 /* Dword offset 0_38 */
195+
#define CNFG_STAT0 0x00E4 /* Dword offset 0_39 */
196196

197197
/* Test and Debug */
198198
#define CRC_SIG 0x00E8 /* Dword offset 0_3A */
@@ -851,17 +851,17 @@
851851
#define PLL_YCLK_CNTL 0x29
852852
#define PM_DYN_CLK_CNTL 0x2A
853853

854-
/* CONFIG_CNTL register constants */
854+
/* CNFG_CNTL register constants */
855855
#define APERTURE_4M_ENABLE 1
856856
#define APERTURE_8M_ENABLE 2
857857
#define VGA_APERTURE_ENABLE 4
858858

859-
/* CONFIG_STAT0 register constants (GX, CX) */
859+
/* CNFG_STAT0 register constants (GX, CX) */
860860
#define CFG_BUS_TYPE 0x00000007
861861
#define CFG_MEM_TYPE 0x00000038
862862
#define CFG_INIT_DAC_TYPE 0x00000e00
863863

864-
/* CONFIG_STAT0 register constants (CT, ET, VT) */
864+
/* CNFG_STAT0 register constants (CT, ET, VT) */
865865
#define CFG_MEM_TYPE_xT 0x00000007
866866

867867
#define ISA 0
@@ -942,7 +942,7 @@
942942
#define PCI_ATI_VENDOR_ID 0x1002
943943

944944

945-
/* CONFIG_CHIP_ID register constants */
945+
/* CNFG_CHIP_ID register constants */
946946
#define CFG_CHIP_TYPE 0x0000FFFF
947947
#define CFG_CHIP_CLASS 0x00FF0000
948948
#define CFG_CHIP_REV 0xFF000000
@@ -951,7 +951,7 @@
951951
#define CFG_CHIP_MINOR 0xC0000000
952952

953953

954-
/* Chip IDs read from CONFIG_CHIP_ID */
954+
/* Chip IDs read from CNFG_CHIP_ID */
955955

956956
/* mach64GX family */
957957
#define GX_CHIP_ID 0xD7 /* mach64GX (ATI888GX00) */
@@ -1254,7 +1254,7 @@
12541254
#define CRTC2_DISPLAY_DIS 0x00000400
12551255

12561256
/* LCD register indices */
1257-
#define CONFIG_PANEL 0x00
1257+
#define CNFG_PANEL 0x00
12581258
#define LCD_GEN_CNTL 0x01
12591259
#define DSTN_CONTROL 0x02
12601260
#define HFB_PITCH_ADDR 0x03

‎include/video/radeon.h‎

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -11,13 +11,13 @@
1111
#define HI_STAT 0x004C
1212
#define BUS_CNTL1 0x0034
1313
#define I2C_CNTL_1 0x0094
14-
#define CONFIG_CNTL 0x00E0
15-
#define CONFIG_MEMSIZE 0x00F8
16-
#define CONFIG_APER_0_BASE 0x0100
17-
#define CONFIG_APER_1_BASE 0x0104
18-
#define CONFIG_APER_SIZE 0x0108
19-
#define CONFIG_REG_1_BASE 0x010C
20-
#define CONFIG_REG_APER_SIZE 0x0110
14+
#define CNFG_CNTL 0x00E0
15+
#define CNFG_MEMSIZE 0x00F8
16+
#define CNFG_APER_0_BASE 0x0100
17+
#define CNFG_APER_1_BASE 0x0104
18+
#define CNFG_APER_SIZE 0x0108
19+
#define CNFG_REG_1_BASE 0x010C
20+
#define CNFG_REG_APER_SIZE 0x0110
2121
#define PAD_AGPINPUT_DELAY 0x0164
2222
#define PAD_CTLR_STRENGTH 0x0168
2323
#define PAD_CTLR_UPDATE 0x016C
@@ -509,7 +509,7 @@
509509
/* CLOCK_CNTL_INDEX bit constants */
510510
#define PLL_WR_EN 0x00000080
511511

512-
/* CONFIG_CNTL bit constants */
512+
/* CNFG_CNTL bit constants */
513513
#define CFG_VGA_RAM_EN 0x00000100
514514
#define CFG_ATI_REV_ID_MASK (0xf << 16)
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#define CFG_ATI_REV_A11 (0 << 16)
@@ -980,7 +980,7 @@
980980

981981
/* masks */
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983-
#define CONFIG_MEMSIZE_MASK 0x1f000000
983+
#define CNFG_MEMSIZE_MASK 0x1f000000
984984
#define MEM_CFG_TYPE 0x40000000
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#define DST_OFFSET_MASK 0x003fffff
986986
#define DST_PITCH_MASK 0x3fc00000

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