cavs: disable data cache operations on uncached addresses

lyakh · lgirdwood · commit bfe7707f37de · 2021-05-08T14:32:40.000+01:00
Trying to write back cache on uncached addresses can overwrite data.
Invalidating cache should have no ill effects but isn't very
meaningful either. Disable both.

Signed-off-by: Guennadi Liakhovetski &lt;guennadi.liakhovetski@linux.intel.com&gt;
diff --git a/src/arch/xtensa/include/arch/lib/cache.h b/src/arch/xtensa/include/arch/lib/cache.h
@@ -20,10 +20,15 @@
 #include <stddef.h>
 #include <stdint.h>
 
+#define SRAM_UNCACHED_ALIAS	0x20000000
+
+#define is_cached(address) (!!((uintptr_t)(address) & SRAM_UNCACHED_ALIAS))
+
 static inline void dcache_writeback_region(void *addr, size_t size)
 {
 #if XCHAL_DCACHE_SIZE > 0
-	xthal_dcache_region_writeback(addr, size);
+	if (is_cached(addr))
+		xthal_dcache_region_writeback(addr, size);
 #endif
 }
 
@@ -37,7 +42,8 @@ static inline void dcache_writeback_all(void)
 static inline void dcache_invalidate_region(void *addr, size_t size)
 {
 #if XCHAL_DCACHE_SIZE > 0
-	xthal_dcache_region_invalidate(addr, size);
+	if (is_cached(addr))
+		xthal_dcache_region_invalidate(addr, size);
 #endif
 }
 
@@ -65,7 +71,8 @@ static inline void icache_invalidate_all(void)
 static inline void dcache_writeback_invalidate_region(void *addr, size_t size)
 {
 #if XCHAL_DCACHE_SIZE > 0
-	xthal_dcache_region_writeback_inv(addr, size);
+	if (is_cached(addr))
+		xthal_dcache_region_writeback_inv(addr, size);
 #endif
 }
 
diff --git a/src/platform/intel/cavs/include/cavs/lib/memory.h b/src/platform/intel/cavs/include/cavs/lib/memory.h
@@ -85,7 +85,7 @@ struct sof;
 
 #define SRAM_ALIAS_BASE		0x9E000000
 #define SRAM_ALIAS_MASK		0xFF000000
-#define SRAM_ALIAS_OFFSET	0x20000000
+#define SRAM_ALIAS_OFFSET	SRAM_UNCACHED_ALIAS
 
 #if !defined UNIT_TEST && !defined __ZEPHYR__
 #define uncache_to_cache(address) \

Original file line number	Diff line number	Diff line change
`@@ -20,10 +20,15 @@`
`20`	`20`	`#include <stddef.h>`
`21`	`21`	`#include <stdint.h>`
`22`	`22`
	`23`	`+#define SRAM_UNCACHED_ALIAS 0x20000000`
	`24`	`+`
	`25`	`+#define is_cached(address) (!!((uintptr_t)(address) & SRAM_UNCACHED_ALIAS))`
	`26`	`+`
`23`	`27`	`static inline void dcache_writeback_region(void *addr, size_t size)`
`24`	`28`	`{`
`25`	`29`	`#if XCHAL_DCACHE_SIZE > 0`
`26`		`- xthal_dcache_region_writeback(addr, size);`
	`30`	`+ if (is_cached(addr))`
	`31`	`+ xthal_dcache_region_writeback(addr, size);`
`27`	`32`	`#endif`
`28`	`33`	`}`
`29`	`34`
`@@ -37,7 +42,8 @@ static inline void dcache_writeback_all(void)`
`37`	`42`	`static inline void dcache_invalidate_region(void *addr, size_t size)`
`38`	`43`	`{`
`39`	`44`	`#if XCHAL_DCACHE_SIZE > 0`
`40`		`- xthal_dcache_region_invalidate(addr, size);`
	`45`	`+ if (is_cached(addr))`
	`46`	`+ xthal_dcache_region_invalidate(addr, size);`
`41`	`47`	`#endif`
`42`	`48`	`}`
`43`	`49`
`@@ -65,7 +71,8 @@ static inline void icache_invalidate_all(void)`
`65`	`71`	`static inline void dcache_writeback_invalidate_region(void *addr, size_t size)`
`66`	`72`	`{`
`67`	`73`	`#if XCHAL_DCACHE_SIZE > 0`
`68`		`- xthal_dcache_region_writeback_inv(addr, size);`
	`74`	`+ if (is_cached(addr))`
	`75`	`+ xthal_dcache_region_writeback_inv(addr, size);`
`69`	`76`	`#endif`
`70`	`77`	`}`
`71`	`78`