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| 1 | +# Capture RTNR Pipeline and PCM |
| 2 | +# |
| 3 | +# Pipeline Endpoints for connection are :- |
| 4 | +# |
| 5 | +# host PCM_C <--- B1 <--- RTNR 0 <-- B0 <-- sink DAI0 |
| 6 | +# |
| 7 | +# |
| 8 | +# |
| 9 | + |
| 10 | +# Include topology builder |
| 11 | +include(`utils.m4') |
| 12 | +include(`buffer.m4') |
| 13 | +include(`pcm.m4') |
| 14 | +include(`dai.m4') |
| 15 | +include(`pipeline.m4') |
| 16 | +include(`bytecontrol.m4') |
| 17 | +include(`rtnr.m4') |
| 18 | + |
| 19 | +ifdef(`RTNR_BUFFER_SIZE_MIN',`', define(RTNR_BUFFER_SIZE_MIN, `65536')) |
| 20 | +ifdef(`RTNR_BUFFER_SIZE_MAX',`', define(RTNR_BUFFER_SIZE_MAX, `65536')) |
| 21 | +# |
| 22 | +# Controls |
| 23 | +# |
| 24 | + |
| 25 | +define(DEF_RTNR_PRIV, concat(`rtnr_priv_', PIPELINE_ID)) |
| 26 | +define(DEF_RTNR_BYTES, concat(`rtnr_bytes_', PIPELINE_ID)) |
| 27 | + |
| 28 | +CONTROLBYTES_PRIV(DEF_RTNR_PRIV, |
| 29 | +` bytes "0x53,0x4f,0x46,0x00,0x00,0x00,0x00,0x00,' |
| 30 | +` 0x20,0x00,0x00,0x00,0x00,0x30,0x01,0x03,' |
| 31 | +` 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,' |
| 32 | +` 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,' |
| 33 | +` 0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,' |
| 34 | +` 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,' |
| 35 | +` 0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,' |
| 36 | +` 0x80,0xbb,0x00,0x00,0x00,0x00,0x00,0x00"' |
| 37 | +) |
| 38 | + |
| 39 | +# RTNR Bytes control with max value of 255 |
| 40 | +C_CONTROLBYTES(DEF_RTNR_BYTES, PIPELINE_ID, |
| 41 | + CONTROLBYTES_OPS(bytes, 258 binds the mixer control to bytes get/put handlers, 258, 258), |
| 42 | + CONTROLBYTES_EXTOPS(258 binds the mixer control to bytes get/put handlers, 258, 258), |
| 43 | + , , , |
| 44 | + CONTROLBYTES_MAX(, 256), |
| 45 | + , |
| 46 | + DEF_RTNR_PRIV) |
| 47 | + |
| 48 | + |
| 49 | +# |
| 50 | +# Components and Buffers |
| 51 | +# |
| 52 | + |
| 53 | +# Host "Capture" PCM |
| 54 | +# with 0 sink and 2 source periods |
| 55 | +W_PCM_CAPTURE(PCM_ID, Capture, 0, 2, SCHEDULE_CORE) |
| 56 | + |
| 57 | +# "RTNR 0" has 2 sink period and 2 source periods |
| 58 | +W_RTNR(0, PIPELINE_FORMAT, 2, DAI_PERIODS, SCHEDULE_CORE, LIST(` ', "DEF_RTNR_BYTES")) |
| 59 | + |
| 60 | +# Capture Buffers |
| 61 | +W_BUFFER(0, COMP_BUFFER_SIZE(4, |
| 62 | + COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, |
| 63 | + eval(PCM_MAX_RATE / SCHEDULE_PERIOD)), PLATFORM_PASS_MEM_CAP) |
| 64 | + |
| 65 | +W_BUFFER(1, COMP_BUFFER_SIZE(4, |
| 66 | + COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, |
| 67 | + eval(PCM_MAX_RATE / SCHEDULE_PERIOD)), PLATFORM_PASS_MEM_CAP) |
| 68 | + |
| 69 | +P_GRAPH(pipe-rtnr-capture-PIPELINE_ID, PIPELINE_ID, |
| 70 | + LIST(` ', |
| 71 | + `dapm(N_PCMC(PCM_ID), N_BUFFER(1))', |
| 72 | + `dapm(N_BUFFER(1), N_RTNR(0))', |
| 73 | + `dapm(N_RTNR(0), N_BUFFER(0))')) |
| 74 | + |
| 75 | +# |
| 76 | +# Pipeline Source and Sinks |
| 77 | +# |
| 78 | +indir(`define', concat(`PIPELINE_SINK_', PIPELINE_ID), N_BUFFER(0)) |
| 79 | +indir(`define', concat(`PIPELINE_PCM_', PIPELINE_ID), Capture PCM_ID) |
| 80 | + |
| 81 | +# |
| 82 | +# PCM Configuration |
| 83 | +# |
| 84 | + |
| 85 | +PCM_CAPABILITIES(Capture PCM_ID, CAPABILITY_FORMAT_NAME(PIPELINE_FORMAT), |
| 86 | + PCM_MIN_RATE, PCM_MAX_RATE, PIPELINE_CHANNELS, PIPELINE_CHANNELS, |
| 87 | + 2, 16, 192, 16384, RTNR_BUFFER_SIZE_MIN, RTNR_BUFFER_SIZE_MAX) |
| 88 | + |
| 89 | +undefine(`DEF_RTNR_PRIV') |
| 90 | +undefine(`DEF_RTNR_BYTES') |
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