memory: add support for L1 DRAM

mrajwa · lgirdwood · commit 0d35bf84f3e9 · 2021-08-03T11:46:45.000+01:00
This patch adds support for L1 DRAM memory. If this
memory is available bootloader will try to power up
as many banks of L1 DRAM memory as the platform supports.

Signed-off-by: Marcin Rajwa &lt;marcin.rajwa@linux.intel.com&gt;
diff --git a/src/include/sof/trace/trace.h b/src/include/sof/trace/trace.h
@@ -38,6 +38,7 @@ struct tr_ctx;
 #define TRACE_BOOT_LDR_HPSRAM		0x110
 #define TRACE_BOOT_LDR_MANIFEST		0x120
 #define TRACE_BOOT_LDR_LPSRAM		0x130
+#define TRACE_BOOT_LDR_L1DRAM		0x140
 #define TRACE_BOOT_LDR_JUMP		0x150
 
 #define TRACE_BOOT_LDR_PARSE_MODULE	0x210
diff --git a/src/platform/intel/cavs/boot_loader.c b/src/platform/intel/cavs/boot_loader.c
@@ -229,6 +229,13 @@ void boot_primary_core(void)
 						true);
 #endif
 
+#if CONFIG_L1_DRAM
+	/* Power ON L1 DRAM memory */
+	trace_point(TRACE_BOOT_LDR_L1DRAM);
+	cavs_pm_memory_l1_dram_banks_power_gate(CONFIG_L1_DRAM_MEMORY_BANKS - 1,
+						0, true);
+#endif
+
 	/* parse manifest and copy modules */
 	trace_point(TRACE_BOOT_LDR_MANIFEST);
 	parse_manifest();
diff --git a/src/platform/intel/cavs/include/cavs/lib/pm_memory.h b/src/platform/intel/cavs/include/cavs/lib/pm_memory.h
@@ -154,4 +154,31 @@ void cavs_pm_memory_lp_sram_power_gate(void *ptr, uint32_t size, bool enabled);
 
 #endif /* CONFIG_LP_SRAM */
 
+#if CONFIG_L1_DRAM
+
+static inline void cavs_pm_memory_l1_dram_banks_power_gate(
+	uint32_t start_bank_id, uint32_t ending_bank_id, bool enable)
+{
+	uint32_t mask = MASK(start_bank_id, ending_bank_id);
+	uint32_t pgctl = io_reg_read(L1_MEM_DRAM_PGCTL);
+	uint32_t expected = enable ? 0 : mask;
+	uint32_t delay = 0;
+
+	if (enable)
+		pgctl &= ~mask;
+	else
+		pgctl |= mask;
+
+	io_reg_write(L1_MEM_DRAM_PGCTL, pgctl);
+
+	while ((io_reg_read(L1_MEM_DRAM_PGISTS) & mask) != expected) {
+		idelay(MEMORY_POWER_CHANGE_DELAY);
+		delay += MEMORY_POWER_CHANGE_DELAY;
+		if (delay >= MEMORY_POWER_CHANGE_TIMEOUT)
+			platform_panic(SOF_IPC_PANIC_MEM);
+	}
+}
+
+#endif /* CONFIG_L1_DRAM */
+
 #endif /* __CAVS_LIB_PM_MEMORY_H__ */
diff --git a/src/platform/tigerlake/include/platform/lib/memory.h b/src/platform/tigerlake/include/platform/lib/memory.h
@@ -449,6 +449,14 @@
 #define BOOT_LDR_STACK_BASE		HEAP_HP_BUFFER_BASE
 #define BOOT_LDR_STACK_SIZE		SOF_STACK_TOTAL_SIZE
 
+/* L1 memory */
+#define L1_MEM_BASE			0x9F000000
+#define L1_DRAM_SIZE			(CONFIG_L1_DRAM_BANKS * CONFIG_L1_DRAM_BANK_SIZE)
+#define L1_MEM_REG_BASE			0x9F080000
+#define L1_MEM_CAP			(L1_MEM_REG_BASE + 0x00)
+#define L1_MEM_DRAM_PGCTL		(L1_MEM_REG_BASE + 0x20)
+#define L1_MEM_DRAM_PGISTS		(L1_MEM_REG_BASE + 0x28)
+
 /* L1 init */
 #define L1CC_ADDR			(0x9F080080)
 #define CxL1CCAP			(L1CC_ADDR + 0x0000)
