forked from thesofproject/sof
-
Notifications
You must be signed in to change notification settings - Fork 0
Expand file tree
/
Copy pathmu.h
More file actions
107 lines (88 loc) · 2.72 KB
/
mu.h
File metadata and controls
107 lines (88 loc) · 2.72 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
/* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright(c) 2019 Intel Corporation. All rights reserved.
* Copyright 2020 NXP
*
* Author: Tomasz Lauda <tomasz.lauda@linux.intel.com>
* Author: Daniel Baluta <daniel.baluta@nxp.com>
*/
#ifndef __SOF_DRIVERS_MU_H__
#define __SOF_DRIVERS_MU_H__
#include <rtos/bit.h>
#include <rtos/clk.h>
#include <stdint.h>
enum imx_mu_type {
IMX_MU_V1,
IMX_MU_V2,
};
#if defined(CONFIG_IMX8ULP) || defined(CONFIG_IMX93_A55)
#define IMX_MU_VERSION IMX_MU_V2
#else
#define IMX_MU_VERSION IMX_MU_V1
#endif
enum imx_mu_xcr {
IMX_MU_GIER = 0x110,
IMX_MU_GCR = 0x114,
IMX_MU_TCR = 0x120,
IMX_MU_RCR = 0x128,
};
enum imx_mu_xsr {
IMX_MU_SR = 0x0c,
IMX_MU_GSR = 0x118,
IMX_MU_TSR = 0x124,
IMX_MU_RSR = 0x12c,
};
#if defined(CONFIG_IMX8ULP) || defined(CONFIG_IMX93_A55)
/* Transmit Register */
#define IMX_MU_xTRn(x) (0x200 + 4 * (x))
/* Receive Register */
#define IMX_MU_xRRn(x) (0x280 + 4 * (x))
#else
/* Transmit Register */
#define IMX_MU_xTRn(x) (0x00 + 4 * (x))
/* Receive Register */
#define IMX_MU_xRRn(x) (0x10 + 4 * (x))
#endif
/* Status Register */
#define IMX_MU_xSR(type, index) (type == IMX_MU_V2 ? index : 0x20)
#define IMX_MU_xSR_GIPn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x))))
#define IMX_MU_xSR_RFn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
#define IMX_MU_xSR_TEn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x))))
#define IMX_MU_xSR_BRDIP BIT(9)
/* Control Register */
#define IMX_MU_xCR(type, index) (type == IMX_MU_V2 ? index : 0x24)
/* General Purpose Interrupt Enable */
#define IMX_MU_xCR_GIEn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x))))
/* Receive Interrupt Enable */
#define IMX_MU_xCR_RIEn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
/* Transmit Interrupt Enable */
#define IMX_MU_xCR_TIEn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x))))
/* General Purpose Interrupt Request */
#define IMX_MU_xCR_GIRn(type, x) (type == IMX_MU_V2 ? BIT(x) : BIT(16 + (3 - (x))))
static inline uint32_t imx_mu_read(uint32_t reg)
{
return *((volatile uint32_t*)(MU_BASE + reg));
}
static inline void imx_mu_write(uint32_t val, uint32_t reg)
{
*((volatile uint32_t*)(MU_BASE + reg)) = val;
}
static inline uint32_t imx_mu_xcr_rmw(int type, int idx, uint32_t set, uint32_t clr)
{
volatile uint32_t val;
val = imx_mu_read(IMX_MU_xCR(type, idx));
val &= ~clr;
val |= set;
imx_mu_write(val, IMX_MU_xCR(type, idx));
return val;
}
static inline uint32_t imx_mu_xsr_rmw(int type, int idx, uint32_t set, uint32_t clr)
{
volatile uint32_t val;
val = imx_mu_read(IMX_MU_xSR(type, idx));
val &= ~clr;
val |= set;
imx_mu_write(val, IMX_MU_xSR(type, idx));
return val;
}
#endif /* __SOF_DRIVERS_MU_H__ */