Skip to content

Commit b7fb41e

Browse files
socovajwebkit-commit-queue
socovaj
authored and
webkit-commit-queue
committed
Source/JavaScriptCore:
[MIPS][JSC] Implement MacroAssembler::probe support on MIPS https://bugs.webkit.org/show_bug.cgi?id=175447 Patch by Stanislav Ocovaj <stanislav.ocovaj@rt-rk.com> on 2017-11-29 Reviewed by Carlos Alberto Lopez Perez. This patch allows DFG JIT to be enabled on MIPS platforms. * Sources.txt: * assembler/MIPSAssembler.h: (JSC::MIPSAssembler::lastSPRegister): (JSC::MIPSAssembler::numberOfSPRegisters): (JSC::MIPSAssembler::sprName): * assembler/MacroAssemblerMIPS.cpp: Added. (JSC::MacroAssembler::probe): * assembler/ProbeContext.cpp: (JSC::Probe::executeProbe): * assembler/ProbeContext.h: (JSC::Probe::CPUState::pc): * assembler/testmasm.cpp: (JSC::isSpecialGPR): (JSC::testProbePreservesGPRS): (JSC::testProbeModifiesStackPointer): (JSC::testProbeModifiesStackValues): Source/WTF: [DFG][MIPS] Enable DFG JIT on MIPS. https://bugs.webkit.org/show_bug.cgi?id=175447 Patch by Stanislav Ocovaj <stanislav.ocovaj@rt-rk.com> on 2017-11-29 Reviewed by Carlos Alberto Lopez Perez. * wtf/Platform.h: Canonical link: https://commits.webkit.org/196145@main git-svn-id: https://svn.webkit.org/repository/webkit/trunk@225286 268f45cc-cd09-0410-ab3c-d52691b4dbfc
1 parent c3a4eb3 commit b7fb41e

9 files changed

Lines changed: 666 additions & 8 deletions

File tree

‎Source/JavaScriptCore/ChangeLog‎

100644100755
Lines changed: 26 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,29 @@
1+
2017-11-29 Stanislav Ocovaj <stanislav.ocovaj@rt-rk.com>
2+
3+
[MIPS][JSC] Implement MacroAssembler::probe support on MIPS
4+
https://bugs.webkit.org/show_bug.cgi?id=175447
5+
6+
Reviewed by Carlos Alberto Lopez Perez.
7+
8+
This patch allows DFG JIT to be enabled on MIPS platforms.
9+
10+
* Sources.txt:
11+
* assembler/MIPSAssembler.h:
12+
(JSC::MIPSAssembler::lastSPRegister):
13+
(JSC::MIPSAssembler::numberOfSPRegisters):
14+
(JSC::MIPSAssembler::sprName):
15+
* assembler/MacroAssemblerMIPS.cpp: Added.
16+
(JSC::MacroAssembler::probe):
17+
* assembler/ProbeContext.cpp:
18+
(JSC::Probe::executeProbe):
19+
* assembler/ProbeContext.h:
20+
(JSC::Probe::CPUState::pc):
21+
* assembler/testmasm.cpp:
22+
(JSC::isSpecialGPR):
23+
(JSC::testProbePreservesGPRS):
24+
(JSC::testProbeModifiesStackPointer):
25+
(JSC::testProbeModifiesStackValues):
26+
127
2017-11-28 JF Bastien <jfbastien@apple.com>
228

329
Strict and sloppy functions shouldn't share structure

‎Source/JavaScriptCore/Sources.txt‎

100644100755
Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -47,6 +47,7 @@ assembler/MacroAssemblerARM.cpp
4747
assembler/MacroAssemblerARM64.cpp
4848
assembler/MacroAssemblerARMv7.cpp
4949
assembler/MacroAssemblerCodeRef.cpp
50+
assembler/MacroAssemblerMIPS.cpp
5051
assembler/MacroAssemblerPrinter.cpp
5152
assembler/MacroAssemblerX86Common.cpp
5253
assembler/Printer.cpp

‎Source/JavaScriptCore/assembler/MIPSAssembler.h‎

100644100755
Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -113,7 +113,8 @@ typedef enum {
113113
fccr = 25,
114114
fexr = 26,
115115
fenr = 28,
116-
fcsr = 31
116+
fcsr = 31,
117+
pc
117118
} SPRegisterID;
118119

119120
typedef enum {
@@ -165,8 +166,8 @@ class MIPSAssembler {
165166
static constexpr unsigned numberOfRegisters() { return lastRegister() - firstRegister() + 1; }
166167

167168
static constexpr SPRegisterID firstSPRegister() { return MIPSRegisters::fir; }
168-
static constexpr SPRegisterID lastSPRegister() { return MIPSRegisters::fcsr; }
169-
static constexpr unsigned numberOfSPRegisters() { return 5; }
169+
static constexpr SPRegisterID lastSPRegister() { return MIPSRegisters::pc; }
170+
static constexpr unsigned numberOfSPRegisters() { return lastSPRegister() - firstSPRegister() + 1; }
170171

171172
static constexpr FPRegisterID firstFPRegister() { return MIPSRegisters::f0; }
172173
static constexpr FPRegisterID lastFPRegister() { return MIPSRegisters::f31; }
@@ -197,6 +198,8 @@ class MIPSAssembler {
197198
return "fenr";
198199
case MIPSRegisters::fcsr:
199200
return "fcsr";
201+
case MIPSRegisters::pc:
202+
return "pc";
200203
default:
201204
RELEASE_ASSERT_NOT_REACHED();
202205
}

‎Source/JavaScriptCore/assembler/MacroAssemblerMIPS.cpp‎

Lines changed: 577 additions & 0 deletions
Large diffs are not rendered by default.

‎Source/JavaScriptCore/assembler/ProbeContext.cpp‎

100644100755
Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -40,6 +40,10 @@ void executeProbe(State* state)
4040
auto& cpu = context.cpu;
4141
void* originalLR = cpu.gpr<void*>(ARM64Registers::lr);
4242
void* originalPC = cpu.pc();
43+
#elif CPU(MIPS)
44+
auto& cpu = context.cpu;
45+
void* originalRA = cpu.gpr<void*>(MIPSRegisters::ra);
46+
void* originalPC = cpu.pc();
4347
#endif
4448

4549
state->initializeStackFunction = nullptr;
@@ -49,6 +53,9 @@ void executeProbe(State* state)
4953
#if CPU(ARM64)
5054
// The ARM64 probe trampoline does not support changing both lr and pc.
5155
RELEASE_ASSERT(originalPC == cpu.pc() || originalLR == cpu.gpr<void*>(ARM64Registers::lr));
56+
#elif CPU(MIPS)
57+
// The MIPS probe trampoline does not support changing both ra and pc.
58+
RELEASE_ASSERT(originalPC == cpu.pc() || originalRA == cpu.gpr<void*>(MIPSRegisters::ra));
5259
#endif
5360

5461
if (context.hasWritesToFlush()) {

‎Source/JavaScriptCore/assembler/ProbeContext.h‎

100644100755
Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -115,7 +115,7 @@ inline void*& CPUState::pc()
115115
#elif CPU(ARM_THUMB2) || CPU(ARM_TRADITIONAL)
116116
return *reinterpret_cast<void**>(&gpr(ARMRegisters::pc));
117117
#elif CPU(MIPS)
118-
RELEASE_ASSERT_NOT_REACHED();
118+
return *reinterpret_cast<void**>(&spr(MIPSRegisters::pc));
119119
#else
120120
#error "Unsupported CPU"
121121
#endif

‎Source/JavaScriptCore/assembler/testmasm.cpp‎

100644100755
Lines changed: 34 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -135,6 +135,9 @@ bool isSpecialGPR(MacroAssembler::RegisterID id)
135135
#if CPU(ARM64)
136136
if (id == ARM64Registers::x18)
137137
return true;
138+
#elif CPU(MIPS)
139+
if (id == MIPSRegisters::zero || id == MIPSRegisters::k0 || id == MIPSRegisters::k1)
140+
return true;
138141
#endif
139142
return false;
140143
}
@@ -400,6 +403,9 @@ void testProbePreservesGPRS()
400403
CHECK_EQ(cpu.gpr(id), testWord(id));
401404
}
402405
for (auto id = CCallHelpers::firstFPRegister(); id <= CCallHelpers::lastFPRegister(); id = nextID(id))
406+
#if CPU(MIPS)
407+
if (!(id & 1))
408+
#endif
403409
CHECK_EQ(cpu.fpr<uint64_t>(id), testWord64(id));
404410
});
405411

@@ -426,6 +432,9 @@ void testProbePreservesGPRS()
426432
CHECK_EQ(cpu.gpr(id), originalState.gpr(id));
427433
}
428434
for (auto id = CCallHelpers::firstFPRegister(); id <= CCallHelpers::lastFPRegister(); id = nextID(id))
435+
#if CPU(MIPS)
436+
if (!(id & 1))
437+
#endif
429438
CHECK_EQ(cpu.fpr<uint64_t>(id), originalState.fpr<uint64_t>(id));
430439
});
431440

@@ -441,7 +450,9 @@ void testProbeModifiesStackPointer(WTF::Function<void*(Probe::Context&)> compute
441450
CPUState originalState;
442451
void* originalSP { nullptr };
443452
void* modifiedSP { nullptr };
453+
#if !(CPU(MIPS))
444454
uintptr_t modifiedFlags { 0 };
455+
#endif
445456

446457
#if CPU(X86) || CPU(X86_64)
447458
auto flagsSPR = X86Registers::eflags;
@@ -473,9 +484,11 @@ void testProbeModifiesStackPointer(WTF::Function<void*(Probe::Context&)> compute
473484
cpu.fpr(id) = bitwise_cast<double>(testWord64(id));
474485
}
475486

487+
#if !(CPU(MIPS))
476488
originalState.spr(flagsSPR) = cpu.spr(flagsSPR);
477489
modifiedFlags = originalState.spr(flagsSPR) ^ flagsMask;
478490
cpu.spr(flagsSPR) = modifiedFlags;
491+
#endif
479492

480493
originalSP = cpu.sp();
481494
modifiedSP = computeModifiedStackPointer(context);
@@ -496,8 +509,13 @@ void testProbeModifiesStackPointer(WTF::Function<void*(Probe::Context&)> compute
496509
CHECK_EQ(cpu.gpr(id), testWord(id));
497510
}
498511
for (auto id = CCallHelpers::firstFPRegister(); id <= CCallHelpers::lastFPRegister(); id = nextID(id))
512+
#if CPU(MIPS)
513+
if (!(id & 1))
514+
#endif
499515
CHECK_EQ(cpu.fpr<uint64_t>(id), testWord64(id));
516+
#if !(CPU(MIPS))
500517
CHECK_EQ(cpu.spr(flagsSPR) & flagsMask, modifiedFlags & flagsMask);
518+
#endif
501519
CHECK_EQ(cpu.sp(), modifiedSP);
502520
});
503521

@@ -512,7 +530,9 @@ void testProbeModifiesStackPointer(WTF::Function<void*(Probe::Context&)> compute
512530
}
513531
for (auto id = CCallHelpers::firstFPRegister(); id <= CCallHelpers::lastFPRegister(); id = nextID(id))
514532
cpu.fpr(id) = originalState.fpr(id);
533+
#if !(CPU(MIPS))
515534
cpu.spr(flagsSPR) = originalState.spr(flagsSPR);
535+
#endif
516536
cpu.sp() = originalSP;
517537
});
518538

@@ -526,8 +546,13 @@ void testProbeModifiesStackPointer(WTF::Function<void*(Probe::Context&)> compute
526546
CHECK_EQ(cpu.gpr(id), originalState.gpr(id));
527547
}
528548
for (auto id = CCallHelpers::firstFPRegister(); id <= CCallHelpers::lastFPRegister(); id = nextID(id))
549+
#if CPU(MIPS)
550+
if (!(id & 1))
551+
#endif
529552
CHECK_EQ(cpu.fpr<uint64_t>(id), originalState.fpr<uint64_t>(id));
553+
#if !(CPU(MIPS))
530554
CHECK_EQ(cpu.spr(flagsSPR) & flagsMask, originalState.spr(flagsSPR) & flagsMask);
555+
#endif
531556
CHECK_EQ(cpu.sp(), originalSP);
532557
});
533558

@@ -640,9 +665,11 @@ void testProbeModifiesStackValues()
640665
originalState.fpr(id) = cpu.fpr(id);
641666
cpu.fpr(id) = bitwise_cast<double>(testWord64(id));
642667
}
668+
#if !(CPU(MIPS))
643669
originalState.spr(flagsSPR) = cpu.spr(flagsSPR);
644670
modifiedFlags = originalState.spr(flagsSPR) ^ flagsMask;
645671
cpu.spr(flagsSPR) = modifiedFlags;
672+
#endif
646673

647674
// Ensure that we'll be writing over the regions of the stack where the Probe::State is.
648675
originalSP = cpu.sp();
@@ -676,8 +703,13 @@ void testProbeModifiesStackValues()
676703
CHECK_EQ(cpu.gpr(id), testWord(id));
677704
}
678705
for (auto id = CCallHelpers::firstFPRegister(); id <= CCallHelpers::lastFPRegister(); id = nextID(id))
706+
#if CPU(MIPS)
707+
if (!(id & 1))
708+
#endif
679709
CHECK_EQ(cpu.fpr<uint64_t>(id), testWord64(id));
710+
#if !(CPU(MIPS))
680711
CHECK_EQ(cpu.spr(flagsSPR) & flagsMask, modifiedFlags & flagsMask);
712+
#endif
681713
CHECK_EQ(cpu.sp(), newSP);
682714

683715
// Validate the stack values.
@@ -701,7 +733,9 @@ void testProbeModifiesStackValues()
701733
}
702734
for (auto id = CCallHelpers::firstFPRegister(); id <= CCallHelpers::lastFPRegister(); id = nextID(id))
703735
cpu.fpr(id) = originalState.fpr(id);
736+
#if !(CPU(MIPS))
704737
cpu.spr(flagsSPR) = originalState.spr(flagsSPR);
738+
#endif
705739
cpu.sp() = originalSP;
706740
});
707741

‎Source/WTF/ChangeLog‎

100644100755
Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,12 @@
1+
2017-11-29 Stanislav Ocovaj <stanislav.ocovaj@rt-rk.com>
2+
3+
[DFG][MIPS] Enable DFG JIT on MIPS.
4+
https://bugs.webkit.org/show_bug.cgi?id=175447
5+
6+
Reviewed by Carlos Alberto Lopez Perez.
7+
8+
* wtf/Platform.h:
9+
110
2017-11-14 Carlos Garcia Campos <cgarcia@igalia.com>
211

312
Move JSONValues to WTF and convert uses of InspectorValues.h to JSONValues.h

‎Source/WTF/wtf/Platform.h‎

100644100755
Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -803,9 +803,10 @@
803803
#if CPU(ARM_TRADITIONAL)
804804
#define ENABLE_DFG_JIT 1
805805
#endif
806-
/* FIXME: MIPS cannot enable the DFG until it has support for MacroAssembler::probe().
807-
https://bugs.webkit.org/show_bug.cgi?id=175447
808-
*/
806+
/* Enable the DFG JIT on MIPS. */
807+
#if CPU(MIPS)
808+
#define ENABLE_DFG_JIT 1
809+
#endif
809810
#endif
810811

811812
/* Concurrent JS only works on 64-bit platforms because it requires that
@@ -824,7 +825,7 @@
824825
#define ENABLE_FAST_TLS_JIT 1
825826
#endif
826827

827-
#if CPU(X86) || CPU(X86_64) || CPU(ARM_THUMB2) || CPU(ARM64) || CPU(ARM_TRADITIONAL)
828+
#if CPU(X86) || CPU(X86_64) || CPU(ARM_THUMB2) || CPU(ARM64) || CPU(ARM_TRADITIONAL) || CPU(MIPS)
828829
#define ENABLE_MASM_PROBE 1
829830
#else
830831
#define ENABLE_MASM_PROBE 0

0 commit comments

Comments
 (0)