radu7
diff --git a/‎SigmaDelta_DAC/circuit/DUO_LX9/papilio_duo_lx9.bit‎
0 Bytes b/‎SigmaDelta_DAC/circuit/DUO_LX9/papilio_duo_lx9.bit‎
0 Bytes
diff --git a/‎SigmaDelta_DAC/circuit/LX9/papilio_pro.bit‎
0 Bytes b/‎SigmaDelta_DAC/circuit/LX9/papilio_pro.bit‎
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diff --git a/‎SigmaDelta_DAC/circuit/PSL_Papilio_DUO_LX9.xise‎
Lines changed: 717 additions & 10 deletions b/‎SigmaDelta_DAC/circuit/PSL_Papilio_DUO_LX9.xise‎
Lines changed: 717 additions & 10 deletions
diff --git a/‎SigmaDelta_DAC/circuit/PSL_Papilio_Pro_LX9.xise‎
Lines changed: 915 additions & 12 deletions b/‎SigmaDelta_DAC/circuit/PSL_Papilio_Pro_LX9.xise‎
Lines changed: 915 additions & 12 deletions
diff --git a/‎libraries/ZPUino_Wishbone_Peripherals/dac_simplesd.vhd‎
Lines changed: 51 additions & 0 deletions b/‎libraries/ZPUino_Wishbone_Peripherals/dac_simplesd.vhd‎
Lines changed: 51 additions & 0 deletions
diff --git a/‎libraries/ZPUino_Wishbone_Peripherals/zpuino_sigmadelta.vhd‎
Lines changed: 15 additions & 4 deletions b/‎libraries/ZPUino_Wishbone_Peripherals/zpuino_sigmadelta.vhd‎
Lines changed: 15 additions & 4 deletions
@@ -0,0 +1,51 @@
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity dac_simplesd is
+  generic (
+    nbits : integer := 9);
+  port (
+    din     : in  signed((nbits-1) downto 0);
+    dout    : out std_logic;
+    clk     : in  std_logic;
+    clk_ena : in  std_logic;
+    rst     : in  std_logic);
+end entity dac_simplesd;
+
+architecture behave of dac_simplesd is
+
+  signal sigma_latch: unsigned(nbits+1 downto 0);
+
+begin
+
+process(clk)
+  variable delta_b:     unsigned(nbits+1 downto 0);
+  variable delta_adder: unsigned(nbits+1 downto 0);
+  variable sigma_adder: unsigned(nbits+1 downto 0);
+  variable data:        unsigned(nbits+1 downto 0);
+begin
+
+  if rising_edge(clk) then
+   if rst='1' then
+      sigma_latch <= (others => '0');
+		  sigma_latch(sigma_latch'high) <= '1';
+		  dout <= '0';
+	  else
+      if clk_ena='1' then
+        delta_b(nbits+1) := sigma_latch(nbits+1);
+        delta_b(nbits)   := sigma_latch(nbits+1);
+        delta_b(nbits-1 downto 0) := (others => '0');
+        data(nbits+1 downto nbits) := "00";
+        data(nbits-1) := not din(nbits-1);
+        data(nbits-2 downto 0) := unsigned(din(nbits-2 downto 0));
+        delta_adder := data + delta_b;
+        sigma_adder := delta_adder + sigma_latch;
+    	  sigma_latch <= sigma_adder;
+    		dout <= sigma_latch(sigma_latch'high);
+      end if;
+  	end if;
+  end if;
+end process;
+end behave;
@@ -82,6 +82,17 @@ component dac_dsm3v is
     n_rst   : in  std_logic);
 end component;
 
+component dac_simplesd is
+  generic (
+    nbits : integer := 16);
+  port (
+    din     : in  signed((nbits-1) downto 0);
+    dout    : out std_logic;
+    clk     : in  std_logic;
+    clk_ena : in  std_logic;
+    rst     : in  std_logic);
+end component;
+
 component dac_dsm2v is
   generic (
     nbits : integer := 16);
@@ -198,22 +209,22 @@ begin
   end if;
 end process;
 
-chan0: dac_dsm3v
+chan0: dac_simplesd
   port map (
     din     => sync_dat_q1(15 downto 0),
     dout    => sdout(0),
     clk     => wb_clk_i,
     clk_ena => '1',
-    n_rst   => nrst
+    rst     => wb_rst_i
   );
 
-chan1: dac_dsm3v
+chan1: dac_simplesd
   port map (
     din     => sync_dat_q2(15 downto 0),
     dout    => sdout(1),
     clk     => wb_clk_i,
     clk_ena => '1',
-    n_rst   => nrst
+    rst     => wb_rst_i
   );