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Add eval tests for logic, Rescale, Atan2, Alias, and discrete Delay
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‎tests/evals/test_logic_system.py‎

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########################################################################################
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##
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## Testing logic and comparison block systems
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##
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## Verifies comparison (GreaterThan, LessThan, Equal) and boolean logic
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## (LogicAnd, LogicOr, LogicNot) blocks in full simulation context.
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##
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########################################################################################
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# IMPORTS ==============================================================================
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import unittest
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import numpy as np
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from pathsim import Simulation, Connection
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from pathsim.blocks import (
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Source,
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Constant,
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Scope,
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)
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from pathsim.blocks.logic import (
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GreaterThan,
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LessThan,
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Equal,
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LogicAnd,
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LogicOr,
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LogicNot,
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)
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# TESTCASE =============================================================================
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class TestComparisonSystem(unittest.TestCase):
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"""
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Test comparison blocks in a simulation that compares a sine wave
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against a constant threshold.
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System: Source(sin(t)) → GT/LT/EQ → Scope
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Constant(0) ↗
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Verify: GT outputs 1 when sin(t) > 0, LT outputs 1 when sin(t) < 0
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"""
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def setUp(self):
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Src = Source(lambda t: np.sin(2 * np.pi * t))
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Thr = Constant(0.0)
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self.GT = GreaterThan()
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self.LT = LessThan()
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self.Sco = Scope(labels=["signal", "gt_zero", "lt_zero"])
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blocks = [Src, Thr, self.GT, self.LT, self.Sco]
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connections = [
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Connection(Src, self.GT["a"], self.LT["a"], self.Sco[0]),
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Connection(Thr, self.GT["b"], self.LT["b"]),
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Connection(self.GT, self.Sco[1]),
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Connection(self.LT, self.Sco[2]),
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]
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self.Sim = Simulation(
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blocks,
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connections,
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dt=0.01,
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log=False
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)
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def test_gt_lt_complementary(self):
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"""GT and LT should be complementary (sum to 1) away from zero crossings"""
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self.Sim.run(duration=3.0, reset=True)
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time, [sig, gt, lt] = self.Sco.read()
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#away from zero crossings, GT + LT should be 1 (exactly one is true)
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mask = np.abs(sig) > 0.1
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result = gt[mask] + lt[mask]
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self.assertTrue(np.allclose(result, 1.0),
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"GT and LT should be complementary away from zero crossings")
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def test_gt_matches_positive(self):
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"""GT output should be 1 when signal is clearly positive"""
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self.Sim.run(duration=3.0, reset=True)
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time, [sig, gt, lt] = self.Sco.read()
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mask_pos = sig > 0.2
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self.assertTrue(np.all(gt[mask_pos] == 1.0),
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"GT should be 1 when signal is positive")
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mask_neg = sig < -0.2
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self.assertTrue(np.all(gt[mask_neg] == 0.0),
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"GT should be 0 when signal is negative")
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class TestLogicGateSystem(unittest.TestCase):
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"""
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Test logic gates combining two comparison outputs.
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System: Two sine waves at different frequencies compared against 0,
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then combined with AND/OR/NOT.
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Verify: Logic truth tables hold across the simulation.
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"""
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def setUp(self):
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#two signals with different frequencies so they go in and out of phase
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Src1 = Source(lambda t: np.sin(2 * np.pi * 1.0 * t))
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Src2 = Source(lambda t: np.sin(2 * np.pi * 1.5 * t))
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Zero = Constant(0.0)
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GT1 = GreaterThan()
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GT2 = GreaterThan()
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self.AND = LogicAnd()
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self.OR = LogicOr()
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self.NOT = LogicNot()
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self.Sco = Scope(labels=["gt1", "gt2", "and", "or", "not1"])
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blocks = [Src1, Src2, Zero, GT1, GT2,
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self.AND, self.OR, self.NOT, self.Sco]
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connections = [
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Connection(Src1, GT1["a"]),
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Connection(Src2, GT2["a"]),
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Connection(Zero, GT1["b"], GT2["b"]),
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Connection(GT1, self.AND["a"], self.OR["a"], self.NOT, self.Sco[0]),
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Connection(GT2, self.AND["b"], self.OR["b"], self.Sco[1]),
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Connection(self.AND, self.Sco[2]),
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Connection(self.OR, self.Sco[3]),
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Connection(self.NOT, self.Sco[4]),
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]
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self.Sim = Simulation(
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blocks,
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connections,
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dt=0.01,
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log=False
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)
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def test_and_gate(self):
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"""AND should only be 1 when both inputs are 1"""
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self.Sim.run(duration=5.0, reset=True)
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time, [gt1, gt2, and_out, or_out, not_out] = self.Sco.read()
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#where both are 1, AND should be 1
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both_true = (gt1 == 1.0) & (gt2 == 1.0)
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if np.any(both_true):
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self.assertTrue(np.all(and_out[both_true] == 1.0))
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#where either is 0, AND should be 0
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either_false = (gt1 == 0.0) | (gt2 == 0.0)
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if np.any(either_false):
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self.assertTrue(np.all(and_out[either_false] == 0.0))
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def test_or_gate(self):
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"""OR should be 1 when either input is 1"""
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self.Sim.run(duration=5.0, reset=True)
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time, [gt1, gt2, and_out, or_out, not_out] = self.Sco.read()
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#where both are 0, OR should be 0
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both_false = (gt1 == 0.0) & (gt2 == 0.0)
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if np.any(both_false):
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self.assertTrue(np.all(or_out[both_false] == 0.0))
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#where either is 1, OR should be 1
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either_true = (gt1 == 1.0) | (gt2 == 1.0)
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if np.any(either_true):
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self.assertTrue(np.all(or_out[either_true] == 1.0))
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def test_not_gate(self):
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"""NOT should invert its input"""
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self.Sim.run(duration=5.0, reset=True)
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time, [gt1, gt2, and_out, or_out, not_out] = self.Sco.read()
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#NOT should be inverse of GT1
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self.assertTrue(np.allclose(not_out + gt1, 1.0),
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"NOT should invert its input")
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class TestEqualSystem(unittest.TestCase):
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"""
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Test Equal block detecting when two signals are close.
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System: Source(sin(t)) → Equal ← Source(sin(t + small_offset))
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"""
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def test_equal_detects_match(self):
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"""Equal should output 1 when signals match within tolerance"""
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Src1 = Constant(3.14)
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Src2 = Constant(3.14)
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Eq = Equal(tolerance=0.01)
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Sco = Scope()
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Sim = Simulation(
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blocks=[Src1, Src2, Eq, Sco],
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connections=[
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Connection(Src1, Eq["a"]),
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Connection(Src2, Eq["b"]),
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Connection(Eq, Sco),
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],
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dt=0.1,
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log=False
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)
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Sim.run(duration=1.0, reset=True)
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time, [eq_out] = Sco.read()
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self.assertTrue(np.all(eq_out == 1.0),
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"Equal should output 1 for identical signals")
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def test_equal_detects_mismatch(self):
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"""Equal should output 0 when signals differ"""
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Src1 = Constant(1.0)
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Src2 = Constant(2.0)
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Eq = Equal(tolerance=0.01)
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Sco = Scope()
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Sim = Simulation(
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blocks=[Src1, Src2, Eq, Sco],
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connections=[
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Connection(Src1, Eq["a"]),
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Connection(Src2, Eq["b"]),
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Connection(Eq, Sco),
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],
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dt=0.1,
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log=False
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)
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Sim.run(duration=1.0, reset=True)
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time, [eq_out] = Sco.read()
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self.assertTrue(np.all(eq_out == 0.0),
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"Equal should output 0 for different signals")
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# RUN TESTS LOCALLY ====================================================================
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if __name__ == '__main__':
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unittest.main(verbosity=2)

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