version = "0.22.0"

cc -std=c99 -ffp-contract=off model.c main.c -lm -o model # Compact layout

cc -std=c99 -ffp-contract=off *.c -lm -o model # Library layout (multi-file)

**Floating-point determinism.** The sources carry `#pragma STDC FP_CONTRACT OFF`

so expressions round exactly as written — that is what makes the C trajectory

bit-identical to the fastsim reference (`double` numeric), including the step on

which a scheduled event fires. Clang honors the pragma; **gcc ignores it** and

contracts to FMA under optimization by default, which can shift an

exactly-boundary-aligned event by one step. Pass `-ffp-contract=off` explicitly

(as above) when bit-exact SiL agreement matters; the generated CMake scaffold

sets it for gcc/clang automatically.

Verified classification of every public block against the C code generator. The

issue asks for two things:

1. **All eventful blocks _without an internal solver_ must be handled by codegen.**

2. **All codegen settings must produce SiL-identical results** to the Rust path.

This document covers point 1 (the acceptance gap). Point 2 (numeric parity across

the setting permutations) is the job of the fuzzing harness and is tracked

separately — a block appearing as `OK` below means codegen *emits* C for it, not

yet that the emitted C is bit-for-bit faithful.

Reproduce with:

The tool constructs a representative instance of each block, assembles a minimal

closed sim, snapshots the IR (`sim.to_ir`) to count events / opaque events /

extern blocks / continuous state, and then tries `sim.to_c()`.

| Category | Count | Blocks |

|---|---|---|

| Codegen-accepted | 94 | all the leaf math/source/discrete/filter/LTI blocks, incl. every op-expressible eventful block |

| **Eventful, opaque → rejected (the #48 gap)** | **2** | **`Wrapper`, `PinkNoise`** |

| Internal-solver / extern → rejected (out of scope) | 5 | `AlgebraicConstraint`, `BVP1D`, `FullyImplicitDAE`, `MassMatrixDAE`, `SemiExplicitDAE` |

| Needs external resource (out of scope) | 2 | `CoSimulationFMU`, `ModelExchangeFMU` (need an FMU file; opaque co-sim) |

Both have an op-expressible representation available — they are lowerable, they

just still emit their sampling event as an opaque host closure.

`_trace_wrapper` (`src/pybindings/py/jit.rs`) already JIT-traces `func(u)` into a

`LazyTraced` op-graph. But the scheduled re-evaluation is pushed as a runtime

`Schedule` event whose action is a host closure (`t_evt.call_into`), so the IR

event is `opaque = true` and `collect_events` rejects it

(`src/codegen/system.rs:1319`).

**Fix direction:** express the sampling as an op-expressible discrete event — a

memory (ZOH) slot written by the traced graph in a `Schedule` effect region,

exactly the pattern `SampleHold` / `ZeroOrderHold` already use (both `OK`). The

traced op-graph is in hand, so this is a lowering change, not new math.

Voss-McCartney: `num_octaves` independent random values plus a sample counter;

each sample updates one octave selected by the counter's bit pattern

(`src/blocks/constructors/noise.rs`). The update runs in an opaque event.

**Fix direction:** carry the octaves + counter as memory slots and express the

per-sample octave update as an op-expressible periodic event, reusing the

`fastsim_rand_*` header helpers (the same helpers that already let `WhiteNoise`

and `RandomNumberGenerator` lower). Heavier than `Wrapper` because of the

counter-bit octave selection.

`WhiteNoise` (sampling-period mode), `RandomNumberGenerator`,

`SinusoidalPhaseNoiseSource` and `Chirp*` lower with **zero events**: their sample

is a deterministic pure function of `t` (`out = scale · normal(key(t))`,

`noise.rs`), so there is no event to drop and they are SiL-reproducible by

construction. The `ev=0 / codegen=OK` rows for them are correct, not a silently

dropped event.

`AlgebraicConstraint`, `BVP1D`, `FullyImplicitDAE`, `MassMatrixDAE`,

`SemiExplicitDAE` carry an **internal solver** (Newton / collocation) and are

represented as opaque extern blocks (`extern=1`, `ev=0`); the issue explicitly

excludes internal-solver blocks. The two FMU blocks wrap external co-simulation

binaries and are opaque by nature.

version = "0.22.0"

__version__ = "0.22.0"

/// Returns `None` when the block cannot lower at this width (e.g. a

/// JIT-traced effect whose Python callable does not trace) — the block then

/// surfaces as an opaque extern `Op::Call`, same as any unported block.

Option<std::rc::Rc<dyn Fn(usize) -> Option<crate::blocks::blockops::DiscreteResolved>>>,

.and_then(|b| b(n_in.max(1)))

.map(|(alg, _, _)| alg)

builder: impl Fn(usize) -> Option<crate::blocks::blockops::DiscreteResolved> + 'static,

Some((alg, memory, events))

Some((alg, memory, events))

// Declare the full bit fan-out up front (port i = bit i, LSB..MSB — pathsim

// parity): the IR/codegen output layout is sized from the declared ports, so

// an under-declaration would under-size the signal buffer when not every bit

// is connected (same pattern as TappedDelay).

b.outputs = Register::new(Some(n_bits), None);

// Declare the full bit fan-in up front (port i = bit i, LSB..MSB — pathsim

// parity): the event effect graph reads `("u", n_bits)`, so the input width

// must match even when not every bit is connected (unconnected bits read 0).

b.inputs = Register::new(Some(n_bits), None);

Some((alg, memory, events))

Some((alg, memory, events))

EventSpec::Periodic { .. } => push(format!("k_{suffix}"), "size_t", 1, 8),

EventSpec::Periodic { .. } => 8, // size_t fire count

/// tolerance used by the discrete run loop's end-of-horizon guard.

/// Event-firing slack added to `m->time` in the schedule tests. Zero for

/// `double`/fixed point, where the clock is exact and a strict `<=` fires an

/// event on precisely the step the (double) reference runtime does — the SiL

/// bit-parity contract. For `float`, `m->time` accumulates in single precision

/// and drifts from the double reference, so a half-step slack keeps the fired

/// step aligned with the reference despite the drift.

evt_tol: String,

evt_tol: match opts.numeric {

// Exact clock: strict `<=` fires on the same step as the runtime.

Numeric::Double | Numeric::Fixed { .. } => "0".to_string(),

// Single-precision clock drifts from the double reference; a half-step

// slack keeps the fired step aligned despite the drift.

Numeric::Float => format!("{} * dt", lit(0.5)),

},

// Count of events fired; the next scheduled time is recomputed as

// `phase + k * period` (multiplication), bit-identical to the

// runtime scheduler's `t_start + n * t_period` — an accumulating

// `next += period` would drift and miss the boundary parity.

fields.push(format!(" size_t k_{suffix};"));

inits.push(format!(" m->k_{suffix} = 0;"));

/* No FMA contraction — round exactly as written, matching the reference runtime

(see the note in the model TU). */

#pragma STDC FP_CONTRACT OFF