For now I'm really just looking for confirmation that I'm in the right path. Do we want to revisit qemu-aarch64 or do we start it all from scratch? Note that I removed all the code pointing at oreboot::drivers and the aarch64 emulation target is basically a stub of what it should be doing.

I can see life with qemu + gdb, but there's no output of any kind. Any suggestions on how to add proper PL011 support? There are some crates, but they depend on cortex-m.

@orangecms FYI

Failing due to lack of #728

Codecov Report

All modified and coverable lines are covered by tests ✅

Project coverage is 0.21%. Comparing base (08384ec) to head (1b7a4fa).

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  Files         22      22           
  Lines        938     938           
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  Hits           2       2           
  Misses       936     936           

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Looks perfectly fine to me :)

For QEMU, the approach from what I am thinking of would be to really just have the main stage and test the higher-level features - decompression, running some test payload, and seeing that our setup works fine (whatever it'd be on Arm, for RISC-V it'd be the SBI, etc). Does that make sense to you as well?

If you don't mind, I'd love to take that first commit here already. Would you move that over into another PR? :)

For the PL011, you can use the register block definition from here:
https://github.com/apgoetz/pl011_qemu/blob/master/src/lib.rs

just copy that over, essentially, and implement the embedded HAL trait for it and the oreboot log library:
https://github.com/oreboot/oreboot/blob/main/src/lib/log/src/lib.rs