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deps: V8: cherry-pick 77d515484864
Original commit message: [riscv64] Move explicit specialization into .cc file Building with Gcc-10 causes error "explicit specialization in non-namespace scope". This change fixes it. Bug: v8:12649 Change-Id: I36b2b042b336c2dfd32ba5541fdbbdb8dc8b4fd7 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3473997 Reviewed-by: ji qiu <qiuji@iscas.ac.cn> Commit-Queue: ji qiu <qiuji@iscas.ac.cn> Cr-Commit-Position: refs/heads/main@{#79185} Refs: v8/v8@77d5154 PR-URL: #42067 Refs: v8/v8@b663343 Reviewed-By: Michaël Zasso <targos@protonmail.com> Reviewed-By: Jiawen Geng <technicalcute@gmail.com> Reviewed-By: Richard Lau <rlau@redhat.com> Reviewed-By: Colin Ihrig <cjihrig@gmail.com> Reviewed-By: Mary Marchini <oss@mmarchini.me> Reviewed-By: Juan José Arboleda <soyjuanarbol@gmail.com> Reviewed-By: James M Snell <jasnell@gmail.com> Reviewed-By: Stewart X Addison <sxa@redhat.com>
1 parent 92d6c40 commit 2f7920c

3 files changed

Lines changed: 159 additions & 159 deletions

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‎common.gypi‎

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Original file line numberDiff line numberDiff line change
@@ -36,7 +36,7 @@
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# Reset this number to 0 on major V8 upgrades.
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# Increment by one for each non-official patch applied to deps/v8.
39-
'v8_embedder_string': '-node.14',
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'v8_embedder_string': '-node.15',
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##### V8 defaults for Node.js #####
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‎deps/v8/src/execution/riscv64/simulator-riscv64.cc‎

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@@ -127,6 +127,164 @@ static inline bool is_overlapped_widen(const int astart, int asize,
127127
#define require_align(val, pos) CHECK_EQ(is_aligned(val, pos), true)
128128
#endif
129129

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// RVV
131+
// The following code about RVV was based from:
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// https://github.com/riscv/riscv-isa-sim
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// Copyright (c) 2010-2017, The Regents of the University of California
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// (Regents). All Rights Reserved.
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
138+
// 1. Redistributions of source code must retain the above copyright
139+
// notice, this list of conditions and the following disclaimer.
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// 2. Redistributions in binary form must reproduce the above copyright
141+
// notice, this list of conditions and the following disclaimer in the
142+
// documentation and/or other materials provided with the distribution.
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// 3. Neither the name of the Regents nor the
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// names of its contributors may be used to endorse or promote products
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// derived from this software without specific prior written permission.
146+
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// IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,
148+
// SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS,
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// ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF
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// REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
151+
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// REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED
153+
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
154+
// PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED
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// HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE
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// MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
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template <uint64_t N>
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struct type_usew_t;
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template <>
160+
struct type_usew_t<8> {
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using type = uint8_t;
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};
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template <>
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struct type_usew_t<16> {
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using type = uint16_t;
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};
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template <>
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struct type_usew_t<32> {
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using type = uint32_t;
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};
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template <>
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struct type_usew_t<64> {
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using type = uint64_t;
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};
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template <>
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struct type_usew_t<128> {
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using type = __uint128_t;
182+
};
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template <uint64_t N>
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struct type_sew_t;
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template <>
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struct type_sew_t<8> {
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using type = int8_t;
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};
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template <>
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struct type_sew_t<16> {
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using type = int16_t;
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};
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template <>
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struct type_sew_t<32> {
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using type = int32_t;
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};
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template <>
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struct type_sew_t<64> {
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using type = int64_t;
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};
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template <>
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struct type_sew_t<128> {
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using type = __int128_t;
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};
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#define VV_PARAMS(x) \
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type_sew_t<x>::type& vd = \
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Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), i, true); \
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type_sew_t<x>::type vs1 = Rvvelt<type_sew_t<x>::type>(rvv_vs1_reg(), i); \
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type_sew_t<x>::type vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i);
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#define VV_UPARAMS(x) \
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type_usew_t<x>::type& vd = \
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Rvvelt<type_usew_t<x>::type>(rvv_vd_reg(), i, true); \
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type_usew_t<x>::type vs1 = Rvvelt<type_usew_t<x>::type>(rvv_vs1_reg(), i); \
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type_usew_t<x>::type vs2 = Rvvelt<type_usew_t<x>::type>(rvv_vs2_reg(), i);
222+
223+
#define VX_PARAMS(x) \
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type_sew_t<x>::type& vd = \
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Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), i, true); \
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type_sew_t<x>::type rs1 = (type_sew_t<x>::type)(get_register(rs1_reg())); \
227+
type_sew_t<x>::type vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i);
228+
229+
#define VX_UPARAMS(x) \
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type_usew_t<x>::type& vd = \
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Rvvelt<type_usew_t<x>::type>(rvv_vd_reg(), i, true); \
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type_usew_t<x>::type rs1 = (type_usew_t<x>::type)(get_register(rs1_reg())); \
233+
type_usew_t<x>::type vs2 = Rvvelt<type_usew_t<x>::type>(rvv_vs2_reg(), i);
234+
235+
#define VI_PARAMS(x) \
236+
type_sew_t<x>::type& vd = \
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Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), i, true); \
238+
type_sew_t<x>::type simm5 = (type_sew_t<x>::type)(instr_.RvvSimm5()); \
239+
type_sew_t<x>::type vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i);
240+
241+
#define VI_UPARAMS(x) \
242+
type_usew_t<x>::type& vd = \
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Rvvelt<type_usew_t<x>::type>(rvv_vd_reg(), i, true); \
244+
type_usew_t<x>::type uimm5 = (type_usew_t<x>::type)(instr_.RvvUimm5()); \
245+
type_usew_t<x>::type vs2 = Rvvelt<type_usew_t<x>::type>(rvv_vs2_reg(), i);
246+
247+
#define VN_PARAMS(x) \
248+
constexpr int half_x = x >> 1; \
249+
type_sew_t<half_x>::type& vd = \
250+
Rvvelt<type_sew_t<half_x>::type>(rvv_vd_reg(), i, true); \
251+
type_sew_t<x>::type uimm5 = (type_sew_t<x>::type)(instr_.RvvUimm5()); \
252+
type_sew_t<x>::type vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i);
253+
254+
#define VN_UPARAMS(x) \
255+
constexpr int half_x = x >> 1; \
256+
type_usew_t<half_x>::type& vd = \
257+
Rvvelt<type_usew_t<half_x>::type>(rvv_vd_reg(), i, true); \
258+
type_usew_t<x>::type uimm5 = (type_usew_t<x>::type)(instr_.RvvUimm5()); \
259+
type_sew_t<x>::type vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i);
260+
261+
#define VXI_PARAMS(x) \
262+
type_sew_t<x>::type& vd = \
263+
Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), i, true); \
264+
type_sew_t<x>::type vs1 = Rvvelt<type_sew_t<x>::type>(rvv_vs1_reg(), i); \
265+
type_sew_t<x>::type vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i); \
266+
type_sew_t<x>::type rs1 = (type_sew_t<x>::type)(get_register(rs1_reg())); \
267+
type_sew_t<x>::type simm5 = (type_sew_t<x>::type)(instr_.RvvSimm5());
268+
269+
#define VI_XI_SLIDEDOWN_PARAMS(x, off) \
270+
auto& vd = Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), i, true); \
271+
auto vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i + off);
272+
273+
#define VI_XI_SLIDEUP_PARAMS(x, offset) \
274+
auto& vd = Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), i, true); \
275+
auto vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i - offset);
276+
277+
/* Vector Integer Extension */
278+
#define VI_VIE_PARAMS(x, scale) \
279+
if ((x / scale) < 8) UNREACHABLE(); \
280+
auto& vd = Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), i, true); \
281+
auto vs2 = Rvvelt<type_sew_t<x / scale>::type>(rvv_vs2_reg(), i);
282+
283+
#define VI_VIE_UPARAMS(x, scale) \
284+
if ((x / scale) < 8) UNREACHABLE(); \
285+
auto& vd = Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), i, true); \
286+
auto vs2 = Rvvelt<type_usew_t<x / scale>::type>(rvv_vs2_reg(), i);
287+
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#define require_noover(astart, asize, bstart, bsize) \
131289
CHECK_EQ(!is_overlapped(astart, asize, bstart, bsize), true)
132290
#define require_noover_widen(astart, asize, bstart, bsize) \

‎deps/v8/src/execution/riscv64/simulator-riscv64.h‎

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@@ -652,164 +652,6 @@ class Simulator : public SimulatorBase {
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}
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}
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// RVV
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// The following code about RVV was based from:
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// https://github.com/riscv/riscv-isa-sim
658-
// Copyright (c) 2010-2017, The Regents of the University of California
659-
// (Regents). All Rights Reserved.
660-
661-
// Redistribution and use in source and binary forms, with or without
662-
// modification, are permitted provided that the following conditions are met:
663-
// 1. Redistributions of source code must retain the above copyright
664-
// notice, this list of conditions and the following disclaimer.
665-
// 2. Redistributions in binary form must reproduce the above copyright
666-
// notice, this list of conditions and the following disclaimer in the
667-
// documentation and/or other materials provided with the distribution.
668-
// 3. Neither the name of the Regents nor the
669-
// names of its contributors may be used to endorse or promote products
670-
// derived from this software without specific prior written permission.
671-
672-
// IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,
673-
// SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS,
674-
// ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF
675-
// REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
676-
677-
// REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED
678-
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
679-
// PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED
680-
// HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE
681-
// MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
682-
template <uint64_t N>
683-
struct type_usew_t;
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template <>
685-
struct type_usew_t<8> {
686-
using type = uint8_t;
687-
};
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template <>
690-
struct type_usew_t<16> {
691-
using type = uint16_t;
692-
};
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694-
template <>
695-
struct type_usew_t<32> {
696-
using type = uint32_t;
697-
};
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template <>
700-
struct type_usew_t<64> {
701-
using type = uint64_t;
702-
};
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template <>
705-
struct type_usew_t<128> {
706-
using type = __uint128_t;
707-
};
708-
template <uint64_t N>
709-
struct type_sew_t;
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711-
template <>
712-
struct type_sew_t<8> {
713-
using type = int8_t;
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};
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template <>
717-
struct type_sew_t<16> {
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using type = int16_t;
719-
};
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721-
template <>
722-
struct type_sew_t<32> {
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using type = int32_t;
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};
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template <>
727-
struct type_sew_t<64> {
728-
using type = int64_t;
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};
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731-
template <>
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struct type_sew_t<128> {
733-
using type = __int128_t;
734-
};
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736-
#define VV_PARAMS(x) \
737-
type_sew_t<x>::type& vd = \
738-
Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), i, true); \
739-
type_sew_t<x>::type vs1 = Rvvelt<type_sew_t<x>::type>(rvv_vs1_reg(), i); \
740-
type_sew_t<x>::type vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i);
741-
742-
#define VV_UPARAMS(x) \
743-
type_usew_t<x>::type& vd = \
744-
Rvvelt<type_usew_t<x>::type>(rvv_vd_reg(), i, true); \
745-
type_usew_t<x>::type vs1 = Rvvelt<type_usew_t<x>::type>(rvv_vs1_reg(), i); \
746-
type_usew_t<x>::type vs2 = Rvvelt<type_usew_t<x>::type>(rvv_vs2_reg(), i);
747-
748-
#define VX_PARAMS(x) \
749-
type_sew_t<x>::type& vd = \
750-
Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), i, true); \
751-
type_sew_t<x>::type rs1 = (type_sew_t<x>::type)(get_register(rs1_reg())); \
752-
type_sew_t<x>::type vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i);
753-
754-
#define VX_UPARAMS(x) \
755-
type_usew_t<x>::type& vd = \
756-
Rvvelt<type_usew_t<x>::type>(rvv_vd_reg(), i, true); \
757-
type_usew_t<x>::type rs1 = (type_usew_t<x>::type)(get_register(rs1_reg())); \
758-
type_usew_t<x>::type vs2 = Rvvelt<type_usew_t<x>::type>(rvv_vs2_reg(), i);
759-
760-
#define VI_PARAMS(x) \
761-
type_sew_t<x>::type& vd = \
762-
Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), i, true); \
763-
type_sew_t<x>::type simm5 = (type_sew_t<x>::type)(instr_.RvvSimm5()); \
764-
type_sew_t<x>::type vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i);
765-
766-
#define VI_UPARAMS(x) \
767-
type_usew_t<x>::type& vd = \
768-
Rvvelt<type_usew_t<x>::type>(rvv_vd_reg(), i, true); \
769-
type_usew_t<x>::type uimm5 = (type_usew_t<x>::type)(instr_.RvvUimm5()); \
770-
type_usew_t<x>::type vs2 = Rvvelt<type_usew_t<x>::type>(rvv_vs2_reg(), i);
771-
772-
#define VN_PARAMS(x) \
773-
constexpr int half_x = x >> 1; \
774-
type_sew_t<half_x>::type& vd = \
775-
Rvvelt<type_sew_t<half_x>::type>(rvv_vd_reg(), i, true); \
776-
type_sew_t<x>::type uimm5 = (type_sew_t<x>::type)(instr_.RvvUimm5()); \
777-
type_sew_t<x>::type vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i);
778-
779-
#define VN_UPARAMS(x) \
780-
constexpr int half_x = x >> 1; \
781-
type_usew_t<half_x>::type& vd = \
782-
Rvvelt<type_usew_t<half_x>::type>(rvv_vd_reg(), i, true); \
783-
type_usew_t<x>::type uimm5 = (type_usew_t<x>::type)(instr_.RvvUimm5()); \
784-
type_sew_t<x>::type vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i);
785-
786-
#define VXI_PARAMS(x) \
787-
type_sew_t<x>::type& vd = \
788-
Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), i, true); \
789-
type_sew_t<x>::type vs1 = Rvvelt<type_sew_t<x>::type>(rvv_vs1_reg(), i); \
790-
type_sew_t<x>::type vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i); \
791-
type_sew_t<x>::type rs1 = (type_sew_t<x>::type)(get_register(rs1_reg())); \
792-
type_sew_t<x>::type simm5 = (type_sew_t<x>::type)(instr_.RvvSimm5());
793-
794-
#define VI_XI_SLIDEDOWN_PARAMS(x, off) \
795-
auto& vd = Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), i, true); \
796-
auto vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i + off);
797-
798-
#define VI_XI_SLIDEUP_PARAMS(x, offset) \
799-
auto& vd = Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), i, true); \
800-
auto vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i - offset);
801-
802-
/* Vector Integer Extension */
803-
#define VI_VIE_PARAMS(x, scale) \
804-
if ((x / scale) < 8) UNREACHABLE(); \
805-
auto& vd = Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), i, true); \
806-
auto vs2 = Rvvelt<type_sew_t<x / scale>::type>(rvv_vs2_reg(), i);
807-
808-
#define VI_VIE_UPARAMS(x, scale) \
809-
if ((x / scale) < 8) UNREACHABLE(); \
810-
auto& vd = Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), i, true); \
811-
auto vs2 = Rvvelt<type_usew_t<x / scale>::type>(rvv_vs2_reg(), i);
812-
813655
inline void rvv_trace_vd() {
814656
if (::v8::internal::FLAG_trace_sim) {
815657
__int128_t value = Vregister_[rvv_vd_reg()];

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