@agatti I thought I'd have a go at this, and it turned out pretty easy: the native linker allows direct relocation of memset/memmove, so the trampoline functions for them are very simple.

This should work on Thumb2. Just need to extend it to all other archs. Then we no longer need any special cases to handle these libc functions.

Code size report:

Reference:  tools/ci.sh: Add new Unix target with terse error messages. [5770ced]
Comparison: examples/natmod: Remove memset, memmove, memcpy. [merge of 534cd8d]
  mpy-cross:    +0 +0.000% 
   bare-arm:    +0 +0.000% 
minimal x86:    +0 +0.000% 
   unix x64:    +0 +0.000% standard
      stm32:    +0 +0.000% PYBV10
      esp32:    +0 +0.000% ESP32_GENERIC
     mimxrt:    +0 +0.000% TEENSY40
        rp2:    +0 +0.000% RPI_PICO_W
       samd:    +0 +0.000% ADAFRUIT_ITSYBITSY_M4_EXPRESS
  qemu rv32:    +0 +0.000% VIRT_RV32

Looks interesting! For RV32/RV64 you should get by with this:

AUIPC T6, offset >> 12          # 0x00000F97 | (offset & 0xFFFFF000)
JALR  ZERO, T6, offset & 0xFFF  # 0x000F8067 | ((offset & 0xFFF) << 20)

assuming that T6 can be trashed there (it should, but you never know). There are different opcode sequences depending on the distance between PC and the offset, but this one should always work assuming a ±2GiB range. If you get stuck on RISC-V let me know and I'll look at it.

For RV32/RV64 you should get by with this:

Thanks for the hint, but the runtime linker (in py/persistentcode.c) can only relocate machine-word entries, nothing else. So in the end I used:

auipc a3, 0
c.lw  a3, 8(a3)
c.jr  a3
<word sized absolute pointer to memset/memmove>

(where the absolute pointer is filled in at runtime upon loading the .mpy)

CI is showing that works on RV32, but fails on RV64... not sure why.

I'm on mobile right now but I seem to recall that c.lw won't load the upper 32 bits of the register.

I guess you either need to use another opcode or clear the register beforehand.

I'm on mobile right now but I seem to recall that c.lw won't load the upper 32 bits of the register.

Ah, you're right. LW is sign-extending to 6-bits, LWU is zero-extending. I need to use LD instead on RV64.

Codecov Report

✅ All modified and coverable lines are covered by tests.
✅ Project coverage is 98.51%. Comparing base (5770ced) to head (534cd8d).

@@           Coverage Diff           @@
##           master   #19357   +/-   ##
=======================================
  Coverage   98.51%   98.51%           
=======================================
  Files         176      176           
  Lines       22904    22904           
=======================================
  Hits        22563    22563           
  Misses        341      341           

☔ View full report in Codecov by Harness.
📢 Have feedback on the report? Share it here.