Skip to content

Commit 0e1d857

Browse files
committed
README: Define and describe the port Tier levels.
MicroPython has quite a few ports now (20 of them), but not all are in the same stage of development. This commit attempts to define port Tier levels and assign a Tier to each of the existing ports. The main aim here is to set expectations for the level of support and development each port gets. And also lower the bar of entry for new ports so they can enter at a low Tier and gradually rise up to Tier 1. See prior art here: - https://peps.python.org/pep-0011/ - https://doc.rust-lang.org/rustc/target-tier-policy.html - https://docs.zephyrproject.org/latest/project/release_process.html#hardware-support-tiers Signed-off-by: Damien George <damien@micropython.org> Signed-off-by: Angus Gratton <angus@redyak.com.au>
1 parent 2082a4d commit 0e1d857

3 files changed

Lines changed: 137 additions & 22 deletions

File tree

README.md

Lines changed: 68 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -98,28 +98,74 @@ development and testing of MicroPython itself, as well as providing
9898
lightweight alternative to CPython on these platforms (in particular on
9999
embedded Linux systems).
100100

101-
The ["minimal"](ports/minimal) port provides an example of a very basic
102-
MicroPython port and can be compiled as both a standalone Linux binary as
103-
well as for ARM Cortex M4. Start with this if you want to port MicroPython to
104-
another microcontroller. Additionally the ["bare-arm"](ports/bare-arm) port
105-
is an example of the absolute minimum configuration, and is used to keep
106-
track of the code size of the core runtime and VM.
107-
108-
In addition, the following ports are provided in this repository:
109-
- [cc3200](ports/cc3200) -- Texas Instruments CC3200 (including PyCom WiPy).
110-
- [esp32](ports/esp32) -- Espressif ESP32 SoC (including ESP32S2, ESP32S3, ESP32C3, ESP32C6).
111-
- [esp8266](ports/esp8266) -- Espressif ESP8266 SoC.
112-
- [mimxrt](ports/mimxrt) -- NXP m.iMX RT (including Teensy 4.x).
113-
- [nrf](ports/nrf) -- Nordic Semiconductor nRF51 and nRF52.
114-
- [pic16bit](ports/pic16bit) -- Microchip PIC 16-bit.
115-
- [powerpc](ports/powerpc) -- IBM PowerPC (including Microwatt)
116-
- [qemu](ports/qemu) -- QEMU-based emulated target (for testing)
117-
- [renesas-ra](ports/renesas-ra) -- Renesas RA family.
118-
- [rp2](ports/rp2) -- Raspberry Pi RP2040 (including Pico and Pico W).
119-
- [samd](ports/samd) -- Microchip (formerly Atmel) SAMD21 and SAMD51.
120-
- [stm32](ports/stm32) -- STMicroelectronics STM32 family (including F0, F4, F7, G0, G4, H7, L0, L4, WB)
121-
- [webassembly](ports/webassembly) -- Emscripten port targeting browsers and NodeJS.
122-
- [zephyr](ports/zephyr) -- Zephyr RTOS.
101+
Over twenty different MicroPython ports are provided in this repository,
102+
split across three
103+
[MicroPython Support Tiers](https://docs.micropython.org/en/latest/develop/support_tiers.html).
104+
105+
Tier 1 Ports
106+
============
107+
108+
👑 Ports in [Tier 1](https://docs.micropython.org/en/latest/develop/support_tiers.html)
109+
are mature and have the most active development, support and testing:
110+
111+
| Port | Target | Quick Reference |
112+
|--------------------------|----------------------------------------------------------------------------------------|----------------------------------------------------------------------|
113+
| [esp32](ports/esp32)* | Espressif ESP32 SoCs (ESP32, ESP32S2, ESP32S3, ESP32C3, ESP32C6) | [here](https://docs.micropython.org/en/latest/esp32/quickref.html) |
114+
| [mimxrt](ports/mimxrt) | NXP m.iMX RT | [here](https://docs.micropython.org/en/latest/mimxrt/quickref.html) |
115+
| [rp2](ports/rp2) | Raspberry Pi RP2040 and RP2350 | [here](https://docs.micropython.org/en/latest/rp2/quickref.html) |
116+
| [samd](ports/samd) | Microchip (formerly Atmel) SAMD21 and SAMD51 | [here](https://docs.micropython.org/en/latest/samd/quickref.html) |
117+
| [stm32](ports/stm32) | STMicroelectronics STM32 MCUs (F0, F4, F7, G0, G4, H5, H7, L0, L1, L4, N6, WB, WL) | [here](https://docs.micropython.org/en/latest/pyboard/quickref.html) |
118+
| [unix](ports/unix) | Linux, BSD, macOS, WSL | [here](https://docs.micropython.org/en/latest/unix/quickref.html) |
119+
| [windows](ports/windows) | Microsoft Windows | [here](https://docs.micropython.org/en/latest/unix/quickref.html) |
120+
121+
An asterisk indicates that the port has ongoing financial support from the vendor.
122+
123+
Tier 2 Ports
124+
============
125+
126+
✔ Ports in [Tier 2](https://docs.micropython.org/en/latest/develop/support_tiers.html)
127+
are less mature and less actively developed and tested than Tier 1, but
128+
still fully supported:
129+
130+
| Port | Target | Quick Reference |
131+
|----------------------------------|-------------------------------------------------------------|-------------------------------------------------------------------------|
132+
| [alif](ports/alif) | Alif Semiconductor Ensemble MCUs (E3, E7) | |
133+
| [embed](ports/embed) | Generates a set of .c/.h files for embedding into a project | |
134+
| [nrf](ports/nrf) | Nordic Semiconductor nRF51 and nRF52 | |
135+
| [renesas-ra](ports/renesas-ra) | Renesas RA family | [here](https://docs.micropython.org/en/latest/renesas-ra/quickref.html) |
136+
| [webassembly](ports/webassembly) | Emscripten port targeting browsers and NodeJS | |
137+
| [zephyr](ports/zephyr) | Zephyr RTOS | [here](https://docs.micropython.org/en/latest/zephyr/quickref.html) |
138+
139+
Tier 3 Ports
140+
============
141+
142+
Ports in [Tier 3](https://docs.micropython.org/en/latest/develop/support_tiers.html)
143+
are built in CI but not regularly tested by the MicroPython maintainers:
144+
145+
| Port | Target | Quick Reference |
146+
|----------------------------|-------------------------------------------------------------------|-------------------------------------------------------------------------|
147+
| [cc3200](ports/cc3200) | Texas Instruments CC3200 | [For WiPy](https://docs.micropython.org/en/latest/wipy/quickref.html) |
148+
| [esp8266](ports/esp8266) | Espressif ESP8266 SoC | [here](https://docs.micropython.org/en/latest/esp8266/quickref.html) |
149+
| [pic16bit](ports/pic16bit) | Microchip PIC 16-bit | |
150+
| [powerpc](ports/powerpc) | IBM PowerPC (including Microwatt) | |
151+
152+
Additional Ports
153+
================
154+
155+
In addition to the above there is a Tier M containing ports that are used
156+
primarily for maintenance, development and testing:
157+
158+
- The ["bare-arm"](ports/bare-arm) port is an example of the absolute minimum
159+
configuration that still includes the compiler, and is used to keep track
160+
of the code size of the core runtime and VM.
161+
162+
- The ["minimal"](ports/minimal) port provides an example of a very basic
163+
MicroPython port and can be compiled as both a standalone Linux binary as
164+
well as for ARM Cortex-M4. Start with this if you want to port MicroPython
165+
to another microcontroller.
166+
167+
- The [qemu](ports/qemu) port is a QEMU-based emulated target for Cortex-A,
168+
Cortex-M, RISC-V 32-bit and RISC-V 64-bit architectures.
123169

124170
The MicroPython cross-compiler, mpy-cross
125171
-----------------------------------------

docs/develop/index.rst

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -24,3 +24,4 @@ MicroPython to a new platform and implementing a core MicroPython library.
2424
publiccapi.rst
2525
extendingmicropython.rst
2626
porting.rst
27+
support_tiers.rst

docs/develop/support_tiers.rst

Lines changed: 68 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,68 @@
1+
MicroPython Support Tiers
2+
=========================
3+
4+
MicroPython operates with a set of Support Tier levels for the various ports.
5+
Tiers 1, 2 and 3 are the main Tier levels with Tier 1 being the most mature and
6+
actively maintained. There is also Tier M for additional ports used primarily
7+
for maintenance, development and testing. These Tier levels are defined in the
8+
table below.
9+
10+
.. table::
11+
:widths: 40 9 9 9 9
12+
13+
+-----------------------------------------------+--------+--------+--------+--------+
14+
| | Tier 1 | Tier 2 | Tier 3 | Tier M |
15+
+-----------------------------------------------+--------+--------+--------+--------+
16+
| builds pass under CI |||||
17+
+-----------------------------------------------+--------+--------+--------+--------+
18+
| tests run under CI (where possible) |||||
19+
+-----------------------------------------------+--------+--------+--------+--------+
20+
| actively maintained ||| ||
21+
+-----------------------------------------------+--------+--------+--------+--------+
22+
| stable Python API ||| | |
23+
+-----------------------------------------------+--------+--------+--------+--------+
24+
| new features actively developed ||| | |
25+
+-----------------------------------------------+--------+--------+--------+--------+
26+
| tested on hardware for releases ||| | |
27+
+-----------------------------------------------+--------+--------+--------+--------+
28+
| prioritized bug reports || | ||
29+
+-----------------------------------------------+--------+--------+--------+--------+
30+
| regressions warrant a patch release || | ||
31+
+-----------------------------------------------+--------+--------+--------+--------+
32+
| has port-specific documentation || | | |
33+
+-----------------------------------------------+--------+--------+--------+--------+
34+
35+
Lower Tiers may tick more boxes, but the above table defines the minimum requirements
36+
for a port to belong to a Tier.
37+
38+
Tier 1 ports:
39+
40+
- esp32
41+
- mimxrt
42+
- rp2
43+
- samd
44+
- stm32
45+
- unix
46+
- windows
47+
48+
Tier 2 ports:
49+
50+
- alif
51+
- embed
52+
- nrf
53+
- renesas-ra
54+
- webassembly
55+
- zephyr
56+
57+
Tier 3 ports:
58+
59+
- cc3200
60+
- esp8266
61+
- pic16bit
62+
- powerpc
63+
64+
Tier M ports:
65+
66+
- bare-arm
67+
- minimal
68+
- qemu

0 commit comments

Comments
 (0)