/**

******************************************************************************

* @file stm32f410tx.h

* @author MCD Application Team

* @version V2.5.1

* @date 28-June-2016

* @brief CMSIS STM32F410Tx Device Peripheral Access Layer Header File.

*

* This file contains:

* - Data structures and the address mapping for all peripherals

* - peripherals registers declarations and bits definition

* - Macros to access peripheral’s registers hardware

*

******************************************************************************

* @attention

*

* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>

*

* Redistribution and use in source and binary forms, with or without modification,

* are permitted provided that the following conditions are met:

* 1. Redistributions of source code must retain the above copyright notice,

* this list of conditions and the following disclaimer.

* 2. Redistributions in binary form must reproduce the above copyright notice,

* this list of conditions and the following disclaimer in the documentation

* and/or other materials provided with the distribution.

* 3. Neither the name of STMicroelectronics nor the names of its contributors

* may be used to endorse or promote products derived from this software

* without specific prior written permission.

*

* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE

* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL

* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR

* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER

* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,

* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE

* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

*

******************************************************************************

*/

/** @addtogroup CMSIS

* @{

*/

/** @addtogroup stm32f410tx

* @{

*/

#ifndef __STM32F410Tx_H

#define __STM32F410Tx_H

#ifdef __cplusplus

extern "C" {

#endif /* __cplusplus */

/** @addtogroup Configuration_section_for_CMSIS

* @{

*/

/**

* @brief Configuration of the Cortex-M4 Processor and Core Peripherals

*/

#define __CM4_REV 0x0001U /*!< Core revision r0p1 */

#define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */

#define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */

#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */

#define __FPU_PRESENT 1U /*!< FPU present */

/**

* @}

*/

/** @addtogroup Peripheral_interrupt_number_definition

* @{

*/

/**

* @brief STM32F4XX Interrupt Number Definition, according to the selected device

* in @ref Library_configuration_section

*/

typedef enum

{

/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/

NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */

MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */

BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */

UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */

SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */

DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */

PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */

SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */

/****** STM32 specific Interrupt Numbers **********************************************************************/

WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */

PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */

TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */

RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */

FLASH_IRQn = 4, /*!< FLASH global Interrupt */

RCC_IRQn = 5, /*!< RCC global Interrupt */

EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */

EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */

EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */

EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */

EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */

DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */

DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */

DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */

DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */

DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */

DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */

DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */

ADC_IRQn = 18, /*!< ADC1 global Interrupts */

EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */

TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */

TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */

TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */

TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */

I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */

I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */

I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */

I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */

SPI1_IRQn = 35, /*!< SPI1 global Interrupt */

USART1_IRQn = 37, /*!< USART1 global Interrupt */

USART2_IRQn = 38, /*!< USART2 global Interrupt */

EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */

RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */

DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */

TIM5_IRQn = 50, /*!< TIM5 global Interrupt */

TIM6_DAC_IRQn = 54, /*!< TIM6 global Interrupt and DAC Global Interrupt */

DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */

DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */

DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */

DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */

DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */

DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */

DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */

DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */

RNG_IRQn = 80, /*!< RNG global Interrupt */

FPU_IRQn = 81, /*!< FPU global interrupt */

FMPI2C1_EV_IRQn = 95, /*!< FMPI2C1 Event Interrupt */

FMPI2C1_ER_IRQn = 96, /*!< FMPI2C1 Error Interrupt */

LPTIM1_IRQn = 97 /*!< LPTIM1 interrupt */

} IRQn_Type;

/**

* @}

*/

#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */

#include "system_stm32f4xx.h"

#include <stdint.h>

/** @addtogroup Peripheral_registers_structures

* @{

*/

/**

* @brief Analog to Digital Converter

*/

typedef struct

{

__IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */

__IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */

__IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */

__IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */

__IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */

__IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */

__IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */

__IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */

__IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */

__IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */

__IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */

__IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */

__IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */

__IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */

__IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/

__IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */

__IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */

__IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */

__IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */

__IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */

} ADC_TypeDef;

typedef struct

{

__IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */

__IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */

__IO uint32_t CDR; /*!< ADC common regular data register for dual

AND triple modes, Address offset: ADC1 base address + 0x308 */

} ADC_Common_TypeDef;

/**

* @brief CRC calculation unit

*/

typedef struct

{

__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */

__IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */

uint8_t RESERVED0; /*!< Reserved, 0x05 */

uint16_t RESERVED1; /*!< Reserved, 0x06 */

__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */

} CRC_TypeDef;

/**

* @brief Digital to Analog Converter

*/

typedef struct

{

__IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */

__IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */

__IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */

__IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */

__IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */

__IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */

__IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */

__IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */

__IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */

__IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */

__IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */

__IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */

__IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */

__IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */

} DAC_TypeDef;

/**

* @brief Debug MCU

*/

typedef struct

{

__IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */

__IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */

__IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */

__IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */

}DBGMCU_TypeDef;

/**

* @brief DMA Controller

*/

typedef struct

{

__IO uint32_t CR; /*!< DMA stream x configuration register */

__IO uint32_t NDTR; /*!< DMA stream x number of data register */

__IO uint32_t PAR; /*!< DMA stream x peripheral address register */

__IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */

__IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */

__IO uint32_t FCR; /*!< DMA stream x FIFO control register */

} DMA_Stream_TypeDef;

typedef struct

{

__IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */

__IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */

__IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */

__IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */

} DMA_TypeDef;

/**

* @brief External Interrupt/Event Controller

*/

typedef struct

{

__IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */

__IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */

__IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */

__IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */

__IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */

__IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */

} EXTI_TypeDef;

/**

* @brief FLASH Registers

*/

typedef struct

{

__IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */

__IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */

__IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */

__IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */

__IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */

__IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */

__IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */

} FLASH_TypeDef;

/**

* @brief General Purpose I/O

*/

typedef struct

{

__IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */

__IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */

__IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */

__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */

__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */

__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */

__IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */

__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */

__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */

} GPIO_TypeDef;

/**

* @brief System configuration controller

*/

typedef struct

{

__IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */

__IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */

__IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */

uint32_t RESERVED; /*!< Reserved, 0x18 */

uint32_t CFGR2; /*!< Reserved, 0x1C */

__IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */

uint32_t RESERVED1[2]; /*!< Reserved, 0x24-0x28 */

__IO uint32_t CFGR; /*!< SYSCFG Configuration register, Address offset: 0x2C */

} SYSCFG_TypeDef;

/**

* @brief Inter-integrated Circuit Interface

*/

typedef struct

{

__IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */

__IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */

__IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */

__IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */

__IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */

__IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */

__IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */

__IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */

__IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */

__IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */

} I2C_TypeDef;

/**

* @brief Inter-integrated Circuit Interface

*/

typedef struct

{

__IO uint32_t CR1; /*!< FMPI2C Control register 1, Address offset: 0x00 */

__IO uint32_t CR2; /*!< FMPI2C Control register 2, Address offset: 0x04 */

__IO uint32_t OAR1; /*!< FMPI2C Own address 1 register, Address offset: 0x08 */

__IO uint32_t OAR2; /*!< FMPI2C Own address 2 register, Address offset: 0x0C */

__IO uint32_t TIMINGR; /*!< FMPI2C Timing register, Address offset: 0x10 */

__IO uint32_t TIMEOUTR; /*!< FMPI2C Timeout register, Address offset: 0x14 */

__IO uint32_t ISR; /*!< FMPI2C Interrupt and status register, Address offset: 0x18 */

__IO uint32_t ICR; /*!< FMPI2C Interrupt clear register, Address offset: 0x1C */

__IO uint32_t PECR; /*!< FMPI2C PEC register, Address offset: 0x20 */

__IO uint32_t RXDR; /*!< FMPI2C Receive data register, Address offset: 0x24 */

__IO uint32_t TXDR; /*!< FMPI2C Transmit data register, Address offset: 0x28 */

} FMPI2C_TypeDef;

/**

* @brief Independent WATCHDOG

*/

typedef struct

{

__IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */

__IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */

__IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */

__IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */

} IWDG_TypeDef;

/**

* @brief Power Control

*/

typedef struct

{

__IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */

__IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */

} PWR_TypeDef;

/**

* @brief Reset and Clock Control

*/

typedef struct

{

__IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */

__IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */

__IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */

__IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */

__IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */

uint32_t RESERVED0[3]; /*!< Reserved, 0x14-0x1C */

__IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */

__IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */

uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */

__IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */

uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */

__IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */

__IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */

uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */

__IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */

uint32_t RESERVED4[3]; /*!< Reserved, 0x54-0x5C */

__IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */

__IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */

uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */

__IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */

__IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */

uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */

__IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */

uint32_t RESERVED7[2]; /*!< Reserved, 0x84-0x88 */

__IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */

__IO uint32_t CKGATENR; /*!< RCC Clocks Gated ENable Register, Address offset: 0x90 */

__IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x94 */

} RCC_TypeDef;

/**

* @brief Real-Time Clock

*/

typedef struct

{

__IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */

__IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */

__IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */

__IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */

__IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */

__IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */

__IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */

__IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */

__IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */

__IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */

__IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */

__IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */

__IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */

__IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */

__IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */

__IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */

__IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */

__IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */

__IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */

uint32_t RESERVED7; /*!< Reserved, 0x4C */

__IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */

__IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */

__IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */

__IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */

__IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */

__IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */

__IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */

__IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */

__IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */

__IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */

__IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */

__IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */

__IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */

__IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */

__IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */

__IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */

__IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */

__IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */

__IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */

__IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */

} RTC_TypeDef;

/**

* @brief Serial Peripheral Interface

*/

typedef struct

{

__IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */

__IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */

__IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */

__IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */

__IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */

__IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */

__IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */

__IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */

__IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */

} SPI_TypeDef;

/**

* @brief TIM

*/

typedef struct

{

__IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */

__IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */

__IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */

__IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */

__IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */

__IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */

__IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */

__IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */

__IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */

__IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */

__IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */

__IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */

__IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */

__IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */

__IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */

__IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */

__IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */

__IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */

__IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */

__IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */

__IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */

} TIM_TypeDef;

/**

* @brief Universal Synchronous Asynchronous Receiver Transmitter

*/

typedef struct

{

__IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */

__IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */

__IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */

__IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */

__IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */

__IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */

__IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */

} USART_TypeDef;

/**

* @brief Window WATCHDOG

*/

typedef struct

{

__IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */

__IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */

__IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */

} WWDG_TypeDef;

/**

* @brief RNG

*/

typedef struct

{

__IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */

__IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */

__IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */

} RNG_TypeDef;

/**

* @brief LPTIMER

*/

typedef struct

{

__IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */

__IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */

__IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */

__IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */

__IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */

__IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */

__IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */

__IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */

__IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */

} LPTIM_TypeDef;

/**

* @brief Peripheral_memory_map

*/

#define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */

#define SRAM1_BASE 0x20000000U /*!< SRAM1(32 KB) base address in the alias region */

#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */

#define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(32 KB) base address in the bit-band region */

#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */

#define FLASH_END 0x0801FFFFU /*!< FLASH end address */

/* Legacy defines */

#define SRAM_BASE SRAM1_BASE

#define SRAM_BB_BASE SRAM1_BB_BASE

/*!< Peripheral memory map */

#define APB1PERIPH_BASE PERIPH_BASE

#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)

#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)

/*!< APB1 peripherals */

#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)

#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)

#define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400U)

#define RTC_BASE (APB1PERIPH_BASE + 0x2800U)

#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)

#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)

#define USART2_BASE (APB1PERIPH_BASE + 0x4400U)

#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)

#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)

#define FMPI2C1_BASE (APB1PERIPH_BASE + 0x6000U)

#define PWR_BASE (APB1PERIPH_BASE + 0x7000U)

#define DAC_BASE (APB1PERIPH_BASE + 0x7400U)

/*!< APB2 peripherals */

#define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)

#define USART1_BASE (APB2PERIPH_BASE + 0x1000U)

#define USART6_BASE (APB2PERIPH_BASE + 0x1400U)

#define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)

#define ADC_BASE (APB2PERIPH_BASE + 0x2300U)

#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)

#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)

#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)

#define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)

#define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)

/*!< AHB1 peripherals */

#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)

#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)

#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)

#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)

#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)

#define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)

#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)

#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)

#define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)

#define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)

#define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)

#define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)

#define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)

#define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)

#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)

#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)

#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)

#define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)

#define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)

#define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)

#define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)

#define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)

#define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)

#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)

#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)

#define RNG_BASE (PERIPH_BASE + 0x80000U)

/* Debug MCU registers base address */

#define DBGMCU_BASE 0xE0042000U

/**

* @}

*/

/** @addtogroup Peripheral_declaration

* @{

*/

#define TIM5 ((TIM_TypeDef *) TIM5_BASE)

#define TIM6 ((TIM_TypeDef *) TIM6_BASE)

#define RTC ((RTC_TypeDef *) RTC_BASE)

#define WWDG ((WWDG_TypeDef *) WWDG_BASE)

#define IWDG ((IWDG_TypeDef *) IWDG_BASE)

#define USART2 ((USART_TypeDef *) USART2_BASE)

#define I2C1 ((I2C_TypeDef *) I2C1_BASE)

#define I2C2 ((I2C_TypeDef *) I2C2_BASE)

#define FMPI2C1 ((FMPI2C_TypeDef *) FMPI2C1_BASE)

#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)

#define PWR ((PWR_TypeDef *) PWR_BASE)

#define DAC ((DAC_TypeDef *) DAC_BASE)

#define TIM1 ((TIM_TypeDef *) TIM1_BASE)

#define USART1 ((USART_TypeDef *) USART1_BASE)

#define USART6 ((USART_TypeDef *) USART6_BASE)

#define ADC ((ADC_Common_TypeDef *) ADC_BASE)

#define ADC1 ((ADC_TypeDef *) ADC1_BASE)

#define SPI1 ((SPI_TypeDef *) SPI1_BASE)

#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)

#define EXTI ((EXTI_TypeDef *) EXTI_BASE)

#define TIM9 ((TIM_TypeDef *) TIM9_BASE)

#define TIM11 ((TIM_TypeDef *) TIM11_BASE)

#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)

#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)

#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)

#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)

#define CRC ((CRC_TypeDef *) CRC_BASE)

#define RCC ((RCC_TypeDef *) RCC_BASE)

#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)

#define DMA1 ((DMA_TypeDef *) DMA1_BASE)

#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)

#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)

#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)

#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)

#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)

#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)

#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)

#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)

#define DMA2 ((DMA_TypeDef *) DMA2_BASE)

#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)

#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)

#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)

#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)

#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)

#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)

#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)

#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)

#define RNG ((RNG_TypeDef *) RNG_BASE)

#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)

/**

* @}

*/

/** @addtogroup Exported_constants

* @{

*/

/** @addtogroup Peripheral_Registers_Bits_Definition

* @{

*/

/******************************************************************************/

/* Peripheral Registers_Bits_Definition */

/******************************************************************************/

/******************************************************************************/

/* */

/* Analog to Digital Converter */

/* */

/******************************************************************************/

/******************** Bit definition for ADC_SR register ********************/

#define ADC_SR_AWD 0x00000001U /*!<Analog watchdog flag */

#define ADC_SR_EOC 0x00000002U /*!<End of conversion */

#define ADC_SR_JEOC 0x00000004U /*!<Injected channel end of conversion */

#define ADC_SR_JSTRT 0x00000008U /*!<Injected channel Start flag */

#define ADC_SR_STRT 0x00000010U /*!<Regular channel Start flag */

#define ADC_SR_OVR 0x00000020U /*!<Overrun flag */

/******************* Bit definition for ADC_CR1 register ********************/

#define ADC_CR1_AWDCH 0x0000001FU /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */

#define ADC_CR1_AWDCH_0 0x00000001U /*!<Bit 0 */

#define ADC_CR1_AWDCH_1 0x00000002U /*!<Bit 1 */

#define ADC_CR1_AWDCH_2 0x00000004U /*!<Bit 2 */

#define ADC_CR1_AWDCH_3 0x00000008U /*!<Bit 3 */

#define ADC_CR1_AWDCH_4 0x00000010U /*!<Bit 4 */

#define ADC_CR1_EOCIE 0x00000020U /*!<Interrupt enable for EOC */

#define ADC_CR1_AWDIE 0x00000040U /*!<AAnalog Watchdog interrupt enable */

#define ADC_CR1_JEOCIE 0x00000080U /*!<Interrupt enable for injected channels */

#define ADC_CR1_SCAN 0x00000100U /*!<Scan mode */

#define ADC_CR1_AWDSGL 0x00000200U /*!<Enable the watchdog on a single channel in scan mode */

#define ADC_CR1_JAUTO 0x00000400U /*!<Automatic injected group conversion */

#define ADC_CR1_DISCEN 0x00000800U /*!<Discontinuous mode on regular channels */

#define ADC_CR1_JDISCEN 0x00001000U /*!<Discontinuous mode on injected channels */

#define ADC_CR1_DISCNUM 0x0000E000U /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */

#define ADC_CR1_DISCNUM_0 0x00002000U /*!<Bit 0 */

#define ADC_CR1_DISCNUM_1 0x00004000U /*!<Bit 1 */

#define ADC_CR1_DISCNUM_2 0x00008000U /*!<Bit 2 */

#define ADC_CR1_JAWDEN 0x00400000U /*!<Analog watchdog enable on injected channels */

#define ADC_CR1_AWDEN 0x00800000U /*!<Analog watchdog enable on regular channels */

#define ADC_CR1_RES 0x03000000U /*!<RES[2:0] bits (Resolution) */

#define ADC_CR1_RES_0 0x01000000U /*!<Bit 0 */

#define ADC_CR1_RES_1 0x02000000U /*!<Bit 1 */

#define ADC_CR1_OVRIE 0x04000000U /*!<overrun interrupt enable */

/******************* Bit definition for ADC_CR2 register ********************/

#define ADC_CR2_ADON 0x00000001U /*!<A/D Converter ON / OFF */

#define ADC_CR2_CONT 0x00000002U /*!<Continuous Conversion */

#define ADC_CR2_DMA 0x00000100U /*!<Direct Memory access mode */

#define ADC_CR2_DDS 0x00000200U /*!<DMA disable selection (Single ADC) */

#define ADC_CR2_EOCS 0x00000400U /*!<End of conversion selection */

#define ADC_CR2_ALIGN 0x00000800U /*!<Data Alignment */

#define ADC_CR2_JEXTSEL 0x000F0000U /*!<JEXTSEL[3:0] bits (External event select for injected group) */

#define ADC_CR2_JEXTSEL_0 0x00010000U /*!<Bit 0 */

#define ADC_CR2_JEXTSEL_1 0x00020000U /*!<Bit 1 */

#define ADC_CR2_JEXTSEL_2 0x00040000U /*!<Bit 2 */

#define ADC_CR2_JEXTSEL_3 0x00080000U /*!<Bit 3 */

#define ADC_CR2_JEXTEN 0x00300000U /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */

#define ADC_CR2_JEXTEN_0 0x00100000U /*!<Bit 0 */

#define ADC_CR2_JEXTEN_1 0x00200000U /*!<Bit 1 */

#define ADC_CR2_JSWSTART 0x00400000U /*!<Start Conversion of injected channels */

#define ADC_CR2_EXTSEL 0x0F000000U /*!<EXTSEL[3:0] bits (External Event Select for regular group) */

#define ADC_CR2_EXTSEL_0 0x01000000U /*!<Bit 0 */

#define ADC_CR2_EXTSEL_1 0x02000000U /*!<Bit 1 */

#define ADC_CR2_EXTSEL_2 0x04000000U /*!<Bit 2 */

#define ADC_CR2_EXTSEL_3 0x08000000U /*!<Bit 3 */

#define ADC_CR2_EXTEN 0x30000000U /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */

#define ADC_CR2_EXTEN_0 0x10000000U /*!<Bit 0 */

#define ADC_CR2_EXTEN_1 0x20000000U /*!<Bit 1 */

#define ADC_CR2_SWSTART 0x40000000U /*!<Start Conversion of regular channels */

/****************** Bit definition for ADC_SMPR1 register *******************/

#define ADC_SMPR1_SMP10 0x00000007U /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */

#define ADC_SMPR1_SMP10_0 0x00000001U /*!<Bit 0 */

#define ADC_SMPR1_SMP10_1 0x00000002U /*!<Bit 1 */

#define ADC_SMPR1_SMP10_2 0x00000004U /*!<Bit 2 */

#define ADC_SMPR1_SMP11 0x00000038U /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */

#define ADC_SMPR1_SMP11_0 0x00000008U /*!<Bit 0 */

#define ADC_SMPR1_SMP11_1 0x00000010U /*!<Bit 1 */

#define ADC_SMPR1_SMP11_2 0x00000020U /*!<Bit 2 */

#define ADC_SMPR1_SMP12 0x000001C0U /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */

#define ADC_SMPR1_SMP12_0 0x00000040U /*!<Bit 0 */

#define ADC_SMPR1_SMP12_1 0x00000080U /*!<Bit 1 */

#define ADC_SMPR1_SMP12_2 0x00000100U /*!<Bit 2 */

#define ADC_SMPR1_SMP13 0x00000E00U /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */

#define ADC_SMPR1_SMP13_0 0x00000200U /*!<Bit 0 */

#define ADC_SMPR1_SMP13_1 0x00000400U /*!<Bit 1 */

#define ADC_SMPR1_SMP13_2 0x00000800U /*!<Bit 2 */

#define ADC_SMPR1_SMP14 0x00007000U /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */

#define ADC_SMPR1_SMP14_0 0x00001000U /*!<Bit 0 */

#define ADC_SMPR1_SMP14_1 0x00002000U /*!<Bit 1 */

#define ADC_SMPR1_SMP14_2 0x00004000U /*!<Bit 2 */

#define ADC_SMPR1_SMP15 0x00038000U /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */

#define ADC_SMPR1_SMP15_0 0x00008000U /*!<Bit 0 */

#define ADC_SMPR1_SMP15_1 0x00010000U /*!<Bit 1 */

#define ADC_SMPR1_SMP15_2 0x00020000U /*!<Bit 2 */

#define ADC_SMPR1_SMP16 0x001C0000U /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */

#define ADC_SMPR1_SMP16_0 0x00040000U /*!<Bit 0 */

#define ADC_SMPR1_SMP16_1 0x00080000U /*!<Bit 1 */

#define ADC_SMPR1_SMP16_2 0x00100000U /*!<Bit 2 */

#define ADC_SMPR1_SMP17 0x00E00000U /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */

#define ADC_SMPR1_SMP17_0 0x00200000U /*!<Bit 0 */

#define ADC_SMPR1_SMP17_1 0x00400000U /*!<Bit 1 */

#define ADC_SMPR1_SMP17_2 0x00800000U /*!<Bit 2 */

#define ADC_SMPR1_SMP18 0x07000000U /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */

#define ADC_SMPR1_SMP18_0 0x01000000U /*!<Bit 0 */

#define ADC_SMPR1_SMP18_1 0x02000000U /*!<Bit 1 */

#define ADC_SMPR1_SMP18_2 0x04000000U /*!<Bit 2 */

/****************** Bit definition for ADC_SMPR2 register *******************/

#define ADC_SMPR2_SMP0 0x00000007U /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */

#define ADC_SMPR2_SMP0_0 0x00000001U /*!<Bit 0 */

#define ADC_SMPR2_SMP0_1 0x00000002U /*!<Bit 1 */

#define ADC_SMPR2_SMP0_2 0x00000004U /*!<Bit 2 */

#define ADC_SMPR2_SMP1 0x00000038U /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */

#define ADC_SMPR2_SMP1_0 0x00000008U /*!<Bit 0 */

#define ADC_SMPR2_SMP1_1 0x00000010U /*!<Bit 1 */

#define ADC_SMPR2_SMP1_2 0x00000020U /*!<Bit 2 */

#define ADC_SMPR2_SMP2 0x000001C0U /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */

#define ADC_SMPR2_SMP2_0 0x00000040U /*!<Bit 0 */

#define ADC_SMPR2_SMP2_1 0x00000080U /*!<Bit 1 */

#define ADC_SMPR2_SMP2_2 0x00000100U /*!<Bit 2 */

#define ADC_SMPR2_SMP3 0x00000E00U /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */

#define ADC_SMPR2_SMP3_0 0x00000200U /*!<Bit 0 */

#define ADC_SMPR2_SMP3_1 0x00000400U /*!<Bit 1 */

#define ADC_SMPR2_SMP3_2 0x00000800U /*!<Bit 2 */

#define ADC_SMPR2_SMP4 0x00007000U /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */

#define ADC_SMPR2_SMP4_0 0x00001000U /*!<Bit 0 */

#define ADC_SMPR2_SMP4_1 0x00002000U /*!<Bit 1 */

#define ADC_SMPR2_SMP4_2 0x00004000U /*!<Bit 2 */

#define ADC_SMPR2_SMP5 0x00038000U /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */

#define ADC_SMPR2_SMP5_0 0x00008000U /*!<Bit 0 */

#define ADC_SMPR2_SMP5_1 0x00010000U /*!<Bit 1 */

#define ADC_SMPR2_SMP5_2 0x00020000U /*!<Bit 2 */

#define ADC_SMPR2_SMP6 0x001C0000U /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */

#define ADC_SMPR2_SMP6_0 0x00040000U /*!<Bit 0 */

#define ADC_SMPR2_SMP6_1 0x00080000U /*!<Bit 1 */

#define ADC_SMPR2_SMP6_2 0x00100000U /*!<Bit 2 */

#define ADC_SMPR2_SMP7 0x00E00000U /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */

#define ADC_SMPR2_SMP7_0 0x00200000U /*!<Bit 0 */

#define ADC_SMPR2_SMP7_1 0x00400000U /*!<Bit 1 */

#define ADC_SMPR2_SMP7_2 0x00800000U /*!<Bit 2 */

#define ADC_SMPR2_SMP8 0x07000000U /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */

#define ADC_SMPR2_SMP8_0 0x01000000U /*!<Bit 0 */

#define ADC_SMPR2_SMP8_1 0x02000000U /*!<Bit 1 */

#define ADC_SMPR2_SMP8_2 0x04000000U /*!<Bit 2 */

#define ADC_SMPR2_SMP9 0x38000000U /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */

#define ADC_SMPR2_SMP9_0 0x08000000U /*!<Bit 0 */

#define ADC_SMPR2_SMP9_1 0x10000000U /*!<Bit 1 */

#define ADC_SMPR2_SMP9_2 0x20000000U /*!<Bit 2 */

/****************** Bit definition for ADC_JOFR1 register *******************/

#define ADC_JOFR1_JOFFSET1 0x0FFFU /*!<Data offset for injected channel 1 */

/****************** Bit definition for ADC_JOFR2 register *******************/

#define ADC_JOFR2_JOFFSET2 0x0FFFU /*!<Data offset for injected channel 2 */

/****************** Bit definition for ADC_JOFR3 register *******************/

#define ADC_JOFR3_JOFFSET3 0x0FFFU /*!<Data offset for injected channel 3 */

/****************** Bit definition for ADC_JOFR4 register *******************/

#define ADC_JOFR4_JOFFSET4 0x0FFFU /*!<Data offset for injected channel 4 */

/******************* Bit definition for ADC_HTR register ********************/

#define ADC_HTR_HT 0x0FFFU /*!<Analog watchdog high threshold */

/******************* Bit definition for ADC_LTR register ********************/

#define ADC_LTR_LT 0x0FFFU /*!<Analog watchdog low threshold */

/******************* Bit definition for ADC_SQR1 register *******************/

#define ADC_SQR1_SQ13 0x0000001FU /*!<SQ13[4:0] bits (13th conversion in regular sequence) */

#define ADC_SQR1_SQ13_0 0x00000001U /*!<Bit 0 */

#define ADC_SQR1_SQ13_1 0x00000002U /*!<Bit 1 */

#define ADC_SQR1_SQ13_2 0x00000004U /*!<Bit 2 */

#define ADC_SQR1_SQ13_3 0x00000008U /*!<Bit 3 */

#define ADC_SQR1_SQ13_4 0x00000010U /*!<Bit 4 */

#define ADC_SQR1_SQ14 0x000003E0U /*!<SQ14[4:0] bits (14th conversion in regular sequence) */

#define ADC_SQR1_SQ14_0 0x00000020U /*!<Bit 0 */

#define ADC_SQR1_SQ14_1 0x00000040U /*!<Bit 1 */

#define ADC_SQR1_SQ14_2 0x00000080U /*!<Bit 2 */

#define ADC_SQR1_SQ14_3 0x00000100U /*!<Bit 3 */

#define ADC_SQR1_SQ14_4 0x00000200U /*!<Bit 4 */

#define ADC_SQR1_SQ15 0x00007C00U /*!<SQ15[4:0] bits (15th conversion in regular sequence) */

#define ADC_SQR1_SQ15_0 0x00000400U /*!<Bit 0 */

#define ADC_SQR1_SQ15_1 0x00000800U /*!<Bit 1 */

#define ADC_SQR1_SQ15_2 0x00001000U /*!<Bit 2 */

#define ADC_SQR1_SQ15_3 0x00002000U /*!<Bit 3 */

#define ADC_SQR1_SQ15_4 0x00004000U /*!<Bit 4 */

#define ADC_SQR1_SQ16 0x000F8000U /*!<SQ16[4:0] bits (16th conversion in regular sequence) */

#define ADC_SQR1_SQ16_0 0x00008000U /*!<Bit 0 */

#define ADC_SQR1_SQ16_1 0x00010000U /*!<Bit 1 */

#define ADC_SQR1_SQ16_2 0x00020000U /*!<Bit 2 */

#define ADC_SQR1_SQ16_3 0x00040000U /*!<Bit 3 */

#define ADC_SQR1_SQ16_4 0x00080000U /*!<Bit 4 */

#define ADC_SQR1_L 0x00F00000U /*!<L[3:0] bits (Regular channel sequence length) */

#define ADC_SQR1_L_0 0x00100000U /*!<Bit 0 */

#define ADC_SQR1_L_1 0x00200000U /*!<Bit 1 */

#define ADC_SQR1_L_2 0x00400000U /*!<Bit 2 */

#define ADC_SQR1_L_3 0x00800000U /*!<Bit 3 */

/******************* Bit definition for ADC_SQR2 register *******************/

#define ADC_SQR2_SQ7 0x0000001FU /*!<SQ7[4:0] bits (7th conversion in regular sequence) */

#define ADC_SQR2_SQ7_0 0x00000001U /*!<Bit 0 */

#define ADC_SQR2_SQ7_1 0x00000002U /*!<Bit 1 */

#define ADC_SQR2_SQ7_2 0x00000004U /*!<Bit 2 */

#define ADC_SQR2_SQ7_3 0x00000008U /*!<Bit 3 */

#define ADC_SQR2_SQ7_4 0x00000010U /*!<Bit 4 */

#define ADC_SQR2_SQ8 0x000003E0U /*!<SQ8[4:0] bits (8th conversion in regular sequence) */

#define ADC_SQR2_SQ8_0 0x00000020U /*!<Bit 0 */

#define ADC_SQR2_SQ8_1 0x00000040U /*!<Bit 1 */

#define ADC_SQR2_SQ8_2 0x00000080U /*!<Bit 2 */

#define ADC_SQR2_SQ8_3 0x00000100U /*!<Bit 3 */

#define ADC_SQR2_SQ8_4 0x00000200U /*!<Bit 4 */

#define ADC_SQR2_SQ9 0x00007C00U /*!<SQ9[4:0] bits (9th conversion in regular sequence) */

#define ADC_SQR2_SQ9_0 0x00000400U /*!<Bit 0 */

#define ADC_SQR2_SQ9_1 0x00000800U /*!<Bit 1 */

#define ADC_SQR2_SQ9_2 0x00001000U /*!<Bit 2 */

#define ADC_SQR2_SQ9_3 0x00002000U /*!<Bit 3 */

#define ADC_SQR2_SQ9_4 0x00004000U /*!<Bit 4 */

#define ADC_SQR2_SQ10 0x000F8000U /*!<SQ10[4:0] bits (10th conversion in regular sequence) */

#define ADC_SQR2_SQ10_0 0x00008000U /*!<Bit 0 */

#define ADC_SQR2_SQ10_1 0x00010000U /*!<Bit 1 */

#define ADC_SQR2_SQ10_2 0x00020000U /*!<Bit 2 */

#define ADC_SQR2_SQ10_3 0x00040000U /*!<Bit 3 */

#define ADC_SQR2_SQ10_4 0x00080000U /*!<Bit 4 */

#define ADC_SQR2_SQ11 0x01F00000U /*!<SQ11[4:0] bits (11th conversion in regular sequence) */

#define ADC_SQR2_SQ11_0 0x00100000U /*!<Bit 0 */

#define ADC_SQR2_SQ11_1 0x00200000U /*!<Bit 1 */

#define ADC_SQR2_SQ11_2 0x00400000U /*!<Bit 2 */

#define ADC_SQR2_SQ11_3 0x00800000U /*!<Bit 3 */

#define ADC_SQR2_SQ11_4 0x01000000U /*!<Bit 4 */

#define ADC_SQR2_SQ12 0x3E000000U /*!<SQ12[4:0] bits (12th conversion in regular sequence) */

#define ADC_SQR2_SQ12_0 0x02000000U /*!<Bit 0 */

#define ADC_SQR2_SQ12_1 0x04000000U /*!<Bit 1 */

#define ADC_SQR2_SQ12_2 0x08000000U /*!<Bit 2 */

#define ADC_SQR2_SQ12_3 0x10000000U /*!<Bit 3 */

#define ADC_SQR2_SQ12_4 0x20000000U /*!<Bit 4 */

/******************* Bit definition for ADC_SQR3 register *******************/

#define ADC_SQR3_SQ1 0x0000001FU /*!<SQ1[4:0] bits (1st conversion in regular sequence) */

#define ADC_SQR3_SQ1_0 0x00000001U /*!<Bit 0 */

#define ADC_SQR3_SQ1_1 0x00000002U /*!<Bit 1 */

#define ADC_SQR3_SQ1_2 0x00000004U /*!<Bit 2 */

#define ADC_SQR3_SQ1_3 0x00000008U /*!<Bit 3 */

#define ADC_SQR3_SQ1_4 0x00000010U /*!<Bit 4 */

#define ADC_SQR3_SQ2 0x000003E0U /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */

#define ADC_SQR3_SQ2_0 0x00000020U /*!<Bit 0 */

#define ADC_SQR3_SQ2_1 0x00000040U /*!<Bit 1 */

#define ADC_SQR3_SQ2_2 0x00000080U /*!<Bit 2 */

#define ADC_SQR3_SQ2_3 0x00000100U /*!<Bit 3 */

#define ADC_SQR3_SQ2_4 0x00000200U /*!<Bit 4 */

#define ADC_SQR3_SQ3 0x00007C00U /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */

#define ADC_SQR3_SQ3_0 0x00000400U /*!<Bit 0 */

#define ADC_SQR3_SQ3_1 0x00000800U /*!<Bit 1 */

#define ADC_SQR3_SQ3_2 0x00001000U /*!<Bit 2 */

#define ADC_SQR3_SQ3_3 0x00002000U /*!<Bit 3 */

#define ADC_SQR3_SQ3_4 0x00004000U /*!<Bit 4 */

#define ADC_SQR3_SQ4 0x000F8000U /*!<SQ4[4:0] bits (4th conversion in regular sequence) */

#define ADC_SQR3_SQ4_0 0x00008000U /*!<Bit 0 */

#define ADC_SQR3_SQ4_1 0x00010000U /*!<Bit 1 */

#define ADC_SQR3_SQ4_2 0x00020000U /*!<Bit 2 */

#define ADC_SQR3_SQ4_3 0x00040000U /*!<Bit 3 */

#define ADC_SQR3_SQ4_4 0x00080000U /*!<Bit 4 */

#define ADC_SQR3_SQ5 0x01F00000U /*!<SQ5[4:0] bits (5th conversion in regular sequence) */

#define ADC_SQR3_SQ5_0 0x00100000U /*!<Bit 0 */

#define ADC_SQR3_SQ5_1 0x00200000U /*!<Bit 1 */

#define ADC_SQR3_SQ5_2 0x00400000U /*!<Bit 2 */

#define ADC_SQR3_SQ5_3 0x00800000U /*!<Bit 3 */

#define ADC_SQR3_SQ5_4 0x01000000U /*!<Bit 4 */

#define ADC_SQR3_SQ6 0x3E000000U /*!<SQ6[4:0] bits (6th conversion in regular sequence) */

#define ADC_SQR3_SQ6_0 0x02000000U /*!<Bit 0 */

#define ADC_SQR3_SQ6_1 0x04000000U /*!<Bit 1 */

#define ADC_SQR3_SQ6_2 0x08000000U /*!<Bit 2 */

#define ADC_SQR3_SQ6_3 0x10000000U /*!<Bit 3 */

#define ADC_SQR3_SQ6_4 0x20000000U /*!<Bit 4 */

/******************* Bit definition for ADC_JSQR register *******************/

#define ADC_JSQR_JSQ1 0x0000001FU /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */

#define ADC_JSQR_JSQ1_0 0x00000001U /*!<Bit 0 */

#define ADC_JSQR_JSQ1_1 0x00000002U /*!<Bit 1 */

#define ADC_JSQR_JSQ1_2 0x00000004U /*!<Bit 2 */

#define ADC_JSQR_JSQ1_3 0x00000008U /*!<Bit 3 */

#define ADC_JSQR_JSQ1_4 0x00000010U /*!<Bit 4 */

#define ADC_JSQR_JSQ2 0x000003E0U /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */

#define ADC_JSQR_JSQ2_0 0x00000020U /*!<Bit 0 */