stmhal: Port of f4 hal commit c568a2b to f7 hal

dhylands · dpgeorge · commit af9d885f8cbb · 2015-08-03T00:49:35.000+01:00
diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_rcc.c b/stmhal/hal/f7/src/stm32f7xx_hal_rcc.c
@@ -981,7 +981,12 @@ uint32_t HAL_RCC_GetSysClockFreq(void)
       if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI)
       {
         /* HSE used as PLL clock source */
-        pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
+        //pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
+        // dpgeorge: Adjust the way the arithmetic is done so it retains
+        // precision for the case that pllm doesn't evenly divide HSE_VALUE.
+        // Must be sure not to overflow, so divide by 4 first.  HSE_VALUE
+        // should be a multiple of 4 (being a multiple of 100 is enough).
+        pllvco = ((HSE_VALUE / 4) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN))) / pllm * 4;
       }
       else
       {

Original file line number	Diff line number	Diff line change
`@@ -981,7 +981,12 @@ uint32_t HAL_RCC_GetSysClockFreq(void)`
`981`	`981`	`if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI)`
`982`	`982`	`{`
`983`	`983`	`/* HSE used as PLL clock source */`
`984`		`- pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));`
	`984`	`+ //pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));`
	`985`	`+ // dpgeorge: Adjust the way the arithmetic is done so it retains`
	`986`	`+ // precision for the case that pllm doesn't evenly divide HSE_VALUE.`
	`987`	`+ // Must be sure not to overflow, so divide by 4 first. HSE_VALUE`
	`988`	`+ // should be a multiple of 4 (being a multiple of 100 is enough).`
	`989`	`+ pllvco = ((HSE_VALUE / 4) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN))) / pllm * 4;`
`985`	`990`	`}`
`986`	`991`	`else`
`987`	`992`	`{`